![David Brownell](/assets/img/avatar_default.png)
Disable some dubious "early" USB handoff code that allegedly works around bugs on some systems (we don't know which ones) but rudely breaks some others. Also make the kernel warnings reporting BIOS handoff problems be more useful, reporting the register whose value displays the trouble. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
352 lines
9.8 KiB
C
352 lines
9.8 KiB
C
/*
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* This file contains code to reset and initialize USB host controllers.
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* Some of it includes work-arounds for PCI hardware and BIOS quirks.
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* It may need to run early during booting -- before USB would normally
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* initialize -- to ensure that Linux doesn't use any legacy modes.
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*
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* Copyright (c) 1999 Martin Mares <mj@ucw.cz>
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* (and others)
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*/
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#include <linux/config.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/acpi.h>
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#define UHCI_USBLEGSUP 0xc0 /* legacy support */
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#define UHCI_USBCMD 0 /* command register */
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#define UHCI_USBINTR 4 /* interrupt register */
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#define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */
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#define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */
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#define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */
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#define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */
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#define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */
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#define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */
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#define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */
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#define OHCI_CONTROL 0x04
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#define OHCI_CMDSTATUS 0x08
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#define OHCI_INTRSTATUS 0x0c
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#define OHCI_INTRENABLE 0x10
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#define OHCI_INTRDISABLE 0x14
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#define OHCI_OCR (1 << 3) /* ownership change request */
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#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
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#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
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#define OHCI_INTR_OC (1 << 30) /* ownership change */
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#define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
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#define EHCI_USBCMD 0 /* command register */
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#define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
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#define EHCI_USBSTS 4 /* status register */
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#define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
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#define EHCI_USBINTR 8 /* interrupt register */
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#define EHCI_USBLEGSUP 0 /* legacy support register */
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#define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
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#define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
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#define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
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#define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
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/*
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* Make sure the controller is completely inactive, unable to
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* generate interrupts or do DMA.
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*/
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void uhci_reset_hc(struct pci_dev *pdev, unsigned long base)
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{
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/* Turn off PIRQ enable and SMI enable. (This also turns off the
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* BIOS's USB Legacy Support.) Turn off all the R/WC bits too.
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*/
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pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC);
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/* Reset the HC - this will force us to get a
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* new notification of any already connected
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* ports due to the virtual disconnect that it
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* implies.
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*/
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outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD);
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mb();
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udelay(5);
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if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET)
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dev_warn(&pdev->dev, "HCRESET not completed yet!\n");
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/* Just to be safe, disable interrupt requests and
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* make sure the controller is stopped.
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*/
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outw(0, base + UHCI_USBINTR);
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outw(0, base + UHCI_USBCMD);
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}
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EXPORT_SYMBOL_GPL(uhci_reset_hc);
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/*
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* Initialize a controller that was newly discovered or has just been
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* resumed. In either case we can't be sure of its previous state.
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*
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* Returns: 1 if the controller was reset, 0 otherwise.
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*/
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int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base)
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{
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u16 legsup;
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unsigned int cmd, intr;
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/*
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* When restarting a suspended controller, we expect all the
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* settings to be the same as we left them:
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*
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* PIRQ and SMI disabled, no R/W bits set in USBLEGSUP;
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* Controller is stopped and configured with EGSM set;
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* No interrupts enabled except possibly Resume Detect.
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*
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* If any of these conditions are violated we do a complete reset.
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*/
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pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup);
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if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) {
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dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n",
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__FUNCTION__, legsup);
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goto reset_needed;
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}
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cmd = inw(base + UHCI_USBCMD);
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if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) ||
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!(cmd & UHCI_USBCMD_EGSM)) {
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dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n",
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__FUNCTION__, cmd);
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goto reset_needed;
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}
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intr = inw(base + UHCI_USBINTR);
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if (intr & (~UHCI_USBINTR_RESUME)) {
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dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n",
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__FUNCTION__, intr);
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goto reset_needed;
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}
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return 0;
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reset_needed:
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dev_dbg(&pdev->dev, "Performing full reset\n");
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uhci_reset_hc(pdev, base);
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return 1;
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}
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EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc);
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static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)
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{
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u16 cmd;
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return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask);
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}
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#define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO)
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#define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY)
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static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev)
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{
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unsigned long base = 0;
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int i;
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if (!pio_enabled(pdev))
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return;
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for (i = 0; i < PCI_ROM_RESOURCE; i++)
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if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
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base = pci_resource_start(pdev, i);
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break;
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}
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if (base)
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uhci_check_and_reset_hc(pdev, base);
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}
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static int __devinit mmio_resource_enabled(struct pci_dev *pdev, int idx)
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{
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return pci_resource_start(pdev, idx) && mmio_enabled(pdev);
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}
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static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
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{
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void __iomem *base;
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int wait_time;
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u32 control;
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if (!mmio_resource_enabled(pdev, 0))
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return;
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base = ioremap_nocache(pci_resource_start(pdev, 0),
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pci_resource_len(pdev, 0));
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if (base == NULL) return;
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/* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
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#ifndef __hppa__
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control = readl(base + OHCI_CONTROL);
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if (control & OHCI_CTRL_IR) {
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wait_time = 500; /* arbitrary; 5 seconds */
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writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
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writel(OHCI_OCR, base + OHCI_CMDSTATUS);
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while (wait_time > 0 &&
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readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
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wait_time -= 10;
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msleep(10);
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}
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if (wait_time <= 0)
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printk(KERN_WARNING "%s %s: BIOS handoff "
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"failed (BIOS bug ?) %08x\n",
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pdev->dev.bus_id, "OHCI",
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readl(base + OHCI_CONTROL));
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/* reset controller, preserving RWC */
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writel(control & OHCI_CTRL_RWC, base + OHCI_CONTROL);
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}
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#endif
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/*
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* disable interrupts
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*/
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writel(~(u32)0, base + OHCI_INTRDISABLE);
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writel(~(u32)0, base + OHCI_INTRSTATUS);
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iounmap(base);
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}
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static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
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{
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int wait_time, delta;
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void __iomem *base, *op_reg_base;
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u32 hcc_params, val;
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u8 offset, cap_length;
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int count = 256/4;
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if (!mmio_resource_enabled(pdev, 0))
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return;
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base = ioremap_nocache(pci_resource_start(pdev, 0),
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pci_resource_len(pdev, 0));
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if (base == NULL) return;
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cap_length = readb(base);
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op_reg_base = base + cap_length;
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/* EHCI 0.96 and later may have "extended capabilities"
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* spec section 5.1 explains the bios handoff, e.g. for
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* booting from USB disk or using a usb keyboard
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*/
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hcc_params = readl(base + EHCI_HCC_PARAMS);
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offset = (hcc_params >> 8) & 0xff;
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while (offset && count--) {
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u32 cap;
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int msec;
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pci_read_config_dword(pdev, offset, &cap);
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switch (cap & 0xff) {
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case 1: /* BIOS/SMM/... handoff support */
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if ((cap & EHCI_USBLEGSUP_BIOS)) {
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pr_debug("%s %s: BIOS handoff\n",
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pdev->dev.bus_id, "EHCI");
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#if 0
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/* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on,
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* but that seems dubious in general (the BIOS left it off intentionally)
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* and is known to prevent some systems from booting. so we won't do this
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* unless maybe we can determine when we're on a system that needs SMI forced.
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*/
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/* BIOS workaround (?): be sure the
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* pre-Linux code receives the SMI
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*/
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pci_read_config_dword(pdev,
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offset + EHCI_USBLEGCTLSTS,
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&val);
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pci_write_config_dword(pdev,
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offset + EHCI_USBLEGCTLSTS,
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val | EHCI_USBLEGCTLSTS_SOOE);
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#endif
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}
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/* always say Linux will own the hardware
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* by setting EHCI_USBLEGSUP_OS.
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*/
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pci_write_config_byte(pdev, offset + 3, 1);
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/* if boot firmware now owns EHCI, spin till
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* it hands it over.
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*/
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msec = 5000;
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while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
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msleep(10);
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msec -= 10;
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pci_read_config_dword(pdev, offset, &cap);
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}
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if (cap & EHCI_USBLEGSUP_BIOS) {
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/* well, possibly buggy BIOS... try to shut
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* it down, and hope nothing goes too wrong
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*/
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printk(KERN_WARNING "%s %s: BIOS handoff "
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"failed (BIOS bug ?) %08x\n",
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pdev->dev.bus_id, "EHCI", cap);
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pci_write_config_byte(pdev, offset + 2, 0);
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}
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/* just in case, always disable EHCI SMIs */
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pci_write_config_dword(pdev,
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offset + EHCI_USBLEGCTLSTS,
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0);
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break;
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case 0: /* illegal reserved capability */
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cap = 0;
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/* FALLTHROUGH */
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default:
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printk(KERN_WARNING "%s %s: unrecognized "
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"capability %02x\n",
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pdev->dev.bus_id, "EHCI",
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cap & 0xff);
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break;
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}
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offset = (cap >> 8) & 0xff;
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}
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if (!count)
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printk(KERN_DEBUG "%s %s: capability loop?\n",
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pdev->dev.bus_id, "EHCI");
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/*
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* halt EHCI & disable its interrupts in any case
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*/
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val = readl(op_reg_base + EHCI_USBSTS);
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if ((val & EHCI_USBSTS_HALTED) == 0) {
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val = readl(op_reg_base + EHCI_USBCMD);
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val &= ~EHCI_USBCMD_RUN;
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writel(val, op_reg_base + EHCI_USBCMD);
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wait_time = 2000;
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delta = 100;
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do {
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writel(0x3f, op_reg_base + EHCI_USBSTS);
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udelay(delta);
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wait_time -= delta;
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val = readl(op_reg_base + EHCI_USBSTS);
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if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
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break;
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}
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} while (wait_time > 0);
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}
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writel(0, op_reg_base + EHCI_USBINTR);
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writel(0x3f, op_reg_base + EHCI_USBSTS);
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iounmap(base);
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return;
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}
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static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev)
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{
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if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI)
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quirk_usb_handoff_uhci(pdev);
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else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI)
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quirk_usb_handoff_ohci(pdev);
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else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI)
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quirk_usb_disable_ehci(pdev);
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff);
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