9a8fd55899
The attached patches provides part 6 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
45 lines
1,008 B
C
45 lines
1,008 B
C
/*
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* include/asm-xtensa/sigcontext.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2003 Tensilica Inc.
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*/
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#ifndef _XTENSA_SIGCONTEXT_H
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#define _XTENSA_SIGCONTEXT_H
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#define _ASMLANGUAGE
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#include <asm/processor.h>
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#include <asm/coprocessor.h>
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struct _cpstate {
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unsigned char _cpstate[XTENSA_CP_EXTRA_SIZE];
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} __attribute__ ((aligned (XTENSA_CP_EXTRA_ALIGN)));
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struct sigcontext {
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unsigned long oldmask;
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/* CPU registers */
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unsigned long sc_pc;
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unsigned long sc_ps;
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unsigned long sc_wmask;
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unsigned long sc_windowbase;
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unsigned long sc_windowstart;
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unsigned long sc_lbeg;
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unsigned long sc_lend;
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unsigned long sc_lcount;
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unsigned long sc_sar;
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unsigned long sc_depc;
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unsigned long sc_dareg0;
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unsigned long sc_treg[4];
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unsigned long sc_areg[XCHAL_NUM_AREGS];
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struct _cpstate *sc_cpstate;
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};
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#endif /* __ASM_XTENSA_SIGCONTEXT_H */
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