![Linus Walleij](/assets/img/avatar_default.png)
Before adding a proper PCI driver in drivers/pci/host, clean out the cruft by deleting the old driver from the machine. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
247 lines
5.6 KiB
C
247 lines
5.6 KiB
C
/*
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* linux/arch/arm/mach-integrator/integrator_ap.c
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*
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* Copyright (C) 2000-2003 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/syscore_ops.h>
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#include <linux/amba/bus.h>
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/termios.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include "hardware.h"
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#include "cm.h"
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#include "common.h"
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#include "lm.h"
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/* Regmap to the AP system controller */
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static struct regmap *ap_syscon_map;
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/*
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* All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
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* is the (PA >> 12).
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*
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* Setup a VA for the Integrator interrupt controller (for header #0,
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* just for now).
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*/
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#define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
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/*
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* Logical Physical
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* f1400000 14000000 Interrupt controller
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* f1600000 16000000 UART 0
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*/
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static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
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{
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.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}
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};
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static void __init ap_map_io(void)
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{
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iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
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}
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#ifdef CONFIG_PM
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static unsigned long ic_irq_enable;
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static int irq_suspend(void)
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{
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ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
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return 0;
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}
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static void irq_resume(void)
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{
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/* disable all irq sources */
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cm_clear_irqs();
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writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
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writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
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writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
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}
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#else
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#define irq_suspend NULL
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#define irq_resume NULL
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#endif
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static struct syscore_ops irq_syscore_ops = {
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.suspend = irq_suspend,
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.resume = irq_resume,
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};
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static int __init irq_syscore_init(void)
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{
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register_syscore_ops(&irq_syscore_ops);
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return 0;
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}
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device_initcall(irq_syscore_init);
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/*
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* For the PL010 found in the Integrator/AP some of the UART control is
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* implemented in the system controller and accessed using a callback
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* from the driver.
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*/
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static void integrator_uart_set_mctrl(struct amba_device *dev,
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void __iomem *base, unsigned int mctrl)
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{
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unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
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u32 phybase = dev->res.start;
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int ret;
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if (phybase == INTEGRATOR_UART0_BASE) {
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/* UART0 */
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rts_mask = 1 << 4;
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dtr_mask = 1 << 5;
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} else {
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/* UART1 */
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rts_mask = 1 << 6;
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dtr_mask = 1 << 7;
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}
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if (mctrl & TIOCM_RTS)
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ctrlc |= rts_mask;
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else
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ctrls |= rts_mask;
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if (mctrl & TIOCM_DTR)
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ctrlc |= dtr_mask;
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else
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ctrls |= dtr_mask;
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ret = regmap_write(ap_syscon_map,
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INTEGRATOR_SC_CTRLS_OFFSET,
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ctrls);
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if (ret)
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pr_err("MODEM: unable to write PL010 UART CTRLS\n");
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ret = regmap_write(ap_syscon_map,
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INTEGRATOR_SC_CTRLC_OFFSET,
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ctrlc);
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if (ret)
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pr_err("MODEM: unable to write PL010 UART CRTLC\n");
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}
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struct amba_pl010_data ap_uart_data = {
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.set_mctrl = integrator_uart_set_mctrl,
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};
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void __init ap_init_early(void)
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{
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}
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static void __init ap_init_irq_of(void)
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{
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cm_init();
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irqchip_init();
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}
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/* For the Device Tree, add in the UART callbacks as AUXDATA */
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static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
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OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
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"uart0", &ap_uart_data),
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OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
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"uart1", &ap_uart_data),
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{ /* sentinel */ },
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};
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static const struct of_device_id ap_syscon_match[] = {
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{ .compatible = "arm,integrator-ap-syscon"},
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{ },
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};
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static void __init ap_init_of(void)
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{
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u32 sc_dec;
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struct device_node *syscon;
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int ret;
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int i;
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of_platform_default_populate(NULL, ap_auxdata_lookup, NULL);
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syscon = of_find_matching_node(NULL, ap_syscon_match);
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if (!syscon)
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return;
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ap_syscon_map = syscon_node_to_regmap(syscon);
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if (IS_ERR(ap_syscon_map)) {
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pr_crit("could not find Integrator/AP system controller\n");
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return;
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}
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ret = regmap_read(ap_syscon_map,
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INTEGRATOR_SC_DEC_OFFSET,
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&sc_dec);
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if (ret) {
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pr_crit("could not read from Integrator/AP syscon\n");
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return;
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}
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for (i = 0; i < 4; i++) {
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struct lm_device *lmdev;
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if ((sc_dec & (16 << i)) == 0)
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continue;
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lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
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if (!lmdev)
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continue;
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lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
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lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
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lmdev->resource.flags = IORESOURCE_MEM;
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lmdev->irq = irq_of_parse_and_map(syscon, i);
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lmdev->id = i;
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lm_device_register(lmdev);
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}
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}
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static const char * ap_dt_board_compat[] = {
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"arm,integrator-ap",
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NULL,
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};
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DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
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.reserve = integrator_reserve,
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.map_io = ap_map_io,
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.init_early = ap_init_early,
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.init_irq = ap_init_irq_of,
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.init_machine = ap_init_of,
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.dt_compat = ap_dt_board_compat,
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MACHINE_END
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