![Linus Torvalds](/assets/img/avatar_default.png)
- Additional struct_size() conversions (Matthew, Kees) - Explicitly reported overflow fixes (Silvio, Kees) - Add missing kvcalloc() function (Kees) - Treewide conversions of allocators to use either 2-factor argument variant when available, or array_size() and array3_size() as needed (Kees) -----BEGIN PGP SIGNATURE----- Comment: Kees Cook <kees@outflux.net> iQJKBAABCgA0FiEEpcP2jyKd1g9yPm4TiXL039xtwCYFAlsgVtMWHGtlZXNjb29r QGNocm9taXVtLm9yZwAKCRCJcvTf3G3AJhsJEACLYe2EbwLFJz7emOT1KUGK5R1b oVxJog0893WyMqgk9XBlA2lvTBRBYzR3tzsadfYo87L3VOBzazUv0YZaweJb65sF bAvxW3nY06brhKKwTRed1PrMa1iG9R63WISnNAuZAq7+79mN6YgW4G6YSAEF9lW7 oPJoPw93YxcI8JcG+dA8BC9w7pJFKooZH4gvLUSUNl5XKr8Ru5YnWcV8F+8M4vZI EJtXFmdlmxAledUPxTSCIojO8m/tNOjYTreBJt9K1DXKY6UcgAdhk75TRLEsp38P fPvMigYQpBDnYz2pi9ourTgvZLkffK1OBZ46PPt8BgUZVf70D6CBg10vK47KO6N2 zreloxkMTrz5XohyjfNjYFRkyyuwV2sSVrRJqF4dpyJ4NJQRjvyywxIP4Myifwlb ONipCM1EjvQjaEUbdcqKgvlooMdhcyxfshqJWjHzXB6BL22uPzq5jHXXugz8/ol8 tOSM2FuJ2sBLQso+szhisxtMd11PihzIZK9BfxEG3du+/hlI+2XgN7hnmlXuA2k3 BUW6BSDhab41HNd6pp50bDJnL0uKPWyFC6hqSNZw+GOIb46jfFcQqnCB3VZGCwj3 LH53Be1XlUrttc/NrtkvVhm4bdxtfsp4F7nsPFNDuHvYNkalAVoC3An0BzOibtkh AtfvEeaPHaOyD8/h2Q== =zUUp -----END PGP SIGNATURE----- Merge tag 'overflow-v4.18-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux Pull more overflow updates from Kees Cook: "The rest of the overflow changes for v4.18-rc1. This includes the explicit overflow fixes from Silvio, further struct_size() conversions from Matthew, and a bug fix from Dan. But the bulk of it is the treewide conversions to use either the 2-factor argument allocators (e.g. kmalloc(a * b, ...) into kmalloc_array(a, b, ...) or the array_size() macros (e.g. vmalloc(a * b) into vmalloc(array_size(a, b)). Coccinelle was fighting me on several fronts, so I've done a bunch of manual whitespace updates in the patches as well. Summary: - Error path bug fix for overflow tests (Dan) - Additional struct_size() conversions (Matthew, Kees) - Explicitly reported overflow fixes (Silvio, Kees) - Add missing kvcalloc() function (Kees) - Treewide conversions of allocators to use either 2-factor argument variant when available, or array_size() and array3_size() as needed (Kees)" * tag 'overflow-v4.18-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux: (26 commits) treewide: Use array_size in f2fs_kvzalloc() treewide: Use array_size() in f2fs_kzalloc() treewide: Use array_size() in f2fs_kmalloc() treewide: Use array_size() in sock_kmalloc() treewide: Use array_size() in kvzalloc_node() treewide: Use array_size() in vzalloc_node() treewide: Use array_size() in vzalloc() treewide: Use array_size() in vmalloc() treewide: devm_kzalloc() -> devm_kcalloc() treewide: devm_kmalloc() -> devm_kmalloc_array() treewide: kvzalloc() -> kvcalloc() treewide: kvmalloc() -> kvmalloc_array() treewide: kzalloc_node() -> kcalloc_node() treewide: kzalloc() -> kcalloc() treewide: kmalloc() -> kmalloc_array() mm: Introduce kvcalloc() video: uvesafb: Fix integer overflow in allocation UBIFS: Fix potential integer overflow in allocation leds: Use struct_size() in allocation Convert intel uncore to struct_size ...
551 lines
15 KiB
C
551 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2017 Cadence
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// Cadence PCIe endpoint controller driver.
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// Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/pci-epc.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/sizes.h>
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#include "pcie-cadence.h"
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#define CDNS_PCIE_EP_MIN_APERTURE 128 /* 128 bytes */
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#define CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE 0x1
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#define CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY 0x3
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/**
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* struct cdns_pcie_ep - private data for this PCIe endpoint controller driver
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* @pcie: Cadence PCIe controller
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* @max_regions: maximum number of regions supported by hardware
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* @ob_region_map: bitmask of mapped outbound regions
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* @ob_addr: base addresses in the AXI bus where the outbound regions start
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* @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ
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* dedicated outbound regions is mapped.
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* @irq_cpu_addr: base address in the CPU space where a write access triggers
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* the sending of a memory write (MSI) / normal message (legacy
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* IRQ) TLP through the PCIe bus.
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* @irq_pci_addr: used to save the current mapping of the MSI/legacy IRQ
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* dedicated outbound region.
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* @irq_pci_fn: the latest PCI function that has updated the mapping of
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* the MSI/legacy IRQ dedicated outbound region.
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* @irq_pending: bitmask of asserted legacy IRQs.
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*/
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struct cdns_pcie_ep {
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struct cdns_pcie pcie;
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u32 max_regions;
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unsigned long ob_region_map;
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phys_addr_t *ob_addr;
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phys_addr_t irq_phys_addr;
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void __iomem *irq_cpu_addr;
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u64 irq_pci_addr;
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u8 irq_pci_fn;
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u8 irq_pending;
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};
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static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn,
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struct pci_epf_header *hdr)
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{
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struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
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struct cdns_pcie *pcie = &ep->pcie;
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cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid);
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cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid);
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cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code);
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cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE,
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hdr->subclass_code | hdr->baseclass_code << 8);
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cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE,
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hdr->cache_line_size);
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cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID, hdr->subsys_id);
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cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN, hdr->interrupt_pin);
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/*
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* Vendor ID can only be modified from function 0, all other functions
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* use the same vendor ID as function 0.
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*/
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if (fn == 0) {
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/* Update the vendor IDs. */
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u32 id = CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) |
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CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id);
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cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id);
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}
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return 0;
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}
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static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn,
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struct pci_epf_bar *epf_bar)
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{
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struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
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struct cdns_pcie *pcie = &ep->pcie;
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dma_addr_t bar_phys = epf_bar->phys_addr;
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enum pci_barno bar = epf_bar->barno;
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int flags = epf_bar->flags;
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u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
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u64 sz;
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/* BAR size is 2^(aperture + 7) */
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sz = max_t(size_t, epf_bar->size, CDNS_PCIE_EP_MIN_APERTURE);
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/*
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* roundup_pow_of_two() returns an unsigned long, which is not suited
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* for 64bit values.
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*/
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sz = 1ULL << fls64(sz - 1);
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aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */
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if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
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ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS;
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} else {
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bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
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bool is_64bits = sz > SZ_2G;
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if (is_64bits && (bar & 1))
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return -EINVAL;
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if (is_64bits && !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64))
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epf_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
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if (is_64bits && is_prefetch)
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ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
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else if (is_prefetch)
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ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
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else if (is_64bits)
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ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS;
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else
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ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS;
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}
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addr0 = lower_32_bits(bar_phys);
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addr1 = upper_32_bits(bar_phys);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar),
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addr0);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar),
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addr1);
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if (bar < BAR_4) {
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reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
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b = bar;
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} else {
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reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
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b = bar - BAR_4;
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}
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cfg = cdns_pcie_readl(pcie, reg);
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cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
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CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
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cfg |= (CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |
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CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
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cdns_pcie_writel(pcie, reg, cfg);
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return 0;
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}
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static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn,
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struct pci_epf_bar *epf_bar)
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{
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struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
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struct cdns_pcie *pcie = &ep->pcie;
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enum pci_barno bar = epf_bar->barno;
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u32 reg, cfg, b, ctrl;
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if (bar < BAR_4) {
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reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
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b = bar;
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} else {
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reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
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b = bar - BAR_4;
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}
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ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED;
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cfg = cdns_pcie_readl(pcie, reg);
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cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
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CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
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cfg |= CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl);
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cdns_pcie_writel(pcie, reg, cfg);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), 0);
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cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), 0);
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}
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static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, phys_addr_t addr,
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u64 pci_addr, size_t size)
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{
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struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
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struct cdns_pcie *pcie = &ep->pcie;
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u32 r;
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r = find_first_zero_bit(&ep->ob_region_map,
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sizeof(ep->ob_region_map) * BITS_PER_LONG);
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if (r >= ep->max_regions - 1) {
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dev_err(&epc->dev, "no free outbound region\n");
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return -EINVAL;
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}
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cdns_pcie_set_outbound_region(pcie, fn, r, false, addr, pci_addr, size);
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set_bit(r, &ep->ob_region_map);
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ep->ob_addr[r] = addr;
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return 0;
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}
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static void cdns_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn,
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phys_addr_t addr)
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{
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struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
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struct cdns_pcie *pcie = &ep->pcie;
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u32 r;
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for (r = 0; r < ep->max_regions - 1; r++)
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if (ep->ob_addr[r] == addr)
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break;
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if (r == ep->max_regions - 1)
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return;
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cdns_pcie_reset_outbound_region(pcie, r);
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ep->ob_addr[r] = 0;
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clear_bit(r, &ep->ob_region_map);
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}
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static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 mmc)
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{
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struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
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struct cdns_pcie *pcie = &ep->pcie;
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u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
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u16 flags;
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/*
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* Set the Multiple Message Capable bitfield into the Message Control
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* register.
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*/
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flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
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flags = (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1);
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flags |= PCI_MSI_FLAGS_64BIT;
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flags &= ~PCI_MSI_FLAGS_MASKBIT;
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cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags);
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return 0;
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}
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static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn)
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{
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struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
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struct cdns_pcie *pcie = &ep->pcie;
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u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
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u16 flags, mmc, mme;
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/* Validate that the MSI feature is actually enabled. */
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flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
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if (!(flags & PCI_MSI_FLAGS_ENABLE))
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return -EINVAL;
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/*
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* Get the Multiple Message Enable bitfield from the Message Control
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* register.
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*/
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mmc = (flags & PCI_MSI_FLAGS_QMASK) >> 1;
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mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;
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return mme;
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}
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static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn,
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u8 intx, bool is_asserted)
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{
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struct cdns_pcie *pcie = &ep->pcie;
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u32 r = ep->max_regions - 1;
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u32 offset;
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u16 status;
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u8 msg_code;
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intx &= 3;
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/* Set the outbound region if needed. */
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if (unlikely(ep->irq_pci_addr != CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY ||
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ep->irq_pci_fn != fn)) {
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/* Last region was reserved for IRQ writes. */
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cdns_pcie_set_outbound_region_for_normal_msg(pcie, fn, r,
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ep->irq_phys_addr);
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ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY;
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ep->irq_pci_fn = fn;
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}
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if (is_asserted) {
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ep->irq_pending |= BIT(intx);
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msg_code = MSG_CODE_ASSERT_INTA + intx;
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} else {
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ep->irq_pending &= ~BIT(intx);
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msg_code = MSG_CODE_DEASSERT_INTA + intx;
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}
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status = cdns_pcie_ep_fn_readw(pcie, fn, PCI_STATUS);
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if (((status & PCI_STATUS_INTERRUPT) != 0) ^ (ep->irq_pending != 0)) {
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status ^= PCI_STATUS_INTERRUPT;
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cdns_pcie_ep_fn_writew(pcie, fn, PCI_STATUS, status);
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}
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offset = CDNS_PCIE_NORMAL_MSG_ROUTING(MSG_ROUTING_LOCAL) |
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CDNS_PCIE_NORMAL_MSG_CODE(msg_code) |
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CDNS_PCIE_MSG_NO_DATA;
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writel(0, ep->irq_cpu_addr + offset);
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}
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static int cdns_pcie_ep_send_legacy_irq(struct cdns_pcie_ep *ep, u8 fn, u8 intx)
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{
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u16 cmd;
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cmd = cdns_pcie_ep_fn_readw(&ep->pcie, fn, PCI_COMMAND);
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if (cmd & PCI_COMMAND_INTX_DISABLE)
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return -EINVAL;
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cdns_pcie_ep_assert_intx(ep, fn, intx, true);
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/*
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* The mdelay() value was taken from dra7xx_pcie_raise_legacy_irq()
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* from drivers/pci/dwc/pci-dra7xx.c
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*/
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mdelay(1);
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cdns_pcie_ep_assert_intx(ep, fn, intx, false);
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return 0;
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}
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static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn,
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u8 interrupt_num)
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{
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struct cdns_pcie *pcie = &ep->pcie;
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u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
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u16 flags, mme, data, data_mask;
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u8 msi_count;
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u64 pci_addr, pci_addr_mask = 0xff;
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/* Check whether the MSI feature has been enabled by the PCI host. */
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flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
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if (!(flags & PCI_MSI_FLAGS_ENABLE))
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return -EINVAL;
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/* Get the number of enabled MSIs */
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mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;
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msi_count = 1 << mme;
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if (!interrupt_num || interrupt_num > msi_count)
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return -EINVAL;
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/* Compute the data value to be written. */
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data_mask = msi_count - 1;
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data = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64);
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data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask);
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/* Get the PCI address where to write the data into. */
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pci_addr = cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI);
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pci_addr <<= 32;
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pci_addr |= cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO);
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pci_addr &= GENMASK_ULL(63, 2);
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/* Set the outbound region if needed. */
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if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) ||
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ep->irq_pci_fn != fn)) {
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/* Last region was reserved for IRQ writes. */
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cdns_pcie_set_outbound_region(pcie, fn, ep->max_regions - 1,
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false,
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ep->irq_phys_addr,
|
|
pci_addr & ~pci_addr_mask,
|
|
pci_addr_mask + 1);
|
|
ep->irq_pci_addr = (pci_addr & ~pci_addr_mask);
|
|
ep->irq_pci_fn = fn;
|
|
}
|
|
writew(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn,
|
|
enum pci_epc_irq_type type, u8 interrupt_num)
|
|
{
|
|
struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
|
|
|
|
switch (type) {
|
|
case PCI_EPC_IRQ_LEGACY:
|
|
return cdns_pcie_ep_send_legacy_irq(ep, fn, 0);
|
|
|
|
case PCI_EPC_IRQ_MSI:
|
|
return cdns_pcie_ep_send_msi_irq(ep, fn, interrupt_num);
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
static int cdns_pcie_ep_start(struct pci_epc *epc)
|
|
{
|
|
struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
|
|
struct cdns_pcie *pcie = &ep->pcie;
|
|
struct pci_epf *epf;
|
|
u32 cfg;
|
|
|
|
/*
|
|
* BIT(0) is hardwired to 1, hence function 0 is always enabled
|
|
* and can't be disabled anyway.
|
|
*/
|
|
cfg = BIT(0);
|
|
list_for_each_entry(epf, &epc->pci_epf, list)
|
|
cfg |= BIT(epf->func_no);
|
|
cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, cfg);
|
|
|
|
/*
|
|
* The PCIe links are automatically established by the controller
|
|
* once for all at powerup: the software can neither start nor stop
|
|
* those links later at runtime.
|
|
*
|
|
* Then we only have to notify the EP core that our links are already
|
|
* established. However we don't call directly pci_epc_linkup() because
|
|
* we've already locked the epc->lock.
|
|
*/
|
|
list_for_each_entry(epf, &epc->pci_epf, list)
|
|
pci_epf_linkup(epf);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct pci_epc_ops cdns_pcie_epc_ops = {
|
|
.write_header = cdns_pcie_ep_write_header,
|
|
.set_bar = cdns_pcie_ep_set_bar,
|
|
.clear_bar = cdns_pcie_ep_clear_bar,
|
|
.map_addr = cdns_pcie_ep_map_addr,
|
|
.unmap_addr = cdns_pcie_ep_unmap_addr,
|
|
.set_msi = cdns_pcie_ep_set_msi,
|
|
.get_msi = cdns_pcie_ep_get_msi,
|
|
.raise_irq = cdns_pcie_ep_raise_irq,
|
|
.start = cdns_pcie_ep_start,
|
|
};
|
|
|
|
static const struct of_device_id cdns_pcie_ep_of_match[] = {
|
|
{ .compatible = "cdns,cdns-pcie-ep" },
|
|
|
|
{ },
|
|
};
|
|
|
|
static int cdns_pcie_ep_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct device_node *np = dev->of_node;
|
|
struct cdns_pcie_ep *ep;
|
|
struct cdns_pcie *pcie;
|
|
struct pci_epc *epc;
|
|
struct resource *res;
|
|
int ret;
|
|
|
|
ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
|
|
if (!ep)
|
|
return -ENOMEM;
|
|
|
|
pcie = &ep->pcie;
|
|
pcie->is_rc = false;
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
|
|
pcie->reg_base = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(pcie->reg_base)) {
|
|
dev_err(dev, "missing \"reg\"\n");
|
|
return PTR_ERR(pcie->reg_base);
|
|
}
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
|
|
if (!res) {
|
|
dev_err(dev, "missing \"mem\"\n");
|
|
return -EINVAL;
|
|
}
|
|
pcie->mem_res = res;
|
|
|
|
ret = of_property_read_u32(np, "cdns,max-outbound-regions",
|
|
&ep->max_regions);
|
|
if (ret < 0) {
|
|
dev_err(dev, "missing \"cdns,max-outbound-regions\"\n");
|
|
return ret;
|
|
}
|
|
ep->ob_addr = devm_kcalloc(dev,
|
|
ep->max_regions, sizeof(*ep->ob_addr),
|
|
GFP_KERNEL);
|
|
if (!ep->ob_addr)
|
|
return -ENOMEM;
|
|
|
|
pm_runtime_enable(dev);
|
|
ret = pm_runtime_get_sync(dev);
|
|
if (ret < 0) {
|
|
dev_err(dev, "pm_runtime_get_sync() failed\n");
|
|
goto err_get_sync;
|
|
}
|
|
|
|
/* Disable all but function 0 (anyway BIT(0) is hardwired to 1). */
|
|
cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, BIT(0));
|
|
|
|
epc = devm_pci_epc_create(dev, &cdns_pcie_epc_ops);
|
|
if (IS_ERR(epc)) {
|
|
dev_err(dev, "failed to create epc device\n");
|
|
ret = PTR_ERR(epc);
|
|
goto err_init;
|
|
}
|
|
|
|
epc_set_drvdata(epc, ep);
|
|
|
|
if (of_property_read_u8(np, "max-functions", &epc->max_functions) < 0)
|
|
epc->max_functions = 1;
|
|
|
|
ret = pci_epc_mem_init(epc, pcie->mem_res->start,
|
|
resource_size(pcie->mem_res));
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to initialize the memory space\n");
|
|
goto err_init;
|
|
}
|
|
|
|
ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr,
|
|
SZ_128K);
|
|
if (!ep->irq_cpu_addr) {
|
|
dev_err(dev, "failed to reserve memory space for MSI\n");
|
|
ret = -ENOMEM;
|
|
goto free_epc_mem;
|
|
}
|
|
ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE;
|
|
|
|
return 0;
|
|
|
|
free_epc_mem:
|
|
pci_epc_mem_exit(epc);
|
|
|
|
err_init:
|
|
pm_runtime_put_sync(dev);
|
|
|
|
err_get_sync:
|
|
pm_runtime_disable(dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void cdns_pcie_ep_shutdown(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
int ret;
|
|
|
|
ret = pm_runtime_put_sync(dev);
|
|
if (ret < 0)
|
|
dev_dbg(dev, "pm_runtime_put_sync failed\n");
|
|
|
|
pm_runtime_disable(dev);
|
|
|
|
/* The PCIe controller can't be disabled. */
|
|
}
|
|
|
|
static struct platform_driver cdns_pcie_ep_driver = {
|
|
.driver = {
|
|
.name = "cdns-pcie-ep",
|
|
.of_match_table = cdns_pcie_ep_of_match,
|
|
},
|
|
.probe = cdns_pcie_ep_probe,
|
|
.shutdown = cdns_pcie_ep_shutdown,
|
|
};
|
|
builtin_platform_driver(cdns_pcie_ep_driver);
|