80 lines
2.7 KiB
Plaintext
80 lines
2.7 KiB
Plaintext
* ARM Generic Interrupt Controller, version 3
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AArch64 SMP cores are often associated with a GICv3, providing Private
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Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
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Software Generated Interrupts (SGI), and Locality-specific Peripheral
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Interrupts (LPI).
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Main node required properties:
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- compatible : should at least contain "arm,gic-v3".
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- interrupt-controller : Identifies the node as an interrupt controller
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt source. Must be a single cell with a value of at least 3.
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The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
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interrupts. Other values are reserved for future use.
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The 2nd cell contains the interrupt number for the interrupt type.
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SPI interrupts are in the range [0-987]. PPI interrupts are in the
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range [0-15].
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The 3rd cell is the flags, encoded as follows:
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bits[3:0] trigger type and level flags.
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1 = edge triggered
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4 = level triggered
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Cells 4 and beyond are reserved for future use. When the 1st cell
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has a value of 0 or 1, cells 4 and beyond act as padding, and may be
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ignored. It is recommended that padding cells have a value of 0.
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- reg : Specifies base physical address(s) and size of the GIC
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registers, in the following order:
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- GIC Distributor interface (GICD)
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- GIC Redistributors (GICR), one range per redistributor region
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- GIC CPU interface (GICC)
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- GIC Hypervisor interface (GICH)
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- GIC Virtual CPU interface (GICV)
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GICC, GICH and GICV are optional.
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- interrupts : Interrupt source of the VGIC maintenance interrupt.
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Optional
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- redistributor-stride : If using padding pages, specifies the stride
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of consecutive redistributors. Must be a multiple of 64kB.
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- #redistributor-regions: The number of independent contiguous regions
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occupied by the redistributors. Required if more than one such
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region is present.
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Examples:
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gic: interrupt-controller@2cf00000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x2f000000 0 0x10000>, // GICD
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<0x0 0x2f100000 0 0x200000>, // GICR
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<0x0 0x2c000000 0 0x2000>, // GICC
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<0x0 0x2c010000 0 0x2000>, // GICH
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<0x0 0x2c020000 0 0x2000>; // GICV
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interrupts = <1 9 4>;
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};
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gic: interrupt-controller@2c010000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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redistributor-stride = <0x0 0x40000>; // 256kB stride
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#redistributor-regions = <2>;
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reg = <0x0 0x2c010000 0 0x10000>, // GICD
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<0x0 0x2d000000 0 0x800000>, // GICR 1: CPUs 0-31
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<0x0 0x2e000000 0 0x800000>; // GICR 2: CPUs 32-63
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<0x0 0x2c040000 0 0x2000>, // GICC
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<0x0 0x2c060000 0 0x2000>, // GICH
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<0x0 0x2c080000 0 0x2000>; // GICV
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interrupts = <1 9 4>;
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};
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