8a97d4287e
The WRSTBI bit (disabled by default but enabled by bootloader), when set, is responsible for resetting voltages to default values of certain bucks on falling edge of Warm Reset Input pin from AP. However on some boards (with S2MPS13) the pin is pulled down so any suspend will effectively trigger the reset of bucks supplying the power to the little and big cores. In the same time when resuming, these bucks must provide voltage greater or equal to voltage before suspend to match the frequency chosen by cpufreq. If voltage (default value of voltage after reset) is lower than one set by cpufreq before suspend, then system will hang during resuming. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reported-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Tested-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
190 lines
3.9 KiB
C
190 lines
3.9 KiB
C
/*
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* s2mps13.h
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*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __LINUX_MFD_S2MPS13_H
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#define __LINUX_MFD_S2MPS13_H
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/* S2MPS13 registers */
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enum s2mps13_reg {
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S2MPS13_REG_ID,
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S2MPS13_REG_INT1,
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S2MPS13_REG_INT2,
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S2MPS13_REG_INT3,
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S2MPS13_REG_INT1M,
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S2MPS13_REG_INT2M,
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S2MPS13_REG_INT3M,
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S2MPS13_REG_ST1,
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S2MPS13_REG_ST2,
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S2MPS13_REG_PWRONSRC,
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S2MPS13_REG_OFFSRC,
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S2MPS13_REG_BU_CHG,
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S2MPS13_REG_RTCCTRL,
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S2MPS13_REG_CTRL1,
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S2MPS13_REG_CTRL2,
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S2MPS13_REG_RSVD1,
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S2MPS13_REG_RSVD2,
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S2MPS13_REG_RSVD3,
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S2MPS13_REG_RSVD4,
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S2MPS13_REG_RSVD5,
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S2MPS13_REG_RSVD6,
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S2MPS13_REG_CTRL3,
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S2MPS13_REG_RSVD7,
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S2MPS13_REG_RSVD8,
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S2MPS13_REG_WRSTBI,
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S2MPS13_REG_B1CTRL,
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S2MPS13_REG_B1OUT,
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S2MPS13_REG_B2CTRL,
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S2MPS13_REG_B2OUT,
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S2MPS13_REG_B3CTRL,
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S2MPS13_REG_B3OUT,
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S2MPS13_REG_B4CTRL,
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S2MPS13_REG_B4OUT,
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S2MPS13_REG_B5CTRL,
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S2MPS13_REG_B5OUT,
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S2MPS13_REG_B6CTRL,
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S2MPS13_REG_B6OUT,
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S2MPS13_REG_B7CTRL,
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S2MPS13_REG_B7SW,
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S2MPS13_REG_B7OUT,
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S2MPS13_REG_B8CTRL,
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S2MPS13_REG_B8OUT,
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S2MPS13_REG_B9CTRL,
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S2MPS13_REG_B9OUT,
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S2MPS13_REG_B10CTRL,
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S2MPS13_REG_B10OUT,
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S2MPS13_REG_BB1CTRL,
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S2MPS13_REG_BB1OUT,
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S2MPS13_REG_BUCK_RAMP1,
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S2MPS13_REG_BUCK_RAMP2,
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S2MPS13_REG_LDO_DVS1,
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S2MPS13_REG_LDO_DVS2,
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S2MPS13_REG_LDO_DVS3,
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S2MPS13_REG_B6OUT2,
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S2MPS13_REG_L1CTRL,
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S2MPS13_REG_L2CTRL,
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S2MPS13_REG_L3CTRL,
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S2MPS13_REG_L4CTRL,
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S2MPS13_REG_L5CTRL,
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S2MPS13_REG_L6CTRL,
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S2MPS13_REG_L7CTRL,
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S2MPS13_REG_L8CTRL,
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S2MPS13_REG_L9CTRL,
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S2MPS13_REG_L10CTRL,
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S2MPS13_REG_L11CTRL,
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S2MPS13_REG_L12CTRL,
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S2MPS13_REG_L13CTRL,
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S2MPS13_REG_L14CTRL,
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S2MPS13_REG_L15CTRL,
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S2MPS13_REG_L16CTRL,
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S2MPS13_REG_L17CTRL,
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S2MPS13_REG_L18CTRL,
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S2MPS13_REG_L19CTRL,
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S2MPS13_REG_L20CTRL,
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S2MPS13_REG_L21CTRL,
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S2MPS13_REG_L22CTRL,
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S2MPS13_REG_L23CTRL,
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S2MPS13_REG_L24CTRL,
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S2MPS13_REG_L25CTRL,
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S2MPS13_REG_L26CTRL,
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S2MPS13_REG_L27CTRL,
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S2MPS13_REG_L28CTRL,
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S2MPS13_REG_L29CTRL,
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S2MPS13_REG_L30CTRL,
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S2MPS13_REG_L31CTRL,
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S2MPS13_REG_L32CTRL,
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S2MPS13_REG_L33CTRL,
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S2MPS13_REG_L34CTRL,
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S2MPS13_REG_L35CTRL,
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S2MPS13_REG_L36CTRL,
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S2MPS13_REG_L37CTRL,
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S2MPS13_REG_L38CTRL,
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S2MPS13_REG_L39CTRL,
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S2MPS13_REG_L40CTRL,
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S2MPS13_REG_LDODSCH1,
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S2MPS13_REG_LDODSCH2,
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S2MPS13_REG_LDODSCH3,
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S2MPS13_REG_LDODSCH4,
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S2MPS13_REG_LDODSCH5,
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};
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/* regulator ids */
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enum s2mps13_regulators {
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S2MPS13_LDO1,
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S2MPS13_LDO2,
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S2MPS13_LDO3,
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S2MPS13_LDO4,
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S2MPS13_LDO5,
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S2MPS13_LDO6,
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S2MPS13_LDO7,
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S2MPS13_LDO8,
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S2MPS13_LDO9,
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S2MPS13_LDO10,
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S2MPS13_LDO11,
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S2MPS13_LDO12,
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S2MPS13_LDO13,
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S2MPS13_LDO14,
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S2MPS13_LDO15,
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S2MPS13_LDO16,
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S2MPS13_LDO17,
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S2MPS13_LDO18,
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S2MPS13_LDO19,
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S2MPS13_LDO20,
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S2MPS13_LDO21,
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S2MPS13_LDO22,
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S2MPS13_LDO23,
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S2MPS13_LDO24,
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S2MPS13_LDO25,
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S2MPS13_LDO26,
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S2MPS13_LDO27,
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S2MPS13_LDO28,
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S2MPS13_LDO29,
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S2MPS13_LDO30,
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S2MPS13_LDO31,
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S2MPS13_LDO32,
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S2MPS13_LDO33,
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S2MPS13_LDO34,
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S2MPS13_LDO35,
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S2MPS13_LDO36,
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S2MPS13_LDO37,
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S2MPS13_LDO38,
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S2MPS13_LDO39,
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S2MPS13_LDO40,
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S2MPS13_BUCK1,
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S2MPS13_BUCK2,
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S2MPS13_BUCK3,
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S2MPS13_BUCK4,
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S2MPS13_BUCK5,
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S2MPS13_BUCK6,
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S2MPS13_BUCK7,
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S2MPS13_BUCK8,
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S2MPS13_BUCK9,
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S2MPS13_BUCK10,
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S2MPS13_REGULATOR_MAX,
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};
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/*
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* Default ramp delay in uv/us. Datasheet says that ramp delay can be
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* controlled however it does not specify which register is used for that.
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* Let's assume that default value will be set.
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*/
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#define S2MPS13_BUCK_RAMP_DELAY 12500
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#define S2MPS13_REG_WRSTBI_MASK BIT(5)
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#endif /* __LINUX_MFD_S2MPS13_H */
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