![Linus Torvalds](/assets/img/avatar_default.png)
Pull intel iommu updates from David Woodhouse: "This lays a little of the groundwork for upcoming Shared Virtual Memory support — fixing some bogus #defines for capability bits and adding the new ones, and starting to use the new wider page tables where we can, in anticipation of actually filling in the new fields therein. It also allows graphics devices to be assigned to VM guests again. This got broken in 3.17 by disallowing assignment of RMRR-afflicted devices. Like USB, we do understand why there's an RMRR for graphics devices — and unlike USB, it's actually sane. So we can make an exception for graphics devices, just as we do USB controllers. Finally, tone down the warning about the X2APIC_OPT_OUT bit, due to persistent requests. X2APIC_OPT_OUT was added to the spec as a nasty hack to allow broken BIOSes to forbid us from using X2APIC when they do stupid and invasive things and would break if we did. Someone noticed that since Windows doesn't have full IOMMU support for DMA protection, setting the X2APIC_OPT_OUT bit made Windows avoid initialising the IOMMU on the graphics unit altogether. This means that it would be available for use in "driver mode", where the IOMMU registers are made available through a BAR of the graphics device and the graphics driver can do SVM all for itself. So they started setting the X2APIC_OPT_OUT bit on *all* platforms with SVM capabilities. And even the platforms which *might*, if the planets had been aligned correctly, possibly have had SVM capability but which in practice actually don't" * git://git.infradead.org/intel-iommu: iommu/vt-d: support extended root and context entries iommu/vt-d: Add new extended capabilities from v2.3 VT-d specification iommu/vt-d: Allow RMRR on graphics devices too iommu/vt-d: Print x2apic opt out info instead of printing a warning iommu/vt-d: kill bogus ecap_niotlb_iunits()
1302 lines
30 KiB
C
1302 lines
30 KiB
C
#include <linux/interrupt.h>
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#include <linux/dmar.h>
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#include <linux/spinlock.h>
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#include <linux/slab.h>
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#include <linux/jiffies.h>
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#include <linux/hpet.h>
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <linux/intel-iommu.h>
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#include <linux/acpi.h>
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#include <asm/io_apic.h>
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#include <asm/smp.h>
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#include <asm/cpu.h>
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#include <asm/irq_remapping.h>
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#include <asm/pci-direct.h>
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#include <asm/msidef.h>
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#include "irq_remapping.h"
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struct ioapic_scope {
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struct intel_iommu *iommu;
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unsigned int id;
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unsigned int bus; /* PCI bus number */
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unsigned int devfn; /* PCI devfn number */
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};
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struct hpet_scope {
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struct intel_iommu *iommu;
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u8 id;
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unsigned int bus;
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unsigned int devfn;
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};
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#define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
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#define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8)
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static int __read_mostly eim_mode;
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static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
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static struct hpet_scope ir_hpet[MAX_HPET_TBS];
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/*
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* Lock ordering:
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* ->dmar_global_lock
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* ->irq_2_ir_lock
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* ->qi->q_lock
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* ->iommu->register_lock
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* Note:
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* intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called
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* in single-threaded environment with interrupt disabled, so no need to tabke
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* the dmar_global_lock.
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*/
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static DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
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static int __init parse_ioapics_under_ir(void);
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static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
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{
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struct irq_cfg *cfg = irq_cfg(irq);
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return cfg ? &cfg->irq_2_iommu : NULL;
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}
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static int get_irte(int irq, struct irte *entry)
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{
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struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
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unsigned long flags;
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int index;
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if (!entry || !irq_iommu)
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return -1;
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raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
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if (unlikely(!irq_iommu->iommu)) {
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raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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return -1;
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}
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index = irq_iommu->irte_index + irq_iommu->sub_handle;
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*entry = *(irq_iommu->iommu->ir_table->base + index);
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raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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return 0;
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}
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static int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
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{
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struct ir_table *table = iommu->ir_table;
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struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
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struct irq_cfg *cfg = irq_cfg(irq);
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unsigned int mask = 0;
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unsigned long flags;
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int index;
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if (!count || !irq_iommu)
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return -1;
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if (count > 1) {
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count = __roundup_pow_of_two(count);
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mask = ilog2(count);
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}
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if (mask > ecap_max_handle_mask(iommu->ecap)) {
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printk(KERN_ERR
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"Requested mask %x exceeds the max invalidation handle"
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" mask value %Lx\n", mask,
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ecap_max_handle_mask(iommu->ecap));
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return -1;
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}
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raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
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index = bitmap_find_free_region(table->bitmap,
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INTR_REMAP_TABLE_ENTRIES, mask);
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if (index < 0) {
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pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id);
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} else {
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cfg->remapped = 1;
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irq_iommu->iommu = iommu;
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irq_iommu->irte_index = index;
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irq_iommu->sub_handle = 0;
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irq_iommu->irte_mask = mask;
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}
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raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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return index;
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}
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static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
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{
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struct qi_desc desc;
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desc.low = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
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| QI_IEC_SELECTIVE;
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desc.high = 0;
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return qi_submit_sync(&desc, iommu);
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}
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static int map_irq_to_irte_handle(int irq, u16 *sub_handle)
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{
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struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
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unsigned long flags;
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int index;
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if (!irq_iommu)
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return -1;
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raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
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*sub_handle = irq_iommu->sub_handle;
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index = irq_iommu->irte_index;
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raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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return index;
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}
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static int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle)
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{
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struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
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struct irq_cfg *cfg = irq_cfg(irq);
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unsigned long flags;
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if (!irq_iommu)
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return -1;
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raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
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cfg->remapped = 1;
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irq_iommu->iommu = iommu;
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irq_iommu->irte_index = index;
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irq_iommu->sub_handle = subhandle;
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irq_iommu->irte_mask = 0;
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raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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return 0;
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}
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static int modify_irte(int irq, struct irte *irte_modified)
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{
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struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
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struct intel_iommu *iommu;
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unsigned long flags;
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struct irte *irte;
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int rc, index;
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if (!irq_iommu)
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return -1;
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raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
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iommu = irq_iommu->iommu;
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index = irq_iommu->irte_index + irq_iommu->sub_handle;
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irte = &iommu->ir_table->base[index];
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set_64bit(&irte->low, irte_modified->low);
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set_64bit(&irte->high, irte_modified->high);
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__iommu_flush_cache(iommu, irte, sizeof(*irte));
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rc = qi_flush_iec(iommu, index, 0);
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raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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return rc;
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}
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static struct intel_iommu *map_hpet_to_ir(u8 hpet_id)
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{
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int i;
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for (i = 0; i < MAX_HPET_TBS; i++)
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if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu)
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return ir_hpet[i].iommu;
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return NULL;
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}
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static struct intel_iommu *map_ioapic_to_ir(int apic)
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{
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int i;
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for (i = 0; i < MAX_IO_APICS; i++)
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if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu)
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return ir_ioapic[i].iommu;
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return NULL;
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}
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static struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
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{
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struct dmar_drhd_unit *drhd;
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drhd = dmar_find_matched_drhd_unit(dev);
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if (!drhd)
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return NULL;
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return drhd->iommu;
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}
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static int clear_entries(struct irq_2_iommu *irq_iommu)
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{
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struct irte *start, *entry, *end;
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struct intel_iommu *iommu;
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int index;
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if (irq_iommu->sub_handle)
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return 0;
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iommu = irq_iommu->iommu;
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index = irq_iommu->irte_index + irq_iommu->sub_handle;
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start = iommu->ir_table->base + index;
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end = start + (1 << irq_iommu->irte_mask);
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for (entry = start; entry < end; entry++) {
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set_64bit(&entry->low, 0);
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set_64bit(&entry->high, 0);
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}
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bitmap_release_region(iommu->ir_table->bitmap, index,
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irq_iommu->irte_mask);
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return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
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}
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static int free_irte(int irq)
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{
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struct irq_2_iommu *irq_iommu = irq_2_iommu(irq);
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unsigned long flags;
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int rc;
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if (!irq_iommu)
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return -1;
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raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
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rc = clear_entries(irq_iommu);
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irq_iommu->iommu = NULL;
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irq_iommu->irte_index = 0;
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irq_iommu->sub_handle = 0;
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irq_iommu->irte_mask = 0;
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raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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return rc;
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}
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/*
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* source validation type
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*/
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#define SVT_NO_VERIFY 0x0 /* no verification is required */
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#define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */
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#define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
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/*
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* source-id qualifier
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*/
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#define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
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#define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
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* the third least significant bit
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*/
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#define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
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* the second and third least significant bits
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*/
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#define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
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* the least three significant bits
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*/
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/*
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* set SVT, SQ and SID fields of irte to verify
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* source ids of interrupt requests
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*/
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static void set_irte_sid(struct irte *irte, unsigned int svt,
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unsigned int sq, unsigned int sid)
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{
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if (disable_sourceid_checking)
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svt = SVT_NO_VERIFY;
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irte->svt = svt;
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irte->sq = sq;
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irte->sid = sid;
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}
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static int set_ioapic_sid(struct irte *irte, int apic)
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{
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int i;
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u16 sid = 0;
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if (!irte)
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return -1;
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down_read(&dmar_global_lock);
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for (i = 0; i < MAX_IO_APICS; i++) {
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if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) {
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sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
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break;
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}
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}
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up_read(&dmar_global_lock);
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if (sid == 0) {
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pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic);
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return -1;
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}
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set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid);
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return 0;
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}
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static int set_hpet_sid(struct irte *irte, u8 id)
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{
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int i;
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u16 sid = 0;
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if (!irte)
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return -1;
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down_read(&dmar_global_lock);
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for (i = 0; i < MAX_HPET_TBS; i++) {
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if (ir_hpet[i].iommu && ir_hpet[i].id == id) {
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sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
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break;
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}
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}
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up_read(&dmar_global_lock);
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if (sid == 0) {
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pr_warning("Failed to set source-id of HPET block (%d)\n", id);
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return -1;
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}
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/*
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* Should really use SQ_ALL_16. Some platforms are broken.
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* While we figure out the right quirks for these broken platforms, use
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* SQ_13_IGNORE_3 for now.
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*/
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set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
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return 0;
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}
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struct set_msi_sid_data {
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struct pci_dev *pdev;
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u16 alias;
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};
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static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque)
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{
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struct set_msi_sid_data *data = opaque;
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data->pdev = pdev;
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data->alias = alias;
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return 0;
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}
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static int set_msi_sid(struct irte *irte, struct pci_dev *dev)
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{
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struct set_msi_sid_data data;
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if (!irte || !dev)
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return -1;
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pci_for_each_dma_alias(dev, set_msi_sid_cb, &data);
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/*
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* DMA alias provides us with a PCI device and alias. The only case
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* where the it will return an alias on a different bus than the
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* device is the case of a PCIe-to-PCI bridge, where the alias is for
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* the subordinate bus. In this case we can only verify the bus.
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*
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* If the alias device is on a different bus than our source device
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* then we have a topology based alias, use it.
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*
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* Otherwise, the alias is for a device DMA quirk and we cannot
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* assume that MSI uses the same requester ID. Therefore use the
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* original device.
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*/
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if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number)
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set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
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PCI_DEVID(PCI_BUS_NUM(data.alias),
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dev->bus->number));
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else if (data.pdev->bus->number != dev->bus->number)
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set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias);
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else
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set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
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PCI_DEVID(dev->bus->number, dev->devfn));
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return 0;
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}
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static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
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{
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u64 addr;
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u32 sts;
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unsigned long flags;
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addr = virt_to_phys((void *)iommu->ir_table->base);
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raw_spin_lock_irqsave(&iommu->register_lock, flags);
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dmar_writeq(iommu->reg + DMAR_IRTA_REG,
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(addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
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/* Set interrupt-remapping table pointer */
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writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG);
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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readl, (sts & DMA_GSTS_IRTPS), sts);
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raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
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/*
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* global invalidation of interrupt entry cache before enabling
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* interrupt-remapping.
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*/
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qi_global_iec(iommu);
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raw_spin_lock_irqsave(&iommu->register_lock, flags);
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/* Enable interrupt-remapping */
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iommu->gcmd |= DMA_GCMD_IRE;
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iommu->gcmd &= ~DMA_GCMD_CFI; /* Block compatibility-format MSIs */
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writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
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IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
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readl, (sts & DMA_GSTS_IRES), sts);
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/*
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* With CFI clear in the Global Command register, we should be
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* protected from dangerous (i.e. compatibility) interrupts
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* regardless of x2apic status. Check just to be sure.
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*/
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if (sts & DMA_GSTS_CFIS)
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WARN(1, KERN_WARNING
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"Compatibility-format IRQs enabled despite intr remapping;\n"
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"you are vulnerable to IRQ injection.\n");
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raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
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}
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static int intel_setup_irq_remapping(struct intel_iommu *iommu)
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{
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struct ir_table *ir_table;
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struct page *pages;
|
|
unsigned long *bitmap;
|
|
|
|
if (iommu->ir_table)
|
|
return 0;
|
|
|
|
ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL);
|
|
if (!ir_table)
|
|
return -ENOMEM;
|
|
|
|
pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO,
|
|
INTR_REMAP_PAGE_ORDER);
|
|
|
|
if (!pages) {
|
|
pr_err("IR%d: failed to allocate pages of order %d\n",
|
|
iommu->seq_id, INTR_REMAP_PAGE_ORDER);
|
|
goto out_free_table;
|
|
}
|
|
|
|
bitmap = kcalloc(BITS_TO_LONGS(INTR_REMAP_TABLE_ENTRIES),
|
|
sizeof(long), GFP_ATOMIC);
|
|
if (bitmap == NULL) {
|
|
pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id);
|
|
goto out_free_pages;
|
|
}
|
|
|
|
ir_table->base = page_address(pages);
|
|
ir_table->bitmap = bitmap;
|
|
iommu->ir_table = ir_table;
|
|
return 0;
|
|
|
|
out_free_pages:
|
|
__free_pages(pages, INTR_REMAP_PAGE_ORDER);
|
|
out_free_table:
|
|
kfree(ir_table);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
static void intel_teardown_irq_remapping(struct intel_iommu *iommu)
|
|
{
|
|
if (iommu && iommu->ir_table) {
|
|
free_pages((unsigned long)iommu->ir_table->base,
|
|
INTR_REMAP_PAGE_ORDER);
|
|
kfree(iommu->ir_table->bitmap);
|
|
kfree(iommu->ir_table);
|
|
iommu->ir_table = NULL;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Disable Interrupt Remapping.
|
|
*/
|
|
static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
|
|
{
|
|
unsigned long flags;
|
|
u32 sts;
|
|
|
|
if (!ecap_ir_support(iommu->ecap))
|
|
return;
|
|
|
|
/*
|
|
* global invalidation of interrupt entry cache before disabling
|
|
* interrupt-remapping.
|
|
*/
|
|
qi_global_iec(iommu);
|
|
|
|
raw_spin_lock_irqsave(&iommu->register_lock, flags);
|
|
|
|
sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
|
|
if (!(sts & DMA_GSTS_IRES))
|
|
goto end;
|
|
|
|
iommu->gcmd &= ~DMA_GCMD_IRE;
|
|
writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
|
|
|
|
IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
|
|
readl, !(sts & DMA_GSTS_IRES), sts);
|
|
|
|
end:
|
|
raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
|
|
}
|
|
|
|
static int __init dmar_x2apic_optout(void)
|
|
{
|
|
struct acpi_table_dmar *dmar;
|
|
dmar = (struct acpi_table_dmar *)dmar_tbl;
|
|
if (!dmar || no_x2apic_optout)
|
|
return 0;
|
|
return dmar->flags & DMAR_X2APIC_OPT_OUT;
|
|
}
|
|
|
|
static void __init intel_cleanup_irq_remapping(void)
|
|
{
|
|
struct dmar_drhd_unit *drhd;
|
|
struct intel_iommu *iommu;
|
|
|
|
for_each_iommu(iommu, drhd) {
|
|
if (ecap_ir_support(iommu->ecap)) {
|
|
iommu_disable_irq_remapping(iommu);
|
|
intel_teardown_irq_remapping(iommu);
|
|
}
|
|
}
|
|
|
|
if (x2apic_supported())
|
|
pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
|
|
}
|
|
|
|
static int __init intel_prepare_irq_remapping(void)
|
|
{
|
|
struct dmar_drhd_unit *drhd;
|
|
struct intel_iommu *iommu;
|
|
|
|
if (irq_remap_broken) {
|
|
printk(KERN_WARNING
|
|
"This system BIOS has enabled interrupt remapping\n"
|
|
"on a chipset that contains an erratum making that\n"
|
|
"feature unstable. To maintain system stability\n"
|
|
"interrupt remapping is being disabled. Please\n"
|
|
"contact your BIOS vendor for an update\n");
|
|
add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (dmar_table_init() < 0)
|
|
return -ENODEV;
|
|
|
|
if (!dmar_ir_support())
|
|
return -ENODEV;
|
|
|
|
if (parse_ioapics_under_ir() != 1) {
|
|
printk(KERN_INFO "Not enabling interrupt remapping\n");
|
|
goto error;
|
|
}
|
|
|
|
/* First make sure all IOMMUs support IRQ remapping */
|
|
for_each_iommu(iommu, drhd)
|
|
if (!ecap_ir_support(iommu->ecap))
|
|
goto error;
|
|
|
|
/* Do the allocations early */
|
|
for_each_iommu(iommu, drhd)
|
|
if (intel_setup_irq_remapping(iommu))
|
|
goto error;
|
|
|
|
return 0;
|
|
|
|
error:
|
|
intel_cleanup_irq_remapping();
|
|
return -ENODEV;
|
|
}
|
|
|
|
static int __init intel_enable_irq_remapping(void)
|
|
{
|
|
struct dmar_drhd_unit *drhd;
|
|
struct intel_iommu *iommu;
|
|
bool setup = false;
|
|
int eim = 0;
|
|
|
|
if (x2apic_supported()) {
|
|
eim = !dmar_x2apic_optout();
|
|
if (!eim)
|
|
pr_info("x2apic is disabled because BIOS sets x2apic opt out bit. You can use 'intremap=no_x2apic_optout' to override the BIOS setting.\n");
|
|
}
|
|
|
|
for_each_iommu(iommu, drhd) {
|
|
/*
|
|
* If the queued invalidation is already initialized,
|
|
* shouldn't disable it.
|
|
*/
|
|
if (iommu->qi)
|
|
continue;
|
|
|
|
/*
|
|
* Clear previous faults.
|
|
*/
|
|
dmar_fault(-1, iommu);
|
|
|
|
/*
|
|
* Disable intr remapping and queued invalidation, if already
|
|
* enabled prior to OS handover.
|
|
*/
|
|
iommu_disable_irq_remapping(iommu);
|
|
|
|
dmar_disable_qi(iommu);
|
|
}
|
|
|
|
/*
|
|
* check for the Interrupt-remapping support
|
|
*/
|
|
for_each_iommu(iommu, drhd)
|
|
if (eim && !ecap_eim_support(iommu->ecap)) {
|
|
printk(KERN_INFO "DRHD %Lx: EIM not supported by DRHD, "
|
|
" ecap %Lx\n", drhd->reg_base_addr, iommu->ecap);
|
|
eim = 0;
|
|
}
|
|
eim_mode = eim;
|
|
if (eim)
|
|
pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
|
|
|
|
/*
|
|
* Enable queued invalidation for all the DRHD's.
|
|
*/
|
|
for_each_iommu(iommu, drhd) {
|
|
int ret = dmar_enable_qi(iommu);
|
|
|
|
if (ret) {
|
|
printk(KERN_ERR "DRHD %Lx: failed to enable queued, "
|
|
" invalidation, ecap %Lx, ret %d\n",
|
|
drhd->reg_base_addr, iommu->ecap, ret);
|
|
goto error;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Setup Interrupt-remapping for all the DRHD's now.
|
|
*/
|
|
for_each_iommu(iommu, drhd) {
|
|
iommu_set_irq_remapping(iommu, eim);
|
|
setup = true;
|
|
}
|
|
|
|
if (!setup)
|
|
goto error;
|
|
|
|
irq_remapping_enabled = 1;
|
|
|
|
/*
|
|
* VT-d has a different layout for IO-APIC entries when
|
|
* interrupt remapping is enabled. So it needs a special routine
|
|
* to print IO-APIC entries for debugging purposes too.
|
|
*/
|
|
x86_io_apic_ops.print_entries = intel_ir_io_apic_print_entries;
|
|
|
|
pr_info("Enabled IRQ remapping in %s mode\n", eim ? "x2apic" : "xapic");
|
|
|
|
return eim ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE;
|
|
|
|
error:
|
|
intel_cleanup_irq_remapping();
|
|
return -1;
|
|
}
|
|
|
|
static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
|
|
struct intel_iommu *iommu,
|
|
struct acpi_dmar_hardware_unit *drhd)
|
|
{
|
|
struct acpi_dmar_pci_path *path;
|
|
u8 bus;
|
|
int count, free = -1;
|
|
|
|
bus = scope->bus;
|
|
path = (struct acpi_dmar_pci_path *)(scope + 1);
|
|
count = (scope->length - sizeof(struct acpi_dmar_device_scope))
|
|
/ sizeof(struct acpi_dmar_pci_path);
|
|
|
|
while (--count > 0) {
|
|
/*
|
|
* Access PCI directly due to the PCI
|
|
* subsystem isn't initialized yet.
|
|
*/
|
|
bus = read_pci_config_byte(bus, path->device, path->function,
|
|
PCI_SECONDARY_BUS);
|
|
path++;
|
|
}
|
|
|
|
for (count = 0; count < MAX_HPET_TBS; count++) {
|
|
if (ir_hpet[count].iommu == iommu &&
|
|
ir_hpet[count].id == scope->enumeration_id)
|
|
return 0;
|
|
else if (ir_hpet[count].iommu == NULL && free == -1)
|
|
free = count;
|
|
}
|
|
if (free == -1) {
|
|
pr_warn("Exceeded Max HPET blocks\n");
|
|
return -ENOSPC;
|
|
}
|
|
|
|
ir_hpet[free].iommu = iommu;
|
|
ir_hpet[free].id = scope->enumeration_id;
|
|
ir_hpet[free].bus = bus;
|
|
ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function);
|
|
pr_info("HPET id %d under DRHD base 0x%Lx\n",
|
|
scope->enumeration_id, drhd->address);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
|
|
struct intel_iommu *iommu,
|
|
struct acpi_dmar_hardware_unit *drhd)
|
|
{
|
|
struct acpi_dmar_pci_path *path;
|
|
u8 bus;
|
|
int count, free = -1;
|
|
|
|
bus = scope->bus;
|
|
path = (struct acpi_dmar_pci_path *)(scope + 1);
|
|
count = (scope->length - sizeof(struct acpi_dmar_device_scope))
|
|
/ sizeof(struct acpi_dmar_pci_path);
|
|
|
|
while (--count > 0) {
|
|
/*
|
|
* Access PCI directly due to the PCI
|
|
* subsystem isn't initialized yet.
|
|
*/
|
|
bus = read_pci_config_byte(bus, path->device, path->function,
|
|
PCI_SECONDARY_BUS);
|
|
path++;
|
|
}
|
|
|
|
for (count = 0; count < MAX_IO_APICS; count++) {
|
|
if (ir_ioapic[count].iommu == iommu &&
|
|
ir_ioapic[count].id == scope->enumeration_id)
|
|
return 0;
|
|
else if (ir_ioapic[count].iommu == NULL && free == -1)
|
|
free = count;
|
|
}
|
|
if (free == -1) {
|
|
pr_warn("Exceeded Max IO APICS\n");
|
|
return -ENOSPC;
|
|
}
|
|
|
|
ir_ioapic[free].bus = bus;
|
|
ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function);
|
|
ir_ioapic[free].iommu = iommu;
|
|
ir_ioapic[free].id = scope->enumeration_id;
|
|
pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n",
|
|
scope->enumeration_id, drhd->address, iommu->seq_id);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
|
|
struct intel_iommu *iommu)
|
|
{
|
|
int ret = 0;
|
|
struct acpi_dmar_hardware_unit *drhd;
|
|
struct acpi_dmar_device_scope *scope;
|
|
void *start, *end;
|
|
|
|
drhd = (struct acpi_dmar_hardware_unit *)header;
|
|
start = (void *)(drhd + 1);
|
|
end = ((void *)drhd) + header->length;
|
|
|
|
while (start < end && ret == 0) {
|
|
scope = start;
|
|
if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC)
|
|
ret = ir_parse_one_ioapic_scope(scope, iommu, drhd);
|
|
else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET)
|
|
ret = ir_parse_one_hpet_scope(scope, iommu, drhd);
|
|
start += scope->length;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < MAX_HPET_TBS; i++)
|
|
if (ir_hpet[i].iommu == iommu)
|
|
ir_hpet[i].iommu = NULL;
|
|
|
|
for (i = 0; i < MAX_IO_APICS; i++)
|
|
if (ir_ioapic[i].iommu == iommu)
|
|
ir_ioapic[i].iommu = NULL;
|
|
}
|
|
|
|
/*
|
|
* Finds the assocaition between IOAPIC's and its Interrupt-remapping
|
|
* hardware unit.
|
|
*/
|
|
static int __init parse_ioapics_under_ir(void)
|
|
{
|
|
struct dmar_drhd_unit *drhd;
|
|
struct intel_iommu *iommu;
|
|
bool ir_supported = false;
|
|
int ioapic_idx;
|
|
|
|
for_each_iommu(iommu, drhd)
|
|
if (ecap_ir_support(iommu->ecap)) {
|
|
if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu))
|
|
return -1;
|
|
|
|
ir_supported = true;
|
|
}
|
|
|
|
if (!ir_supported)
|
|
return 0;
|
|
|
|
for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
|
|
int ioapic_id = mpc_ioapic_id(ioapic_idx);
|
|
if (!map_ioapic_to_ir(ioapic_id)) {
|
|
pr_err(FW_BUG "ioapic %d has no mapping iommu, "
|
|
"interrupt remapping will be disabled\n",
|
|
ioapic_id);
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
static int __init ir_dev_scope_init(void)
|
|
{
|
|
int ret;
|
|
|
|
if (!irq_remapping_enabled)
|
|
return 0;
|
|
|
|
down_write(&dmar_global_lock);
|
|
ret = dmar_dev_scope_init();
|
|
up_write(&dmar_global_lock);
|
|
|
|
return ret;
|
|
}
|
|
rootfs_initcall(ir_dev_scope_init);
|
|
|
|
static void disable_irq_remapping(void)
|
|
{
|
|
struct dmar_drhd_unit *drhd;
|
|
struct intel_iommu *iommu = NULL;
|
|
|
|
/*
|
|
* Disable Interrupt-remapping for all the DRHD's now.
|
|
*/
|
|
for_each_iommu(iommu, drhd) {
|
|
if (!ecap_ir_support(iommu->ecap))
|
|
continue;
|
|
|
|
iommu_disable_irq_remapping(iommu);
|
|
}
|
|
}
|
|
|
|
static int reenable_irq_remapping(int eim)
|
|
{
|
|
struct dmar_drhd_unit *drhd;
|
|
bool setup = false;
|
|
struct intel_iommu *iommu = NULL;
|
|
|
|
for_each_iommu(iommu, drhd)
|
|
if (iommu->qi)
|
|
dmar_reenable_qi(iommu);
|
|
|
|
/*
|
|
* Setup Interrupt-remapping for all the DRHD's now.
|
|
*/
|
|
for_each_iommu(iommu, drhd) {
|
|
if (!ecap_ir_support(iommu->ecap))
|
|
continue;
|
|
|
|
/* Set up interrupt remapping for iommu.*/
|
|
iommu_set_irq_remapping(iommu, eim);
|
|
setup = true;
|
|
}
|
|
|
|
if (!setup)
|
|
goto error;
|
|
|
|
return 0;
|
|
|
|
error:
|
|
/*
|
|
* handle error condition gracefully here!
|
|
*/
|
|
return -1;
|
|
}
|
|
|
|
static void prepare_irte(struct irte *irte, int vector,
|
|
unsigned int dest)
|
|
{
|
|
memset(irte, 0, sizeof(*irte));
|
|
|
|
irte->present = 1;
|
|
irte->dst_mode = apic->irq_dest_mode;
|
|
/*
|
|
* Trigger mode in the IRTE will always be edge, and for IO-APIC, the
|
|
* actual level or edge trigger will be setup in the IO-APIC
|
|
* RTE. This will help simplify level triggered irq migration.
|
|
* For more details, see the comments (in io_apic.c) explainig IO-APIC
|
|
* irq migration in the presence of interrupt-remapping.
|
|
*/
|
|
irte->trigger_mode = 0;
|
|
irte->dlvry_mode = apic->irq_delivery_mode;
|
|
irte->vector = vector;
|
|
irte->dest_id = IRTE_DEST(dest);
|
|
irte->redir_hint = 1;
|
|
}
|
|
|
|
static int intel_setup_ioapic_entry(int irq,
|
|
struct IO_APIC_route_entry *route_entry,
|
|
unsigned int destination, int vector,
|
|
struct io_apic_irq_attr *attr)
|
|
{
|
|
int ioapic_id = mpc_ioapic_id(attr->ioapic);
|
|
struct intel_iommu *iommu;
|
|
struct IR_IO_APIC_route_entry *entry;
|
|
struct irte irte;
|
|
int index;
|
|
|
|
down_read(&dmar_global_lock);
|
|
iommu = map_ioapic_to_ir(ioapic_id);
|
|
if (!iommu) {
|
|
pr_warn("No mapping iommu for ioapic %d\n", ioapic_id);
|
|
index = -ENODEV;
|
|
} else {
|
|
index = alloc_irte(iommu, irq, 1);
|
|
if (index < 0) {
|
|
pr_warn("Failed to allocate IRTE for ioapic %d\n",
|
|
ioapic_id);
|
|
index = -ENOMEM;
|
|
}
|
|
}
|
|
up_read(&dmar_global_lock);
|
|
if (index < 0)
|
|
return index;
|
|
|
|
prepare_irte(&irte, vector, destination);
|
|
|
|
/* Set source-id of interrupt request */
|
|
set_ioapic_sid(&irte, ioapic_id);
|
|
|
|
modify_irte(irq, &irte);
|
|
|
|
apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: "
|
|
"Set IRTE entry (P:%d FPD:%d Dst_Mode:%d "
|
|
"Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X "
|
|
"Avail:%X Vector:%02X Dest:%08X "
|
|
"SID:%04X SQ:%X SVT:%X)\n",
|
|
attr->ioapic, irte.present, irte.fpd, irte.dst_mode,
|
|
irte.redir_hint, irte.trigger_mode, irte.dlvry_mode,
|
|
irte.avail, irte.vector, irte.dest_id,
|
|
irte.sid, irte.sq, irte.svt);
|
|
|
|
entry = (struct IR_IO_APIC_route_entry *)route_entry;
|
|
memset(entry, 0, sizeof(*entry));
|
|
|
|
entry->index2 = (index >> 15) & 0x1;
|
|
entry->zero = 0;
|
|
entry->format = 1;
|
|
entry->index = (index & 0x7fff);
|
|
/*
|
|
* IO-APIC RTE will be configured with virtual vector.
|
|
* irq handler will do the explicit EOI to the io-apic.
|
|
*/
|
|
entry->vector = attr->ioapic_pin;
|
|
entry->mask = 0; /* enable IRQ */
|
|
entry->trigger = attr->trigger;
|
|
entry->polarity = attr->polarity;
|
|
|
|
/* Mask level triggered irqs.
|
|
* Use IRQ_DELAYED_DISABLE for edge triggered irqs.
|
|
*/
|
|
if (attr->trigger)
|
|
entry->mask = 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Migrate the IO-APIC irq in the presence of intr-remapping.
|
|
*
|
|
* For both level and edge triggered, irq migration is a simple atomic
|
|
* update(of vector and cpu destination) of IRTE and flush the hardware cache.
|
|
*
|
|
* For level triggered, we eliminate the io-apic RTE modification (with the
|
|
* updated vector information), by using a virtual vector (io-apic pin number).
|
|
* Real vector that is used for interrupting cpu will be coming from
|
|
* the interrupt-remapping table entry.
|
|
*
|
|
* As the migration is a simple atomic update of IRTE, the same mechanism
|
|
* is used to migrate MSI irq's in the presence of interrupt-remapping.
|
|
*/
|
|
static int
|
|
intel_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
|
|
bool force)
|
|
{
|
|
struct irq_cfg *cfg = irqd_cfg(data);
|
|
unsigned int dest, irq = data->irq;
|
|
struct irte irte;
|
|
int err;
|
|
|
|
if (!config_enabled(CONFIG_SMP))
|
|
return -EINVAL;
|
|
|
|
if (!cpumask_intersects(mask, cpu_online_mask))
|
|
return -EINVAL;
|
|
|
|
if (get_irte(irq, &irte))
|
|
return -EBUSY;
|
|
|
|
err = assign_irq_vector(irq, cfg, mask);
|
|
if (err)
|
|
return err;
|
|
|
|
err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest);
|
|
if (err) {
|
|
if (assign_irq_vector(irq, cfg, data->affinity))
|
|
pr_err("Failed to recover vector for irq %d\n", irq);
|
|
return err;
|
|
}
|
|
|
|
irte.vector = cfg->vector;
|
|
irte.dest_id = IRTE_DEST(dest);
|
|
|
|
/*
|
|
* Atomically updates the IRTE with the new destination, vector
|
|
* and flushes the interrupt entry cache.
|
|
*/
|
|
modify_irte(irq, &irte);
|
|
|
|
/*
|
|
* After this point, all the interrupts will start arriving
|
|
* at the new destination. So, time to cleanup the previous
|
|
* vector allocation.
|
|
*/
|
|
if (cfg->move_in_progress)
|
|
send_cleanup_vector(cfg);
|
|
|
|
cpumask_copy(data->affinity, mask);
|
|
return 0;
|
|
}
|
|
|
|
static void intel_compose_msi_msg(struct pci_dev *pdev,
|
|
unsigned int irq, unsigned int dest,
|
|
struct msi_msg *msg, u8 hpet_id)
|
|
{
|
|
struct irq_cfg *cfg;
|
|
struct irte irte;
|
|
u16 sub_handle = 0;
|
|
int ir_index;
|
|
|
|
cfg = irq_cfg(irq);
|
|
|
|
ir_index = map_irq_to_irte_handle(irq, &sub_handle);
|
|
BUG_ON(ir_index == -1);
|
|
|
|
prepare_irte(&irte, cfg->vector, dest);
|
|
|
|
/* Set source-id of interrupt request */
|
|
if (pdev)
|
|
set_msi_sid(&irte, pdev);
|
|
else
|
|
set_hpet_sid(&irte, hpet_id);
|
|
|
|
modify_irte(irq, &irte);
|
|
|
|
msg->address_hi = MSI_ADDR_BASE_HI;
|
|
msg->data = sub_handle;
|
|
msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
|
|
MSI_ADDR_IR_SHV |
|
|
MSI_ADDR_IR_INDEX1(ir_index) |
|
|
MSI_ADDR_IR_INDEX2(ir_index);
|
|
}
|
|
|
|
/*
|
|
* Map the PCI dev to the corresponding remapping hardware unit
|
|
* and allocate 'nvec' consecutive interrupt-remapping table entries
|
|
* in it.
|
|
*/
|
|
static int intel_msi_alloc_irq(struct pci_dev *dev, int irq, int nvec)
|
|
{
|
|
struct intel_iommu *iommu;
|
|
int index;
|
|
|
|
down_read(&dmar_global_lock);
|
|
iommu = map_dev_to_ir(dev);
|
|
if (!iommu) {
|
|
printk(KERN_ERR
|
|
"Unable to map PCI %s to iommu\n", pci_name(dev));
|
|
index = -ENOENT;
|
|
} else {
|
|
index = alloc_irte(iommu, irq, nvec);
|
|
if (index < 0) {
|
|
printk(KERN_ERR
|
|
"Unable to allocate %d IRTE for PCI %s\n",
|
|
nvec, pci_name(dev));
|
|
index = -ENOSPC;
|
|
}
|
|
}
|
|
up_read(&dmar_global_lock);
|
|
|
|
return index;
|
|
}
|
|
|
|
static int intel_msi_setup_irq(struct pci_dev *pdev, unsigned int irq,
|
|
int index, int sub_handle)
|
|
{
|
|
struct intel_iommu *iommu;
|
|
int ret = -ENOENT;
|
|
|
|
down_read(&dmar_global_lock);
|
|
iommu = map_dev_to_ir(pdev);
|
|
if (iommu) {
|
|
/*
|
|
* setup the mapping between the irq and the IRTE
|
|
* base index, the sub_handle pointing to the
|
|
* appropriate interrupt remap table entry.
|
|
*/
|
|
set_irte_irq(irq, iommu, index, sub_handle);
|
|
ret = 0;
|
|
}
|
|
up_read(&dmar_global_lock);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int intel_alloc_hpet_msi(unsigned int irq, unsigned int id)
|
|
{
|
|
int ret = -1;
|
|
struct intel_iommu *iommu;
|
|
int index;
|
|
|
|
down_read(&dmar_global_lock);
|
|
iommu = map_hpet_to_ir(id);
|
|
if (iommu) {
|
|
index = alloc_irte(iommu, irq, 1);
|
|
if (index >= 0)
|
|
ret = 0;
|
|
}
|
|
up_read(&dmar_global_lock);
|
|
|
|
return ret;
|
|
}
|
|
|
|
struct irq_remap_ops intel_irq_remap_ops = {
|
|
.prepare = intel_prepare_irq_remapping,
|
|
.enable = intel_enable_irq_remapping,
|
|
.disable = disable_irq_remapping,
|
|
.reenable = reenable_irq_remapping,
|
|
.enable_faulting = enable_drhd_fault_handling,
|
|
.setup_ioapic_entry = intel_setup_ioapic_entry,
|
|
.set_affinity = intel_ioapic_set_affinity,
|
|
.free_irq = free_irte,
|
|
.compose_msi_msg = intel_compose_msi_msg,
|
|
.msi_alloc_irq = intel_msi_alloc_irq,
|
|
.msi_setup_irq = intel_msi_setup_irq,
|
|
.alloc_hpet_msi = intel_alloc_hpet_msi,
|
|
};
|
|
|
|
/*
|
|
* Support of Interrupt Remapping Unit Hotplug
|
|
*/
|
|
static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu)
|
|
{
|
|
int ret;
|
|
int eim = x2apic_enabled();
|
|
|
|
if (eim && !ecap_eim_support(iommu->ecap)) {
|
|
pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n",
|
|
iommu->reg_phys, iommu->ecap);
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) {
|
|
pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n",
|
|
iommu->reg_phys);
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* TODO: check all IOAPICs are covered by IOMMU */
|
|
|
|
/* Setup Interrupt-remapping now. */
|
|
ret = intel_setup_irq_remapping(iommu);
|
|
if (ret) {
|
|
pr_err("DRHD %Lx: failed to allocate resource\n",
|
|
iommu->reg_phys);
|
|
ir_remove_ioapic_hpet_scope(iommu);
|
|
return ret;
|
|
}
|
|
|
|
if (!iommu->qi) {
|
|
/* Clear previous faults. */
|
|
dmar_fault(-1, iommu);
|
|
iommu_disable_irq_remapping(iommu);
|
|
dmar_disable_qi(iommu);
|
|
}
|
|
|
|
/* Enable queued invalidation */
|
|
ret = dmar_enable_qi(iommu);
|
|
if (!ret) {
|
|
iommu_set_irq_remapping(iommu, eim);
|
|
} else {
|
|
pr_err("DRHD %Lx: failed to enable queued invalidation, ecap %Lx, ret %d\n",
|
|
iommu->reg_phys, iommu->ecap, ret);
|
|
intel_teardown_irq_remapping(iommu);
|
|
ir_remove_ioapic_hpet_scope(iommu);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
|
|
{
|
|
int ret = 0;
|
|
struct intel_iommu *iommu = dmaru->iommu;
|
|
|
|
if (!irq_remapping_enabled)
|
|
return 0;
|
|
if (iommu == NULL)
|
|
return -EINVAL;
|
|
if (!ecap_ir_support(iommu->ecap))
|
|
return 0;
|
|
|
|
if (insert) {
|
|
if (!iommu->ir_table)
|
|
ret = dmar_ir_add(dmaru, iommu);
|
|
} else {
|
|
if (iommu->ir_table) {
|
|
if (!bitmap_empty(iommu->ir_table->bitmap,
|
|
INTR_REMAP_TABLE_ENTRIES)) {
|
|
ret = -EBUSY;
|
|
} else {
|
|
iommu_disable_irq_remapping(iommu);
|
|
intel_teardown_irq_remapping(iommu);
|
|
ir_remove_ioapic_hpet_scope(iommu);
|
|
}
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|