![Linus Torvalds](/assets/img/avatar_default.png)
Highlights: - Major rework of Book3S 64-bit exception vectors (Nicholas Piggin) - Use gas sections for arranging exception vectors et. al. - Large set of TM cleanups and selftests (Cyril Bur) - Enable transactional memory (TM) lazily for userspace (Cyril Bur) - Support for XZ compression in the zImage wrapper (Oliver O'Halloran) - Add support for bpf constant blinding (Naveen N. Rao) - Beginnings of upstream support for PA Semi Nemo motherboards (Darren Stevens) Fixes: - Ensure .mem(init|exit).text are within _stext/_etext (Michael Ellerman) - xmon: Don't use ld on 32-bit (Michael Ellerman) - vdso64: Use double word compare on pointers (Anton Blanchard) - powerpc/nvram: Fix an incorrect partition merge (Pan Xinhui) - powerpc: Fix usage of _PAGE_RO in hugepage (Christophe Leroy) - powerpc/mm: Update FORCE_MAX_ZONEORDER range to allow hugetlb w/4K (Aneesh Kumar K.V) - Fix memory leak in queue_hotplug_event() error path (Andrew Donnellan) - Replay hypervisor maintenance interrupt first (Nicholas Piggin) Cleanups & features: - Sparse fixes/cleanups (Daniel Axtens) - Preserve CFAR value on SLB miss caused by access to bogus address (Paul Mackerras) - Radix MMU fixups for POWER9 (Aneesh Kumar K.V) - Support for setting used_(vsr|vr|spe) in sigreturn path (for CRIU) (Simon Guo) - Optimise syscall entry for virtual, relocatable case (Nicholas Piggin) - Optimise MSR handling in exception handling (Nicholas Piggin) - Support for kexec with Radix MMU (Benjamin Herrenschmidt) - powernv EEH fixes (Russell Currey) - Suprise PCI hotplug support for powernv (Gavin Shan) - Endian/sparse fixes for powernv PCI (Gavin Shan) - Defconfig updates (Anton Blanchard) - Various performance optimisations (Anton Blanchard) - Align hot loops of memset() and backwards_memcpy() - During context switch, check before setting mm_cpumask - Remove static branch prediction in atomic{, 64}_add_unless - Only disable HAVE_EFFICIENT_UNALIGNED_ACCESS on POWER7 little endian - Set default CPU type to POWER8 for little endian builds - KVM: PPC: Book3S HV: Migrate pinned pages out of CMA (Balbir Singh) - cxl: Flush PSL cache before resetting the adapter (Frederic Barrat) - cxl: replace loop with for_each_child_of_node(), remove unneeded of_node_put() (Andrew Donnellan) - Fix HV facility unavailable to use correct handler (Nicholas Piggin) - Remove unnecessary syscall trampoline (Nicholas Piggin) - fadump: Fix build break when CONFIG_PROC_VMCORE=n (Michael Ellerman) - Quieten EEH message when no adapters are found (Anton Blanchard) - powernv: Add PHB register dump debugfs handle (Russell Currey) - Use kprobe blacklist for exception handlers & asm functions (Nicholas Piggin) - Document the syscall ABI (Nicholas Piggin) - MAINTAINERS: Update cxl maintainers (Michael Neuling) - powerpc: Remove all usages of NO_IRQ (Michael Ellerman) Minor cleanups: - Andrew Donnellan, Christophe Leroy, Colin Ian King, Cyril Bur, Frederic Barrat, Pan Xinhui, PrasannaKumar Muralidharan, Rui Teng, Simon Guo. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJX9x5ZAAoJEFHr6jzI4aWAWQ0P+gOhdtayMsRY0k0dzPmYaFr0 Ha5v968RJaNIyGGM9ARJg8h27PGMaSlBp/9zaYdk1G7xfv/DMR0uq8d8l5pjy/Zw Jm72WE4PEX/zAcQxry6Y2fDdumO09crTBA/W0hM1UZzqu0bcVUfD+E51ZFYWW7yh fyhT2YnlucxIcT34pxsLqwTIiZYG4xgN3+YGo0wohY1D1GHE3UZ7SXIglb49yM6v ZeXrL7SOdERR1w88rC+g99P/cWng5HDS0wPLUbxGT5KIpoOSXOs7EbZwFqQBUy5O 37PB07K5dDyUbrm++l5lUigldF3W1OZQBN5+n8PciulxxwFX84pllTlAxv1p60JR piEKZ8pl023IF7zMGatUG9qcNOcnbxdMsAhoEhlcFi9ulM/yLzbmRTKVfDYm+O/J UI+YtcbsgdyOXMdGXCqdpeBNuuypgLG/g7gC8bnk3taS0LUUZLcXtRNuE4tcPJJe v8FnszaLkjAi83Lmzt3fgZo7DI1RIPwDSw6fY+nBrxCRfEPRVx3f7KhmUXvSeol5 Ln9xpk4AtyQt1RHhckxXwWSUgvXVg2ltmz7ElqK4sQ9mO/D2ZIs6R6fPY4VlJLc4 /2yIV4RLIsbHmdv9IbJ8PBp0VTugSNdicZ904QiAHSZQv/i1mgYuXw3tjR6kuy9f bKOzNJTwLV1WUsOlUpiq =Jnn8 -----END PGP SIGNATURE----- Merge tag 'powerpc-4.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Pull powerpc updates from Michael Ellerman: "Highlights: - Major rework of Book3S 64-bit exception vectors (Nicholas Piggin) - Use gas sections for arranging exception vectors et. al. - Large set of TM cleanups and selftests (Cyril Bur) - Enable transactional memory (TM) lazily for userspace (Cyril Bur) - Support for XZ compression in the zImage wrapper (Oliver O'Halloran) - Add support for bpf constant blinding (Naveen N. Rao) - Beginnings of upstream support for PA Semi Nemo motherboards (Darren Stevens) Fixes: - Ensure .mem(init|exit).text are within _stext/_etext (Michael Ellerman) - xmon: Don't use ld on 32-bit (Michael Ellerman) - vdso64: Use double word compare on pointers (Anton Blanchard) - powerpc/nvram: Fix an incorrect partition merge (Pan Xinhui) - powerpc: Fix usage of _PAGE_RO in hugepage (Christophe Leroy) - powerpc/mm: Update FORCE_MAX_ZONEORDER range to allow hugetlb w/4K (Aneesh Kumar K.V) - Fix memory leak in queue_hotplug_event() error path (Andrew Donnellan) - Replay hypervisor maintenance interrupt first (Nicholas Piggin) Various performance optimisations (Anton Blanchard): - Align hot loops of memset() and backwards_memcpy() - During context switch, check before setting mm_cpumask - Remove static branch prediction in atomic{, 64}_add_unless - Only disable HAVE_EFFICIENT_UNALIGNED_ACCESS on POWER7 little endian - Set default CPU type to POWER8 for little endian builds Cleanups & features: - Sparse fixes/cleanups (Daniel Axtens) - Preserve CFAR value on SLB miss caused by access to bogus address (Paul Mackerras) - Radix MMU fixups for POWER9 (Aneesh Kumar K.V) - Support for setting used_(vsr|vr|spe) in sigreturn path (for CRIU) (Simon Guo) - Optimise syscall entry for virtual, relocatable case (Nicholas Piggin) - Optimise MSR handling in exception handling (Nicholas Piggin) - Support for kexec with Radix MMU (Benjamin Herrenschmidt) - powernv EEH fixes (Russell Currey) - Suprise PCI hotplug support for powernv (Gavin Shan) - Endian/sparse fixes for powernv PCI (Gavin Shan) - Defconfig updates (Anton Blanchard) - KVM: PPC: Book3S HV: Migrate pinned pages out of CMA (Balbir Singh) - cxl: Flush PSL cache before resetting the adapter (Frederic Barrat) - cxl: replace loop with for_each_child_of_node(), remove unneeded of_node_put() (Andrew Donnellan) - Fix HV facility unavailable to use correct handler (Nicholas Piggin) - Remove unnecessary syscall trampoline (Nicholas Piggin) - fadump: Fix build break when CONFIG_PROC_VMCORE=n (Michael Ellerman) - Quieten EEH message when no adapters are found (Anton Blanchard) - powernv: Add PHB register dump debugfs handle (Russell Currey) - Use kprobe blacklist for exception handlers & asm functions (Nicholas Piggin) - Document the syscall ABI (Nicholas Piggin) - MAINTAINERS: Update cxl maintainers (Michael Neuling) - powerpc: Remove all usages of NO_IRQ (Michael Ellerman) Minor cleanups: - Andrew Donnellan, Christophe Leroy, Colin Ian King, Cyril Bur, Frederic Barrat, Pan Xinhui, PrasannaKumar Muralidharan, Rui Teng, Simon Guo" * tag 'powerpc-4.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (156 commits) powerpc/bpf: Add support for bpf constant blinding powerpc/bpf: Implement support for tail calls powerpc/bpf: Introduce accessors for using the tmp local stack space powerpc/fadump: Fix build break when CONFIG_PROC_VMCORE=n powerpc: tm: Enable transactional memory (TM) lazily for userspace powerpc/tm: Add TM Unavailable Exception powerpc: Remove do_load_up_transact_{fpu,altivec} powerpc: tm: Rename transct_(*) to ck(\1)_state powerpc: tm: Always use fp_state and vr_state to store live registers selftests/powerpc: Add checks for transactional VSXs in signal contexts selftests/powerpc: Add checks for transactional VMXs in signal contexts selftests/powerpc: Add checks for transactional FPUs in signal contexts selftests/powerpc: Add checks for transactional GPRs in signal contexts selftests/powerpc: Check that signals always get delivered selftests/powerpc: Add TM tcheck helpers in C selftests/powerpc: Allow tests to extend their kill timeout selftests/powerpc: Introduce GPR asm helper header file selftests/powerpc: Move VMX stack frame macros to header file selftests/powerpc: Rework FPU stack placement macros and move to header file selftests/powerpc: Check for VSX preservation across userspace preemption ...
275 lines
7.4 KiB
ArmAsm
275 lines
7.4 KiB
ArmAsm
/*
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* Low-level SLB routines
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*
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* Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
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*
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* Based on earlier C version:
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* Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
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* Copyright (c) 2001 Dave Engebretsen
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* Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/processor.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/cputable.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/pgtable.h>
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#include <asm/firmware.h>
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/* void slb_allocate_realmode(unsigned long ea);
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*
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* Create an SLB entry for the given EA (user or kernel).
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* r3 = faulting address, r13 = PACA
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* r9, r10, r11 are clobbered by this function
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* No other registers are examined or changed.
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*/
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_GLOBAL(slb_allocate_realmode)
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/*
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* check for bad kernel/user address
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* (ea & ~REGION_MASK) >= PGTABLE_RANGE
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*/
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rldicr. r9,r3,4,(63 - H_PGTABLE_EADDR_SIZE - 4)
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bne- 8f
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srdi r9,r3,60 /* get region */
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srdi r10,r3,SID_SHIFT /* get esid */
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cmpldi cr7,r9,0xc /* cmp PAGE_OFFSET for later use */
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/* r3 = address, r10 = esid, cr7 = <> PAGE_OFFSET */
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blt cr7,0f /* user or kernel? */
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/* kernel address: proto-VSID = ESID */
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/* WARNING - MAGIC: we don't use the VSID 0xfffffffff, but
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* this code will generate the protoVSID 0xfffffffff for the
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* top segment. That's ok, the scramble below will translate
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* it to VSID 0, which is reserved as a bad VSID - one which
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* will never have any pages in it. */
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/* Check if hitting the linear mapping or some other kernel space
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*/
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bne cr7,1f
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/* Linear mapping encoding bits, the "li" instruction below will
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* be patched by the kernel at boot
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*/
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.globl slb_miss_kernel_load_linear
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slb_miss_kernel_load_linear:
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li r11,0
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/*
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* context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1
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* r9 = region id.
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*/
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addis r9,r9,(MAX_USER_CONTEXT - 0xc + 1)@ha
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addi r9,r9,(MAX_USER_CONTEXT - 0xc + 1)@l
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BEGIN_FTR_SECTION
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b slb_finish_load
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END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
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b slb_finish_load_1T
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1:
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#ifdef CONFIG_SPARSEMEM_VMEMMAP
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/* Check virtual memmap region. To be patches at kernel boot */
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cmpldi cr0,r9,0xf
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bne 1f
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.globl slb_miss_kernel_load_vmemmap
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slb_miss_kernel_load_vmemmap:
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li r11,0
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b 6f
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1:
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#endif /* CONFIG_SPARSEMEM_VMEMMAP */
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/* vmalloc mapping gets the encoding from the PACA as the mapping
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* can be demoted from 64K -> 4K dynamically on some machines
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*/
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clrldi r11,r10,48
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cmpldi r11,(H_VMALLOC_SIZE >> 28) - 1
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bgt 5f
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lhz r11,PACAVMALLOCSLLP(r13)
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b 6f
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5:
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/* IO mapping */
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.globl slb_miss_kernel_load_io
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slb_miss_kernel_load_io:
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li r11,0
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6:
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/*
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* context = (MAX_USER_CONTEXT) + ((ea >> 60) - 0xc) + 1
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* r9 = region id.
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*/
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addis r9,r9,(MAX_USER_CONTEXT - 0xc + 1)@ha
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addi r9,r9,(MAX_USER_CONTEXT - 0xc + 1)@l
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BEGIN_FTR_SECTION
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b slb_finish_load
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END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
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b slb_finish_load_1T
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0: /*
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* For userspace addresses, make sure this is region 0.
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*/
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cmpdi r9, 0
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bne 8f
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/* when using slices, we extract the psize off the slice bitmaps
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* and then we need to get the sllp encoding off the mmu_psize_defs
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* array.
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*
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* XXX This is a bit inefficient especially for the normal case,
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* so we should try to implement a fast path for the standard page
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* size using the old sllp value so we avoid the array. We cannot
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* really do dynamic patching unfortunately as processes might flip
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* between 4k and 64k standard page size
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*/
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#ifdef CONFIG_PPC_MM_SLICES
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/* r10 have esid */
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cmpldi r10,16
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/* below SLICE_LOW_TOP */
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blt 5f
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/*
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* Handle hpsizes,
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* r9 is get_paca()->context.high_slices_psize[index], r11 is mask_index
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*/
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srdi r11,r10,(SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT + 1) /* index */
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addi r9,r11,PACAHIGHSLICEPSIZE
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lbzx r9,r13,r9 /* r9 is hpsizes[r11] */
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/* r11 = (r10 >> (SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT)) & 0x1 */
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rldicl r11,r10,(64 - (SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT)),63
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b 6f
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5:
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/*
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* Handle lpsizes
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* r9 is get_paca()->context.low_slices_psize, r11 is index
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*/
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ld r9,PACALOWSLICESPSIZE(r13)
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mr r11,r10
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6:
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sldi r11,r11,2 /* index * 4 */
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/* Extract the psize and multiply to get an array offset */
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srd r9,r9,r11
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andi. r9,r9,0xf
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mulli r9,r9,MMUPSIZEDEFSIZE
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/* Now get to the array and obtain the sllp
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*/
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ld r11,PACATOC(r13)
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ld r11,mmu_psize_defs@got(r11)
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add r11,r11,r9
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ld r11,MMUPSIZESLLP(r11)
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ori r11,r11,SLB_VSID_USER
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#else
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/* paca context sllp already contains the SLB_VSID_USER bits */
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lhz r11,PACACONTEXTSLLP(r13)
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#endif /* CONFIG_PPC_MM_SLICES */
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ld r9,PACACONTEXTID(r13)
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BEGIN_FTR_SECTION
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cmpldi r10,0x1000
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bge slb_finish_load_1T
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END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
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b slb_finish_load
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8: /* invalid EA - return an error indication */
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crset 4*cr0+eq /* indicate failure */
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blr
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/*
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* Finish loading of an SLB entry and return
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*
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* r3 = EA, r9 = context, r10 = ESID, r11 = flags, clobbers r9, cr7 = <> PAGE_OFFSET
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*/
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slb_finish_load:
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rldimi r10,r9,ESID_BITS,0
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ASM_VSID_SCRAMBLE(r10,r9,256M)
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/*
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* bits above VSID_BITS_256M need to be ignored from r10
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* also combine VSID and flags
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*/
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rldimi r11,r10,SLB_VSID_SHIFT,(64 - (SLB_VSID_SHIFT + VSID_BITS_256M))
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/* r3 = EA, r11 = VSID data */
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/*
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* Find a slot, round robin. Previously we tried to find a
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* free slot first but that took too long. Unfortunately we
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* dont have any LRU information to help us choose a slot.
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*/
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7: ld r10,PACASTABRR(r13)
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addi r10,r10,1
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/* This gets soft patched on boot. */
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.globl slb_compare_rr_to_size
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slb_compare_rr_to_size:
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cmpldi r10,0
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blt+ 4f
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li r10,SLB_NUM_BOLTED
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4:
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std r10,PACASTABRR(r13)
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3:
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rldimi r3,r10,0,36 /* r3= EA[0:35] | entry */
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oris r10,r3,SLB_ESID_V@h /* r3 |= SLB_ESID_V */
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/* r3 = ESID data, r11 = VSID data */
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/*
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* No need for an isync before or after this slbmte. The exception
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* we enter with and the rfid we exit with are context synchronizing.
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*/
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slbmte r11,r10
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/* we're done for kernel addresses */
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crclr 4*cr0+eq /* set result to "success" */
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bgelr cr7
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/* Update the slb cache */
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lhz r3,PACASLBCACHEPTR(r13) /* offset = paca->slb_cache_ptr */
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cmpldi r3,SLB_CACHE_ENTRIES
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bge 1f
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/* still room in the slb cache */
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sldi r11,r3,2 /* r11 = offset * sizeof(u32) */
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srdi r10,r10,28 /* get the 36 bits of the ESID */
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add r11,r11,r13 /* r11 = (u32 *)paca + offset */
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stw r10,PACASLBCACHE(r11) /* paca->slb_cache[offset] = esid */
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addi r3,r3,1 /* offset++ */
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b 2f
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1: /* offset >= SLB_CACHE_ENTRIES */
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li r3,SLB_CACHE_ENTRIES+1
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2:
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sth r3,PACASLBCACHEPTR(r13) /* paca->slb_cache_ptr = offset */
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crclr 4*cr0+eq /* set result to "success" */
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blr
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/*
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* Finish loading of a 1T SLB entry (for the kernel linear mapping) and return.
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*
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* r3 = EA, r9 = context, r10 = ESID(256MB), r11 = flags, clobbers r9
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*/
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slb_finish_load_1T:
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srdi r10,r10,(SID_SHIFT_1T - SID_SHIFT) /* get 1T ESID */
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rldimi r10,r9,ESID_BITS_1T,0
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ASM_VSID_SCRAMBLE(r10,r9,1T)
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/*
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* bits above VSID_BITS_1T need to be ignored from r10
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* also combine VSID and flags
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*/
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rldimi r11,r10,SLB_VSID_SHIFT_1T,(64 - (SLB_VSID_SHIFT_1T + VSID_BITS_1T))
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li r10,MMU_SEGSIZE_1T
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rldimi r11,r10,SLB_VSID_SSIZE_SHIFT,0 /* insert segment size */
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/* r3 = EA, r11 = VSID data */
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clrrdi r3,r3,SID_SHIFT_1T /* clear out non-ESID bits */
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b 7b
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