3677d4c6a2
In this initial implementation we force-require 5-level paging support from the hardware, when compiled with CONFIG_X86_5LEVEL=y. (The kernel will panic during boot on CPUs that don't support 5-level paging.) We will implement boot-time switch between 4- and 5-level paging later. Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Andy Lutomirski <luto@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Dave Hansen <dave.hansen@intel.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-arch@vger.kernel.org Cc: linux-mm@kvack.org Link: http://lkml.kernel.org/r/20170330080731.65421-2-kirill.shutemov@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
129 lines
2.9 KiB
C
129 lines
2.9 KiB
C
#include <linux/types.h>
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#include "bitops.h"
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#include <asm/processor-flags.h>
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#include <asm/required-features.h>
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#include <asm/msr-index.h>
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#include "cpuflags.h"
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struct cpu_features cpu;
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u32 cpu_vendor[3];
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static bool loaded_flags;
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static int has_fpu(void)
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{
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u16 fcw = -1, fsw = -1;
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unsigned long cr0;
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asm volatile("mov %%cr0,%0" : "=r" (cr0));
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if (cr0 & (X86_CR0_EM|X86_CR0_TS)) {
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cr0 &= ~(X86_CR0_EM|X86_CR0_TS);
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asm volatile("mov %0,%%cr0" : : "r" (cr0));
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}
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asm volatile("fninit ; fnstsw %0 ; fnstcw %1"
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: "+m" (fsw), "+m" (fcw));
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return fsw == 0 && (fcw & 0x103f) == 0x003f;
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}
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/*
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* For building the 16-bit code we want to explicitly specify 32-bit
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* push/pop operations, rather than just saying 'pushf' or 'popf' and
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* letting the compiler choose. But this is also included from the
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* compressed/ directory where it may be 64-bit code, and thus needs
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* to be 'pushfq' or 'popfq' in that case.
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*/
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#ifdef __x86_64__
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#define PUSHF "pushfq"
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#define POPF "popfq"
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#else
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#define PUSHF "pushfl"
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#define POPF "popfl"
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#endif
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int has_eflag(unsigned long mask)
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{
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unsigned long f0, f1;
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asm volatile(PUSHF " \n\t"
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PUSHF " \n\t"
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"pop %0 \n\t"
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"mov %0,%1 \n\t"
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"xor %2,%1 \n\t"
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"push %1 \n\t"
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POPF " \n\t"
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PUSHF " \n\t"
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"pop %1 \n\t"
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POPF
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: "=&r" (f0), "=&r" (f1)
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: "ri" (mask));
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return !!((f0^f1) & mask);
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}
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/* Handle x86_32 PIC using ebx. */
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#if defined(__i386__) && defined(__PIC__)
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# define EBX_REG "=r"
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#else
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# define EBX_REG "=b"
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#endif
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static inline void cpuid_count(u32 id, u32 count,
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u32 *a, u32 *b, u32 *c, u32 *d)
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{
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asm volatile(".ifnc %%ebx,%3 ; movl %%ebx,%3 ; .endif \n\t"
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"cpuid \n\t"
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".ifnc %%ebx,%3 ; xchgl %%ebx,%3 ; .endif \n\t"
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: "=a" (*a), "=c" (*c), "=d" (*d), EBX_REG (*b)
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: "a" (id), "c" (count)
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);
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}
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#define cpuid(id, a, b, c, d) cpuid_count(id, 0, a, b, c, d)
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void get_cpuflags(void)
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{
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u32 max_intel_level, max_amd_level;
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u32 tfms;
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u32 ignored;
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if (loaded_flags)
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return;
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loaded_flags = true;
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if (has_fpu())
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set_bit(X86_FEATURE_FPU, cpu.flags);
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if (has_eflag(X86_EFLAGS_ID)) {
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cpuid(0x0, &max_intel_level, &cpu_vendor[0], &cpu_vendor[2],
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&cpu_vendor[1]);
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if (max_intel_level >= 0x00000001 &&
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max_intel_level <= 0x0000ffff) {
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cpuid(0x1, &tfms, &ignored, &cpu.flags[4],
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&cpu.flags[0]);
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cpu.level = (tfms >> 8) & 15;
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cpu.family = cpu.level;
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cpu.model = (tfms >> 4) & 15;
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if (cpu.level >= 6)
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cpu.model += ((tfms >> 16) & 0xf) << 4;
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}
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if (max_intel_level >= 0x00000007) {
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cpuid_count(0x00000007, 0, &ignored, &ignored,
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&cpu.flags[16], &ignored);
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}
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cpuid(0x80000000, &max_amd_level, &ignored, &ignored,
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&ignored);
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if (max_amd_level >= 0x80000001 &&
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max_amd_level <= 0x8000ffff) {
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cpuid(0x80000001, &ignored, &ignored, &cpu.flags[6],
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&cpu.flags[1]);
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}
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}
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}
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