167 lines
5.5 KiB
C
167 lines
5.5 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2016-2017 Cadence Design Systems, Inc.
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* All rights reserved worldwide.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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* INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
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* OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Copyright 2017-2018 NXP
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*
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******************************************************************************
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*
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* This file was auto-generated. Do not edit it manually.
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*
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******************************************************************************
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*
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* general_handler.h
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*
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******************************************************************************
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*/
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#ifndef GENERAL_HANDLER_H
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#define GENERAL_HANDLER_H
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/**
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* \file
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* \brief general handler, checks available messages, receives it from mailbox, handles requests and sends response to the host
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*/
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#define DP_TX_MAIL_HANDLER_REQUEST_BUFFER_LEN 256
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/**
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* \brief opcode defines host->controller
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*/
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#define GENERAL_MAIN_CONTROL 0x01
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#define GENERAL_TEST_ECHO 0x02
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#define GENERAL_BUS_SETTINGS 0x03
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#define GENERAL_TEST_ACCESS 0x04
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#define GENERAL_WRITE_REGISTER 0x05
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#define GENERAL_WRITE_FIELD 0x06
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#define GENERAL_READ_REGISTER 0x07
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#define GENERAL_GET_HPD_STATE 0x11
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#define GENERAL_TEST_TRNG_SIMPLE 0xF0
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#define GENERAL_MAIN_CONTROL_SET_ACTIVE_BIT 0
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#define GENERAL_MAIN_CONTROL_SET_ALT_CIPHER_ADDR 1
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#define GENERAL_MAIN_CONTROL_SET_FAST_HDCP_DELAYS 2
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#define GENERAL_BUS_SETTINGS_DPCD_BUS_BIT 0
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#define GENERAL_BUS_SETTINGS_DPCD_BUS_LOCK_BIT 1
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#define GENERAL_BUS_SETTINGS_HDCP_BUS_BIT 2
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#define GENERAL_BUS_SETTINGS_HDCP_BUS_LOCK_BIT 3
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#define GENERAL_BUS_SETTINGS_CAPB_OWNER_BIT 4
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#define GENERAL_BUS_SETTINGS_CAPB_OWNER_LOCK_BIT 5
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/**
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* \brief opcode defines controller->host
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*/
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#define GENERAL_MAIN_CONTROL_RESP 0x01
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#define GENERAL_TEST_ECHO_RESP 0x02
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#define GENERAL_BUS_SETTINGS_RESP 0x03
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#define GENERAL_READ_REGISTER_RESP 0x07
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#define GENERAL_BUS_SETTINGS_RESP_DPCD_BUS_BIT 0
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#define GENERAL_BUS_SETTINGS_RESP_HDCP_BUS_BIT 1
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#define GENERAL_BUS_SETTINGS_RESP_CAPB_OWNER_BIT 2
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#define GENERAL_BUS_SETTINGS_RESP_SUCCESS 0
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#define GENERAL_BUS_SETTINGS_RESP_LOCK_ERROR 1
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typedef struct {
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unsigned char dpcd_locked;
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unsigned char hdcp_locked;
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unsigned char capb_locked;
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unsigned char active_mode;
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} S_GENERAL_HANDLER_DATA;
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/**
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* \brief event id sent to the host
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*/
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typedef enum {
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EVENT_ID_DPTX_HPD = 0,
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EVENT_ID_HDMI_TX_HPD = 0,
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EVENT_ID_HDMI_RX_5V = 0,
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EVENT_ID_DPTX_TRAINING = 1,
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EVENT_ID_HDMI_RX_SCDC_CHANGE = 1,
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EVENT_ID_RESERVE0 = 2,
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EVENT_ID_RESERVE1 = 3,
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EVENT_ID_HDCPTX_STATUS = 4,
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EVENT_ID_HDCPRX_STATUS = 4,
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EVENT_ID_HDCPTX_IS_KM_STORED = 5,
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EVENT_ID_HDCPTX_STORE_KM = 6,
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EVENT_ID_HDCPTX_IS_RECEIVER_ID_VALID = 7,
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EVENT_ID_HDMITX_READ_REQUEST = 8,
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} EVENT_ID;
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/**
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* \brief convert bank id and register number to address and write to ptr
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*/
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#define select_reg_old(bank, reg_no, ptr) \
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{ \
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ptr = 0; \
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if ((bank == 0x22) || (bank == 0x20) || (bank == 0x0b) || (bank == 0x09) || (bank == 0x0A)) \
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ptr = (u32 *)(bank << 8 | reg_no); \
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}
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#define select_reg(bank, reg_no, ptr) \
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do { \
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ptr = (u32 *)(bank << 8 | reg_no); \
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} while (0)
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#define select_reg4(pmsb, p2, p3, plsb, ptr) \
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do { \
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ptr = (u32 *)((pmsb << 24) | (p2 << 16) | (p3 << 8) | (plsb << 0)); \
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} while (0)
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#define EVENTS_DPTX_CNT 2
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#define EVENTS_HDCPTX_CNT 4
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void general_handler_set_active_mode(void);
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void general_handler_set_standby_mode(void);
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/**
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* \brief request sending en event to the host
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* \param [in] eventId
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* \param [in] eventCode
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*/
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#endif /* GENERAL_HANDLER_H */
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