1144 lines
26 KiB
Plaintext
1144 lines
26 KiB
Plaintext
/*
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* Copyright 2012-2016 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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* Copyright 2017 NXP.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <dt-bindings/clock/imx6qdl-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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aliases {
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mxcfb0 = &mxcfb1;
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mxcfb1 = &mxcfb2;
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mxcfb2 = &mxcfb3;
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mxcfb3 = &mxcfb4;
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};
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battery: max8903@0 {
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compatible = "fsl,max8903-charger";
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pinctrl-names = "default";
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dok_input = <&gpio2 24 1>;
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uok_input = <&gpio1 27 1>;
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chg_input = <&gpio3 23 1>;
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flt_input = <&gpio5 2 1>;
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fsl,dcm_always_high;
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fsl,dc_valid;
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fsl,usb_valid;
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status = "okay";
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};
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hannstar_cabc {
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compatible = "hannstar,cabc";
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lvds0 {
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gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
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};
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lvds1 {
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gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
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};
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};
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chosen {
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stdout-path = &uart1;
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};
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memory: memory {
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reg = <0x10000000 0x40000000>;
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_usb_otg_vbus: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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regulator-name = "usb_otg_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio3 22 0>;
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enable-active-high;
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vin-supply = <&swbst_reg>;
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};
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reg_usb_h1_vbus: regulator@1 {
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compatible = "regulator-fixed";
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reg = <1>;
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regulator-name = "usb_h1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio1 29 0>;
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enable-active-high;
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vin-supply = <&swbst_reg>;
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};
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reg_audio: regulator@2 {
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compatible = "regulator-fixed";
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reg = <2>;
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regulator-name = "wm8962-supply";
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gpio = <&gpio4 10 0>;
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enable-active-high;
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};
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reg_pcie: regulator@3 {
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compatible = "regulator-fixed";
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reg = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie_reg>;
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regulator-name = "MPCIE_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio3 19 0>;
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regulator-always-on;
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enable-active-high;
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};
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reg_sensor: regulator@4 {
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compatible = "regulator-fixed";
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reg = <4>;
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regulator-name = "sensor-supply";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 31 0>;
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startup-delay-us = <500>;
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enable-active-high;
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};
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reg_hdmi: regulator@5 {
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compatible = "regulator-fixed";
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reg = <5>;
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regulator-name = "hdmi-5v-supply";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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hdmi-5v-supply = <&swbst_reg>;
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};
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reg_mipi_dsi_pwr_on: mipi_dsi_pwr_on {
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compatible = "regulator-fixed";
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regulator-name = "mipi_dsi_pwr_on";
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gpio = <&gpio6 14 0>;
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enable-active-high;
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_keys>;
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power {
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label = "Power Button";
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gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
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wakeup-source;
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linux,code = <KEY_POWER>;
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};
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volume-up {
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label = "Volume Up";
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gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
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wakeup-source;
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linux,code = <KEY_VOLUMEUP>;
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};
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volume-down {
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label = "Volume Down";
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gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
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wakeup-source;
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linux,code = <KEY_VOLUMEDOWN>;
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};
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};
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sound {
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compatible = "fsl,imx6q-sabresd-wm8962",
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"fsl,imx-audio-wm8962";
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model = "wm8962-audio";
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cpu-dai = <&ssi2>;
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audio-codec = <&codec>;
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asrc-controller = <&asrc>;
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audio-routing =
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"Headphone Jack", "HPOUTL",
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"Headphone Jack", "HPOUTR",
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"Ext Spk", "SPKOUTL",
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"Ext Spk", "SPKOUTR",
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"AMIC", "MICBIAS",
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"IN3R", "AMIC",
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"DMIC", "MICBIAS",
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"DMICDAT", "DMIC",
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"CPU-Playback", "ASRC-Playback",
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"Playback", "CPU-Playback",
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"ASRC-Capture", "CPU-Capture",
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"CPU-Capture", "Capture";
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mux-int-port = <2>;
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mux-ext-port = <3>;
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codec-master;
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hp-det-gpios = <&gpio7 8 1>;
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mic-det-gpios = <&gpio1 9 1>;
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};
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sound-hdmi {
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compatible = "fsl,imx6q-audio-hdmi",
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"fsl,imx-audio-hdmi";
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model = "imx-audio-hdmi";
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hdmi-controller = <&hdmi_audio>;
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};
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mxcfb1: fb@0 {
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compatible = "fsl,mxc_sdc_fb";
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disp_dev = "ldb";
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interface_pix_fmt = "RGB666";
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default_bpp = <16>;
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int_clk = <0>;
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late_init = <0>;
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status = "disabled";
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};
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mxcfb2: fb@1 {
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compatible = "fsl,mxc_sdc_fb";
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disp_dev = "hdmi";
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interface_pix_fmt = "RGB24";
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mode_str ="1920x1080M@60";
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default_bpp = <24>;
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int_clk = <0>;
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late_init = <0>;
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status = "disabled";
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};
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mxcfb3: fb@2 {
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compatible = "fsl,mxc_sdc_fb";
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disp_dev = "lcd";
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interface_pix_fmt = "RGB565";
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mode_str ="CLAA-WVGA";
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default_bpp = <16>;
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int_clk = <0>;
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late_init = <0>;
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status = "disabled";
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};
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mxcfb4: fb@3 {
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compatible = "fsl,mxc_sdc_fb";
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disp_dev = "ldb";
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interface_pix_fmt = "RGB666";
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default_bpp = <16>;
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int_clk = <0>;
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late_init = <0>;
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status = "disabled";
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};
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lcd@0 {
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compatible = "fsl,lcd";
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ipu_id = <0>;
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disp_id = <0>;
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default_ifmt = "RGB565";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ipu1>;
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status = "okay";
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};
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backlight {
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compatible = "pwm-backlight";
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pwms = <&pwm1 0 5000000>;
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brightness-levels = <0 4 8 16 32 64 128 255>;
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default-brightness-level = <7>;
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status = "okay";
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_leds>;
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charger-led {
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gpios = <&gpio1 2 0>;
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linux,default-trigger = "max8903-charger-charging";
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retain-state-suspended;
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};
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};
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v4l2_cap_0 {
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compatible = "fsl,imx6q-v4l2-capture";
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ipu_id = <0>;
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csi_id = <0>;
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mclk_source = <0>;
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status = "okay";
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};
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v4l2_cap_1 {
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compatible = "fsl,imx6q-v4l2-capture";
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ipu_id = <0>;
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csi_id = <1>;
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mclk_source = <0>;
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status = "okay";
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};
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v4l2_out {
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compatible = "fsl,mxc_v4l2_output";
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status = "okay";
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};
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};
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&ipu1_csi0_from_ipu1_csi0_mux {
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bus-width = <8>;
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data-shift = <12>; /* Lines 19:12 used */
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hsync-active = <1>;
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vsync-active = <1>;
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};
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&ipu1_csi0_mux_from_parallel_sensor {
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/* Downstream driver doesn't use endpoints */
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/*
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remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
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*/
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};
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&ipu1_csi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ipu1_csi0>;
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};
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&mipi_csi {
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status = "okay";
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};
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&audmux {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_audmux>;
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status = "okay";
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};
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&clks {
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assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
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<&clks IMX6QDL_CLK_LDB_DI1_SEL>;
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assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
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<&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
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};
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&ecspi1 {
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cs-gpios = <&gpio4 9 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi1>;
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status = "okay";
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flash: m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,m25p32", "jedec,spi-nor";
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spi-max-frequency = <20000000>;
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reg = <0>;
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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phy-mode = "rgmii";
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phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
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fsl,magic-packet;
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status = "okay";
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};
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&gpc {
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fsl,ldo-bypass = <1>;
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};
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&dcic1 {
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dcic_id = <0>;
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dcic_mux = "dcic-hdmi";
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status = "okay";
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};
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&dcic2 {
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dcic_id = <1>;
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dcic_mux = "dcic-lvds1";
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status = "okay";
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};
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&hdmi_audio {
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status = "okay";
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};
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&hdmi_cec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hdmi_cec>;
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status = "okay";
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};
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&hdmi_core {
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ipu_id = <0>;
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disp_id = <0>;
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status = "okay";
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};
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&hdmi_video {
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fsl,phy_reg_vlev = <0x0294>;
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fsl,phy_reg_cksymtx = <0x800d>;
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HDMI-supply = <®_hdmi>;
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status = "okay";
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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codec: wm8962@1a {
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compatible = "wlf,wm8962";
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reg = <0x1a>;
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clocks = <&clks IMX6QDL_CLK_CKO>;
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DCVDD-supply = <®_audio>;
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DBVDD-supply = <®_audio>;
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AVDD-supply = <®_audio>;
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CPVDD-supply = <®_audio>;
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MICVDD-supply = <®_audio>;
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PLLVDD-supply = <®_audio>;
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SPKVDD1-supply = <®_audio>;
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SPKVDD2-supply = <®_audio>;
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gpio-cfg = <
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0x0000 /* 0:Default */
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0x0000 /* 1:Default */
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0x0013 /* 2:FN_DMICCLK */
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0x0000 /* 3:Default */
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0x8014 /* 4:FN_DMICCDAT */
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0x0000 /* 5:Default */
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>;
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amic-mono;
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};
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mma8451@1c {
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compatible = "fsl,mma8451";
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reg = <0x1c>;
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position = <0>;
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vdd-supply = <®_sensor>;
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vddio-supply = <®_sensor>;
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interrupt-parent = <&gpio1>;
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interrupts = <18 8>;
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interrupt-route = <1>;
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};
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ov564x: ov564x@3c {
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compatible = "ovti,ov564x";
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reg = <0x3c>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ipu1_2>;
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clocks = <&clks IMX6QDL_CLK_CKO>;
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clock-names = "csi_mclk";
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DOVDD-supply = <&vgen4_reg>; /* 1.8v */
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AVDD-supply = <&vgen3_reg>; /* 2.8v, on rev C board is VGEN3,
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on rev B board is VGEN5 */
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DVDD-supply = <&vgen2_reg>; /* 1.5v*/
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pwn-gpios = <&gpio1 16 1>; /* active low: SD1_DAT0 */
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rst-gpios = <&gpio1 17 0>; /* active high: SD1_DAT1 */
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csi_id = <0>;
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mclk = <24000000>;
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mclk_source = <0>;
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};
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c2>;
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pinctrl-1 = <&pinctrl_i2c2_gpio>;
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scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
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status = "okay";
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egalax_ts@04 {
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compatible = "eeti,egalax_ts";
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reg = <0x04>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2_egalax_int>;
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interrupt-parent = <&gpio6>;
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interrupts = <8 2>;
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wakeup-gpios = <&gpio6 8 0>;
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};
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max11801@48 {
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compatible = "maxim,max11801";
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reg = <0x48>;
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interrupt-parent = <&gpio3>;
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interrupts = <26 2>;
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work-mode = <1>;/*DCM mode*/
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};
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pmic: pfuze100@08 {
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compatible = "fsl,pfuze100";
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reg = <0x08>;
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regulators {
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sw1a_reg: sw1ab {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1875000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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sw1c_reg: sw1c {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1875000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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sw2_reg: sw2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <6250>;
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};
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sw3a_reg: sw3a {
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regulator-min-microvolt = <400000>;
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regulator-max-microvolt = <1975000>;
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regulator-boot-on;
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regulator-always-on;
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};
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sw3b_reg: sw3b {
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regulator-min-microvolt = <400000>;
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regulator-max-microvolt = <1975000>;
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regulator-boot-on;
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regulator-always-on;
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};
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sw4_reg: sw4 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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swbst_reg: swbst {
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5150000>;
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};
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snvs_reg: vsnvs {
|
|
regulator-min-microvolt = <1000000>;
|
|
regulator-max-microvolt = <3000000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
vref_reg: vrefddr {
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
vgen1_reg: vgen1 {
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <1550000>;
|
|
};
|
|
|
|
vgen2_reg: vgen2 {
|
|
regulator-min-microvolt = <800000>;
|
|
regulator-max-microvolt = <1550000>;
|
|
};
|
|
|
|
vgen3_reg: vgen3 {
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
};
|
|
|
|
vgen4_reg: vgen4 {
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
vgen5_reg: vgen5 {
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
|
|
vgen6_reg: vgen6 {
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-always-on;
|
|
};
|
|
};
|
|
};
|
|
|
|
hdmi_edid: edid@50 {
|
|
compatible = "fsl,imx6-hdmi-i2c";
|
|
reg = <0x50>;
|
|
};
|
|
|
|
ov564x_mipi: ov564x_mipi@3c { /* i2c2 driver */
|
|
compatible = "ovti,ov564x_mipi";
|
|
reg = <0x3c>;
|
|
clocks = <&clks 201>;
|
|
clock-names = "csi_mclk";
|
|
DOVDD-supply = <&vgen4_reg>; /* 1.8v */
|
|
AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3
|
|
rev B board is VGEN5 */
|
|
DVDD-supply = <&vgen2_reg>; /* 1.5v*/
|
|
pwn-gpios = <&gpio1 19 1>; /* active low: SD1_CLK */
|
|
rst-gpios = <&gpio1 20 0>; /* active high: SD1_DAT2 */
|
|
csi_id = <1>;
|
|
mclk = <24000000>;
|
|
mclk_source = <0>;
|
|
};
|
|
};
|
|
|
|
&i2c3 {
|
|
clock-frequency = <100000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c3>;
|
|
status = "okay";
|
|
|
|
egalax_ts@04 {
|
|
compatible = "eeti,egalax_ts";
|
|
reg = <0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c3_egalax_int>;
|
|
interrupt-parent = <&gpio6>;
|
|
interrupts = <7 2>;
|
|
wakeup-gpios = <&gpio6 7 0>;
|
|
};
|
|
|
|
isl29023@44 {
|
|
compatible = "fsl,isl29023";
|
|
reg = <0x44>;
|
|
rext = <499>;
|
|
vdd-supply = <®_sensor>;
|
|
interrupt-parent = <&gpio3>;
|
|
interrupts = <9 2>;
|
|
};
|
|
|
|
mag3110@0e {
|
|
compatible = "fsl,mag3110";
|
|
reg = <0x0e>;
|
|
position = <2>;
|
|
vdd-supply = <®_sensor>;
|
|
vddio-supply = <®_sensor>;
|
|
interrupt-parent = <&gpio3>;
|
|
interrupts = <16 1>;
|
|
};
|
|
};
|
|
|
|
&iomuxc {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_hog>;
|
|
|
|
imx6qdl-sabresd {
|
|
pinctrl_hog: hoggrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
|
|
MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
|
|
MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
|
|
MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
|
|
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
|
|
MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
|
|
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
|
|
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
|
|
MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000
|
|
MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000
|
|
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
|
|
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000
|
|
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
|
|
MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000
|
|
MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x80000000
|
|
MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000
|
|
MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000
|
|
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000
|
|
MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
|
|
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
|
|
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
|
|
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
|
|
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000
|
|
>;
|
|
};
|
|
|
|
pinctrl_audmux: audmuxgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
|
|
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
|
|
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
|
|
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_ecspi1: ecspi1grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
|
|
MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
|
|
MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
|
|
MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2_egalax_int: egalax_i2c2_intgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c3_egalax_int: egalax_i2c3_intgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
|
|
>;
|
|
};
|
|
|
|
pinctrl_enet: enetgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
|
|
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
|
|
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
|
|
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
|
|
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
|
|
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
|
|
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
|
|
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
|
|
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
|
|
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
|
|
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
|
|
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
|
|
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
|
|
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
|
|
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
|
|
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
|
|
>;
|
|
};
|
|
|
|
pinctrl_enet_irq: enetirqgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_gpio_keys: gpio_keysgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0
|
|
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
|
|
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_hdmi_cec: hdmicecgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x108b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_hdmi_hdcp: hdmihdcpgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
|
|
MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c1: i2c1grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
|
|
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2: i2c2grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
|
|
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2_gpio: i2c2_gpio_grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0
|
|
MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c3: i2c3grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
|
|
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_ipu1: ipu1grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
|
|
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
|
|
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
|
|
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
|
|
MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
|
|
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
|
|
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
|
|
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
|
|
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
|
|
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
|
|
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
|
|
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
|
|
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
|
|
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
|
|
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
|
|
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
|
|
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
|
|
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
|
|
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
|
|
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
|
|
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
|
|
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
|
|
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
|
|
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
|
|
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
|
|
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
|
|
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
|
|
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
|
|
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
|
|
>;
|
|
};
|
|
|
|
pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
|
|
fsl,pins = <
|
|
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
|
|
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
|
|
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
|
|
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
|
|
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
|
|
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
|
|
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
|
|
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
|
|
MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
|
|
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
|
|
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
|
|
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
|
|
MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000
|
|
MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000
|
|
>;
|
|
};
|
|
|
|
pinctrl_ipu1_csi0: ipu1csi0grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
|
|
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
|
|
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
|
|
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
|
|
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
|
|
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
|
|
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
|
|
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
|
|
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
|
|
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
|
|
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_ov5640: ov5640grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x1b0b0
|
|
MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x1b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_ov5642: ov5642grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
|
|
MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_pcie: pciegrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_pcie_reg: pciereggrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_pwm1: pwm1grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
|
|
MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart5_1: uart5grp-1 {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
|
|
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
|
|
MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x1b0b1
|
|
MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart5dte_1: uart5dtegrp-1 {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1
|
|
MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1
|
|
MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x1b0b1
|
|
MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x1b0b1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usbotg: usbotggrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
|
|
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
|
|
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
|
|
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
|
|
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
|
|
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
|
|
MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
|
|
MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
|
|
MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
|
|
MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3: usdhc3grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
|
|
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
|
|
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
|
|
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
|
|
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
|
|
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
|
|
MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
|
|
MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
|
|
MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
|
|
MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc4: usdhc4grp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
|
|
MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
|
|
MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
|
|
MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
|
|
MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
|
|
MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
|
|
MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
|
|
MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
|
|
MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
|
|
MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
|
|
>;
|
|
};
|
|
|
|
pinctrl_wdog: wdoggrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_GPIO_1__WDOG2_B 0x80000000
|
|
>;
|
|
};
|
|
};
|
|
|
|
gpio_leds {
|
|
pinctrl_gpio_leds: gpioledsgrp {
|
|
fsl,pins = <
|
|
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
|
|
>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&ldb {
|
|
status = "okay";
|
|
|
|
lvds-channel@0 {
|
|
fsl,data-mapping = "spwg";
|
|
fsl,data-width = <18>;
|
|
status = "okay";
|
|
|
|
display-timings {
|
|
native-mode = <&timing0>;
|
|
timing0: hsd100pxn1 {
|
|
clock-frequency = <65000000>;
|
|
hactive = <1024>;
|
|
vactive = <768>;
|
|
hback-porch = <220>;
|
|
hfront-porch = <40>;
|
|
vback-porch = <21>;
|
|
vfront-porch = <7>;
|
|
hsync-len = <60>;
|
|
vsync-len = <10>;
|
|
};
|
|
};
|
|
};
|
|
|
|
lvds-channel@1 {
|
|
fsl,data-mapping = "spwg";
|
|
fsl,data-width = <18>;
|
|
primary;
|
|
status = "okay";
|
|
|
|
display-timings {
|
|
native-mode = <&timing1>;
|
|
timing1: hsd100pxn1 {
|
|
clock-frequency = <65000000>;
|
|
hactive = <1024>;
|
|
vactive = <768>;
|
|
hback-porch = <220>;
|
|
hfront-porch = <40>;
|
|
vback-porch = <21>;
|
|
vfront-porch = <7>;
|
|
hsync-len = <60>;
|
|
vsync-len = <10>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&mipi_csi {
|
|
status = "okay";
|
|
ipu_id = <0>;
|
|
csi_id = <1>;
|
|
v_channel = <0>;
|
|
lanes = <2>;
|
|
};
|
|
|
|
&mipi_dsi {
|
|
dev_id = <0>;
|
|
disp_id = <1>;
|
|
lcd_panel = "TRULY-WVGA";
|
|
disp-power-on-supply = <®_mipi_dsi_pwr_on>;
|
|
reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
|
|
reset-delay-us = <50>;
|
|
status = "okay";
|
|
};
|
|
|
|
&pcie {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pcie>;
|
|
reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
|
|
status = "okay";
|
|
};
|
|
|
|
&pwm1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pwm1>;
|
|
status = "okay";
|
|
};
|
|
|
|
®_arm {
|
|
vin-supply = <&sw1a_reg>;
|
|
};
|
|
|
|
®_pu {
|
|
vin-supply = <&sw1c_reg>;
|
|
};
|
|
|
|
®_soc {
|
|
vin-supply = <&sw1c_reg>;
|
|
};
|
|
|
|
&snvs_poweroff {
|
|
status = "okay";
|
|
};
|
|
|
|
&ssi2 {
|
|
assigned-clocks = <&clks IMX6QDL_CLK_PLL4>,
|
|
<&clks IMX6QDL_PLL4_BYPASS>,
|
|
<&clks IMX6QDL_CLK_SSI2_SEL>;
|
|
assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>,
|
|
<&clks IMX6QDL_CLK_PLL4>,
|
|
<&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
|
|
assigned-clock-rates = <737280000>, <0>, <0>;
|
|
status = "okay";
|
|
};
|
|
|
|
&uart1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart1>;
|
|
status = "okay";
|
|
};
|
|
|
|
&usbh1 {
|
|
vbus-supply = <®_usb_h1_vbus>;
|
|
status = "okay";
|
|
};
|
|
|
|
&usbotg {
|
|
vbus-supply = <®_usb_otg_vbus>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usbotg>;
|
|
disable-over-current;
|
|
srp-disable;
|
|
hnp-disable;
|
|
adp-disable;
|
|
status = "okay";
|
|
};
|
|
|
|
&usbphy1 {
|
|
fsl,tx-d-cal = <106>;
|
|
};
|
|
|
|
&usbphy2 {
|
|
fsl,tx-d-cal = <106>;
|
|
};
|
|
|
|
&usdhc2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usdhc2>;
|
|
bus-width = <8>;
|
|
cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
|
|
wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
|
|
no-1-8-v;
|
|
keep-power-in-suspend;
|
|
enable-sdio-wakeup;
|
|
status = "okay";
|
|
};
|
|
|
|
&usdhc3 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usdhc3>;
|
|
bus-width = <8>;
|
|
cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
|
|
wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
|
|
no-1-8-v;
|
|
keep-power-in-suspend;
|
|
enable-sdio-wakeup;
|
|
status = "okay";
|
|
};
|
|
|
|
&usdhc4 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usdhc4>;
|
|
bus-width = <8>;
|
|
non-removable;
|
|
no-1-8-v;
|
|
keep-power-in-suspend;
|
|
status = "okay";
|
|
};
|
|
|
|
&wdog1 {
|
|
status = "disabled";
|
|
};
|
|
|
|
&wdog2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_wdog>;
|
|
fsl,ext-reset-output;
|
|
status = "okay";
|
|
};
|