![Tomi Valkeinen](/assets/img/avatar_default.png)
When setting the rate of a clock, by default the clock framework will change the parent of the clock to the most suitable one in __clk_mux_determine_rate() (most suitable by looking at the clock rate). This is a rather dangerous default, and causes problems on AM43x when using display and ethernet. There are multiple ways to select the clock muxes on AM43x, and some of those clock paths have the same source clocks for display and ethernet. When changing the clock rate for the display subsystem, the clock framework decides to change the display mux from the dedicated display PLL to a shared PLL which is used by the ethernet, and then changes the rate of the shared PLL, breaking the ethernet. As I don't think there ever is a case where we want the clock framework to automatically change the parent clock of a clock mux, this patch sets the CLK_SET_RATE_NO_REPARENT for all ti,mux-clocks. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by: Paul Walmsley <paul@pwsan.com> Tested-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
247 lines
5.7 KiB
C
247 lines
5.7 KiB
C
/*
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* TI Multiplexer Clock
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*
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* Tero Kristo <t-kristo@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/clk/ti.h>
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#undef pr_fmt
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
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static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
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{
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struct clk_mux *mux = to_clk_mux(hw);
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int num_parents = __clk_get_num_parents(hw->clk);
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u32 val;
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/*
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* FIXME need a mux-specific flag to determine if val is bitwise or
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* numeric. e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges
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* from 0x1 to 0x7 (index starts at one)
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* OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
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* val = 0x4 really means "bit 2, index starts at bit 0"
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*/
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val = ti_clk_ll_ops->clk_readl(mux->reg) >> mux->shift;
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val &= mux->mask;
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if (mux->table) {
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int i;
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for (i = 0; i < num_parents; i++)
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if (mux->table[i] == val)
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return i;
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return -EINVAL;
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}
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if (val && (mux->flags & CLK_MUX_INDEX_BIT))
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val = ffs(val) - 1;
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if (val && (mux->flags & CLK_MUX_INDEX_ONE))
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val--;
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if (val >= num_parents)
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return -EINVAL;
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return val;
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}
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static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_mux *mux = to_clk_mux(hw);
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u32 val;
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unsigned long flags = 0;
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if (mux->table) {
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index = mux->table[index];
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} else {
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if (mux->flags & CLK_MUX_INDEX_BIT)
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index = (1 << ffs(index));
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if (mux->flags & CLK_MUX_INDEX_ONE)
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index++;
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}
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if (mux->lock)
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spin_lock_irqsave(mux->lock, flags);
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if (mux->flags & CLK_MUX_HIWORD_MASK) {
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val = mux->mask << (mux->shift + 16);
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} else {
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val = ti_clk_ll_ops->clk_readl(mux->reg);
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val &= ~(mux->mask << mux->shift);
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}
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val |= index << mux->shift;
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ti_clk_ll_ops->clk_writel(val, mux->reg);
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if (mux->lock)
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spin_unlock_irqrestore(mux->lock, flags);
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return 0;
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}
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const struct clk_ops ti_clk_mux_ops = {
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.get_parent = ti_clk_mux_get_parent,
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.set_parent = ti_clk_mux_set_parent,
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.determine_rate = __clk_mux_determine_rate,
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};
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static struct clk *_register_mux(struct device *dev, const char *name,
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const char **parent_names, u8 num_parents,
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unsigned long flags, void __iomem *reg,
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u8 shift, u32 mask, u8 clk_mux_flags,
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u32 *table, spinlock_t *lock)
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{
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struct clk_mux *mux;
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struct clk *clk;
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struct clk_init_data init;
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/* allocate the mux */
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mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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if (!mux) {
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pr_err("%s: could not allocate mux clk\n", __func__);
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return ERR_PTR(-ENOMEM);
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}
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init.name = name;
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init.ops = &ti_clk_mux_ops;
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init.flags = flags | CLK_IS_BASIC;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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/* struct clk_mux assignments */
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mux->reg = reg;
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mux->shift = shift;
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mux->mask = mask;
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mux->flags = clk_mux_flags;
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mux->lock = lock;
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mux->table = table;
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mux->hw.init = &init;
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clk = clk_register(dev, &mux->hw);
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if (IS_ERR(clk))
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kfree(mux);
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return clk;
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}
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/**
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* of_mux_clk_setup - Setup function for simple mux rate clock
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* @node: DT node for the clock
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*
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* Sets up a basic clock multiplexer.
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*/
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static void of_mux_clk_setup(struct device_node *node)
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{
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struct clk *clk;
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void __iomem *reg;
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int num_parents;
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const char **parent_names;
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int i;
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u8 clk_mux_flags = 0;
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u32 mask = 0;
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u32 shift = 0;
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u32 flags = CLK_SET_RATE_NO_REPARENT;
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num_parents = of_clk_get_parent_count(node);
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if (num_parents < 2) {
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pr_err("mux-clock %s must have parents\n", node->name);
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return;
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}
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parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
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if (!parent_names)
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goto cleanup;
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for (i = 0; i < num_parents; i++)
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parent_names[i] = of_clk_get_parent_name(node, i);
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reg = ti_clk_get_reg_addr(node, 0);
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if (!reg)
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goto cleanup;
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of_property_read_u32(node, "ti,bit-shift", &shift);
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if (of_property_read_bool(node, "ti,index-starts-at-one"))
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clk_mux_flags |= CLK_MUX_INDEX_ONE;
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if (of_property_read_bool(node, "ti,set-rate-parent"))
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flags |= CLK_SET_RATE_PARENT;
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/* Generate bit-mask based on parent info */
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mask = num_parents;
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if (!(clk_mux_flags & CLK_MUX_INDEX_ONE))
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mask--;
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mask = (1 << fls(mask)) - 1;
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clk = _register_mux(NULL, node->name, parent_names, num_parents, flags,
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reg, shift, mask, clk_mux_flags, NULL, NULL);
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if (!IS_ERR(clk))
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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cleanup:
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kfree(parent_names);
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}
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CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup);
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static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
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{
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struct clk_mux *mux;
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int num_parents;
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u32 val;
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mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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if (!mux)
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return;
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mux->reg = ti_clk_get_reg_addr(node, 0);
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if (!mux->reg)
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goto cleanup;
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if (!of_property_read_u32(node, "ti,bit-shift", &val))
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mux->shift = val;
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if (of_property_read_bool(node, "ti,index-starts-at-one"))
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mux->flags |= CLK_MUX_INDEX_ONE;
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num_parents = of_clk_get_parent_count(node);
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if (num_parents < 2) {
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pr_err("%s must have parents\n", node->name);
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goto cleanup;
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}
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mux->mask = num_parents - 1;
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mux->mask = (1 << fls(mux->mask)) - 1;
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if (!ti_clk_add_component(node, &mux->hw, CLK_COMPONENT_TYPE_MUX))
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return;
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cleanup:
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kfree(mux);
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}
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CLK_OF_DECLARE(ti_composite_mux_clk_setup, "ti,composite-mux-clock",
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of_ti_composite_mux_clk_setup);
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