79 lines
1.8 KiB
C
79 lines
1.8 KiB
C
/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include "mx8_mu.h"
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/*!
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* This function enables specific RX full interrupt.
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*/
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void MU_EnableRxFullInt(void __iomem *base, uint32_t index)
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{
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uint32_t reg = readl_relaxed(base + MU_ACR_OFFSET1);
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reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1);
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reg |= ~MU_CR_RIE0_MASK1 >> index;
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writel_relaxed(reg, base + MU_ACR_OFFSET1);
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}
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/*!
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* This function enables specific general purpose interrupt.
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*/
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void MU_EnableGeneralInt(void __iomem *base, uint32_t index)
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{
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uint32_t reg = readl_relaxed(base + MU_ACR_OFFSET1);
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reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1);
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reg |= MU_CR_GIE0_MASK1 >> index;
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writel_relaxed(reg, base + MU_ACR_OFFSET1);
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}
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/*
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* Wait and send message to the other core.
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*/
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void MU_SendMessage(void __iomem *base, uint32_t regIndex, uint32_t msg)
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{
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uint32_t mask = MU_SR_TE0_MASK1 >> regIndex;
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/* Wait TX register to be empty. */
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while (!(readl_relaxed(base + MU_ASR_OFFSET1) & mask))
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;
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writel_relaxed(msg, base + MU_ATR0_OFFSET1 + (regIndex * 4));
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}
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/*
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* Wait to receive message from the other core.
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*/
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void MU_ReceiveMsg(void __iomem *base, uint32_t regIndex, uint32_t *msg)
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{
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uint32_t mask = MU_SR_RF0_MASK1 >> regIndex;
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/* Wait RX register to be full. */
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while (!(readl_relaxed(base + MU_ASR_OFFSET1) & mask))
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;
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*msg = readl_relaxed(base + MU_ARR0_OFFSET1 + (regIndex * 4));
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}
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void MU_Init(void __iomem *base)
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{
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uint32_t reg;
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reg = readl_relaxed(base + MU_ACR_OFFSET1);
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/* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */
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reg &= ~(MU_CR_GIEn_MASK1 | MU_CR_RIEn_MASK1 | MU_CR_TIEn_MASK1
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| MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1 | MU_CR_Fn_MASK1);
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writel_relaxed(reg, base + MU_ACR_OFFSET1);
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}
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/**@}*/
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