159 lines
4.6 KiB
C
159 lines
4.6 KiB
C
/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*!
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* Header file containing the public API for the System Controller (SC)
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* Interrupt (IRQ) function.
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*
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* @addtogroup IRQ_SVC (SVC) Interrupt Service
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*
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* Module for the Interrupt (IRQ) service.
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*
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* @{
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*/
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#ifndef _SC_IRQ_API_H
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#define _SC_IRQ_API_H
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/* Includes */
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#include <soc/imx8/sc/types.h>
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/* Defines */
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#define SC_IRQ_NUM_GROUP 4 /* Number of groups */
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/*!
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* @name Defines for sc_irq_group_t
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*/
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/*@{*/
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#define SC_IRQ_GROUP_TEMP 0 /* Temp interrupts */
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#define SC_IRQ_GROUP_WDOG 1 /* Watchdog interrupts */
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#define SC_IRQ_GROUP_RTC 2 /* RTC interrupts */
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#define SC_IRQ_GROUP_WAKE 3 /* Wakeup interrupts */
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/*@}*/
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/*!
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* @name Defines for sc_irq_temp_t
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*/
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/*@{*/
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#define SC_IRQ_TEMP_HIGH (1 << 0) /* Temp alarm interrupt */
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#define SC_IRQ_TEMP_CPU0_HIGH (1 << 1) /* CPU0 temp alarm interrupt */
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#define SC_IRQ_TEMP_CPU1_HIGH (1 << 2) /* CPU1 temp alarm interrupt */
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#define SC_IRQ_TEMP_GPU0_HIGH (1 << 3) /* GPU0 temp alarm interrupt */
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#define SC_IRQ_TEMP_GPU1_HIGH (1 << 4) /* GPU1 temp alarm interrupt */
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#define SC_IRQ_TEMP_DRC0_HIGH (1 << 5) /* DRC0 temp alarm interrupt */
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#define SC_IRQ_TEMP_DRC1_HIGH (1 << 6) /* DRC1 temp alarm interrupt */
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#define SC_IRQ_TEMP_VPU_HIGH (1 << 7) /* DRC1 temp alarm interrupt */
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#define SC_IRQ_TEMP_PMIC0_HIGH (1 << 8) /* PMIC0 temp alarm interrupt */
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#define SC_IRQ_TEMP_PMIC1_HIGH (1 << 9) /* PMIC1 temp alarm interrupt */
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#define SC_IRQ_TEMP_LOW (1 << 10) /* Temp alarm interrupt */
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#define SC_IRQ_TEMP_CPU0_LOW (1 << 11) /* CPU0 temp alarm interrupt */
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#define SC_IRQ_TEMP_CPU1_LOW (1 << 12) /* CPU1 temp alarm interrupt */
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#define SC_IRQ_TEMP_GPU0_LOW (1 << 13) /* GPU0 temp alarm interrupt */
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#define SC_IRQ_TEMP_GPU1_LOW (1 << 14) /* GPU1 temp alarm interrupt */
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#define SC_IRQ_TEMP_DRC0_LOW (1 << 15) /* DRC0 temp alarm interrupt */
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#define SC_IRQ_TEMP_DRC1_LOW (1 << 16) /* DRC1 temp alarm interrupt */
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#define SC_IRQ_TEMP_VPU_LOW (1 << 17) /* DRC1 temp alarm interrupt */
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#define SC_IRQ_TEMP_PMIC0_LOW (1 << 18) /* PMIC0 temp alarm interrupt */
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#define SC_IRQ_TEMP_PMIC1_LOW (1 << 19) /* PMIC1 temp alarm interrupt */
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#define SC_IRQ_TEMP_PMIC2_HIGH (1 << 20) /* PMIC2 temp alarm interrupt */
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#define SC_IRQ_TEMP_PMIC2_LOW (1 << 21) /* PMIC2 temp alarm interrupt */
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/*@}*/
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/*!
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* @name Defines for sc_irq_wdog_t
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*/
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/*@{*/
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#define SC_IRQ_WDOG (1 << 0) /* Watchdog interrupt */
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/*@}*/
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/*!
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* @name Defines for sc_irq_rtc_t
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*/
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/*@{*/
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#define SC_IRQ_RTC (1 << 0) /* RTC interrupt */
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/*@}*/
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/*!
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* @name Defines for sc_irq_wake_t
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*/
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/*@{*/
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#define SC_IRQ_BUTTON (1 << 0) /* Button interrupt */
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/*@}*/
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/* Types */
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/*!
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* This type is used to declare an interrupt group.
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*/
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typedef uint8_t sc_irq_group_t;
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/*!
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* This type is used to declare a bit mask of temp interrupts.
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*/
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typedef uint8_t sc_irq_temp_t;
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/*!
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* This type is used to declare a bit mask of watchdog interrupts.
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*/
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typedef uint8_t sc_irq_wdog_t;
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/*!
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* This type is used to declare a bit mask of RTC interrupts.
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*/
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typedef uint8_t sc_irq_rtc_t;
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/*!
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* This type is used to declare a bit mask of wakeup interrupts.
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*/
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typedef uint8_t sc_irq_wake_t;
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/* Functions */
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/*!
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* This function enables/disables interrupts. If pending interrupts
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* are unmasked, an interrupt will be triggered.
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*
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* @param[in] ipc IPC handle
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* @param[in] resource MU channel
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* @param[in] group group the interrupts are in
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* @param[in] mask mask of interrupts to affect
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* @param[in] enable state to change interrupts to
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*
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* @return Returns an error code (SC_ERR_NONE = success).
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*
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* Return errors:
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* - SC_PARM if group invalid
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*/
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sc_err_t sc_irq_enable(sc_ipc_t ipc, sc_rsrc_t resource,
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sc_irq_group_t group, uint32_t mask, bool enable);
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/*!
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* This function returns the current interrupt status (regardless if
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* masked). Automatically clears pending interrupts.
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*
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* @param[in] ipc IPC handle
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* @param[in] resource MU channel
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* @param[in] group groups the interrupts are in
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* @param[in] status status of interrupts
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*
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* @return Returns an error code (SC_ERR_NONE = success).
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*
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* Return errors:
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* - SC_PARM if group invalid
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*
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* The returned \a status may show interrupts pending that are
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* currently masked.
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*/
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sc_err_t sc_irq_status(sc_ipc_t ipc, sc_rsrc_t resource,
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sc_irq_group_t group, uint32_t *status);
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#endif /* _SC_IRQ_API_H */
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/**@}*/
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