![Mika Westerberg](/assets/img/avatar_default.png)
The PXA SPI driver uses PXA platform specific private DMA implementation which does not work on non-PXA platforms. In order to use this driver on other platforms we break out the private DMA implementation into a separate file that gets compiled only when CONFIG_SPI_PXA2XX_PXADMA is set. The DMA functions are stubbed out if there is no DMA implementation selected (i.e we are building on non-PXA platform). While we are there we can kill the dummy DMA bits in pxa2xx_spi.h as they are not needed anymore for CE4100. Once this is done we can add the generic DMA engine support to the driver that allows usage of any DMA controller that implements DMA engine API. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Lu Cao <lucao@marvell.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
1103 lines
28 KiB
C
1103 lines
28 KiB
C
/*
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* Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/ioport.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/spi/pxa2xx_spi.h>
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#include <linux/spi/spi.h>
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#include <linux/workqueue.h>
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#include <linux/delay.h>
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/delay.h>
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#include "spi-pxa2xx.h"
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MODULE_AUTHOR("Stephen Street");
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MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:pxa2xx-spi");
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#define MAX_BUSES 3
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#define TIMOUT_DFLT 1000
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/*
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* for testing SSCR1 changes that require SSP restart, basically
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* everything except the service and interrupt enables, the pxa270 developer
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* manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
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* list, but the PXA255 dev man says all bits without really meaning the
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* service and interrupt enables
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*/
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#define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
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| SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
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| SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
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| SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
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| SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
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| SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
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static void cs_assert(struct driver_data *drv_data)
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{
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struct chip_data *chip = drv_data->cur_chip;
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if (drv_data->ssp_type == CE4100_SSP) {
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write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr);
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return;
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}
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if (chip->cs_control) {
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chip->cs_control(PXA2XX_CS_ASSERT);
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return;
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}
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if (gpio_is_valid(chip->gpio_cs))
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gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
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}
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static void cs_deassert(struct driver_data *drv_data)
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{
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struct chip_data *chip = drv_data->cur_chip;
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if (drv_data->ssp_type == CE4100_SSP)
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return;
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if (chip->cs_control) {
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chip->cs_control(PXA2XX_CS_DEASSERT);
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return;
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}
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if (gpio_is_valid(chip->gpio_cs))
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gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
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}
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int pxa2xx_spi_flush(struct driver_data *drv_data)
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{
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unsigned long limit = loops_per_jiffy << 1;
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void __iomem *reg = drv_data->ioaddr;
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do {
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while (read_SSSR(reg) & SSSR_RNE) {
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read_SSDR(reg);
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}
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} while ((read_SSSR(reg) & SSSR_BSY) && --limit);
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write_SSSR_CS(drv_data, SSSR_ROR);
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return limit;
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}
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static int null_writer(struct driver_data *drv_data)
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{
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void __iomem *reg = drv_data->ioaddr;
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u8 n_bytes = drv_data->n_bytes;
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if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
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|| (drv_data->tx == drv_data->tx_end))
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return 0;
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write_SSDR(0, reg);
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drv_data->tx += n_bytes;
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return 1;
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}
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static int null_reader(struct driver_data *drv_data)
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{
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void __iomem *reg = drv_data->ioaddr;
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u8 n_bytes = drv_data->n_bytes;
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while ((read_SSSR(reg) & SSSR_RNE)
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&& (drv_data->rx < drv_data->rx_end)) {
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read_SSDR(reg);
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drv_data->rx += n_bytes;
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}
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return drv_data->rx == drv_data->rx_end;
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}
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static int u8_writer(struct driver_data *drv_data)
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{
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void __iomem *reg = drv_data->ioaddr;
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if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
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|| (drv_data->tx == drv_data->tx_end))
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return 0;
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write_SSDR(*(u8 *)(drv_data->tx), reg);
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++drv_data->tx;
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return 1;
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}
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static int u8_reader(struct driver_data *drv_data)
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{
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void __iomem *reg = drv_data->ioaddr;
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while ((read_SSSR(reg) & SSSR_RNE)
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&& (drv_data->rx < drv_data->rx_end)) {
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*(u8 *)(drv_data->rx) = read_SSDR(reg);
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++drv_data->rx;
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}
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return drv_data->rx == drv_data->rx_end;
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}
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static int u16_writer(struct driver_data *drv_data)
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{
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void __iomem *reg = drv_data->ioaddr;
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if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
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|| (drv_data->tx == drv_data->tx_end))
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return 0;
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write_SSDR(*(u16 *)(drv_data->tx), reg);
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drv_data->tx += 2;
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return 1;
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}
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static int u16_reader(struct driver_data *drv_data)
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{
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void __iomem *reg = drv_data->ioaddr;
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while ((read_SSSR(reg) & SSSR_RNE)
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&& (drv_data->rx < drv_data->rx_end)) {
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*(u16 *)(drv_data->rx) = read_SSDR(reg);
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drv_data->rx += 2;
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}
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return drv_data->rx == drv_data->rx_end;
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}
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static int u32_writer(struct driver_data *drv_data)
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{
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void __iomem *reg = drv_data->ioaddr;
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if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
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|| (drv_data->tx == drv_data->tx_end))
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return 0;
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write_SSDR(*(u32 *)(drv_data->tx), reg);
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drv_data->tx += 4;
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return 1;
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}
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static int u32_reader(struct driver_data *drv_data)
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{
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void __iomem *reg = drv_data->ioaddr;
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while ((read_SSSR(reg) & SSSR_RNE)
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&& (drv_data->rx < drv_data->rx_end)) {
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*(u32 *)(drv_data->rx) = read_SSDR(reg);
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drv_data->rx += 4;
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}
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return drv_data->rx == drv_data->rx_end;
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}
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void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
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{
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struct spi_message *msg = drv_data->cur_msg;
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struct spi_transfer *trans = drv_data->cur_transfer;
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/* Move to next transfer */
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if (trans->transfer_list.next != &msg->transfers) {
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drv_data->cur_transfer =
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list_entry(trans->transfer_list.next,
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struct spi_transfer,
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transfer_list);
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return RUNNING_STATE;
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} else
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return DONE_STATE;
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}
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/* caller already set message->status; dma and pio irqs are blocked */
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static void giveback(struct driver_data *drv_data)
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{
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struct spi_transfer* last_transfer;
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struct spi_message *msg;
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msg = drv_data->cur_msg;
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drv_data->cur_msg = NULL;
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drv_data->cur_transfer = NULL;
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last_transfer = list_entry(msg->transfers.prev,
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struct spi_transfer,
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transfer_list);
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/* Delay if requested before any change in chip select */
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if (last_transfer->delay_usecs)
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udelay(last_transfer->delay_usecs);
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/* Drop chip select UNLESS cs_change is true or we are returning
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* a message with an error, or next message is for another chip
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*/
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if (!last_transfer->cs_change)
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cs_deassert(drv_data);
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else {
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struct spi_message *next_msg;
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/* Holding of cs was hinted, but we need to make sure
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* the next message is for the same chip. Don't waste
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* time with the following tests unless this was hinted.
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*
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* We cannot postpone this until pump_messages, because
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* after calling msg->complete (below) the driver that
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* sent the current message could be unloaded, which
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* could invalidate the cs_control() callback...
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*/
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/* get a pointer to the next message, if any */
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next_msg = spi_get_next_queued_message(drv_data->master);
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/* see if the next and current messages point
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* to the same chip
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*/
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if (next_msg && next_msg->spi != msg->spi)
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next_msg = NULL;
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if (!next_msg || msg->state == ERROR_STATE)
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cs_deassert(drv_data);
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}
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spi_finalize_current_message(drv_data->master);
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drv_data->cur_chip = NULL;
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}
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static void reset_sccr1(struct driver_data *drv_data)
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{
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void __iomem *reg = drv_data->ioaddr;
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struct chip_data *chip = drv_data->cur_chip;
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u32 sccr1_reg;
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sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1;
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sccr1_reg &= ~SSCR1_RFT;
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sccr1_reg |= chip->threshold;
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write_SSCR1(sccr1_reg, reg);
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}
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static void int_error_stop(struct driver_data *drv_data, const char* msg)
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{
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void __iomem *reg = drv_data->ioaddr;
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/* Stop and reset SSP */
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write_SSSR_CS(drv_data, drv_data->clear_sr);
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reset_sccr1(drv_data);
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if (!pxa25x_ssp_comp(drv_data))
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write_SSTO(0, reg);
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pxa2xx_spi_flush(drv_data);
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write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
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dev_err(&drv_data->pdev->dev, "%s\n", msg);
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drv_data->cur_msg->state = ERROR_STATE;
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tasklet_schedule(&drv_data->pump_transfers);
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}
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static void int_transfer_complete(struct driver_data *drv_data)
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{
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void __iomem *reg = drv_data->ioaddr;
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/* Stop SSP */
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write_SSSR_CS(drv_data, drv_data->clear_sr);
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reset_sccr1(drv_data);
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if (!pxa25x_ssp_comp(drv_data))
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write_SSTO(0, reg);
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/* Update total byte transferred return count actual bytes read */
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drv_data->cur_msg->actual_length += drv_data->len -
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(drv_data->rx_end - drv_data->rx);
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/* Transfer delays and chip select release are
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* handled in pump_transfers or giveback
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*/
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/* Move to next transfer */
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drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
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/* Schedule transfer tasklet */
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tasklet_schedule(&drv_data->pump_transfers);
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}
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static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
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{
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void __iomem *reg = drv_data->ioaddr;
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u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
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drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
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u32 irq_status = read_SSSR(reg) & irq_mask;
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if (irq_status & SSSR_ROR) {
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int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
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return IRQ_HANDLED;
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}
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if (irq_status & SSSR_TINT) {
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write_SSSR(SSSR_TINT, reg);
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if (drv_data->read(drv_data)) {
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int_transfer_complete(drv_data);
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return IRQ_HANDLED;
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}
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}
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/* Drain rx fifo, Fill tx fifo and prevent overruns */
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do {
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if (drv_data->read(drv_data)) {
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int_transfer_complete(drv_data);
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return IRQ_HANDLED;
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}
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} while (drv_data->write(drv_data));
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if (drv_data->read(drv_data)) {
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int_transfer_complete(drv_data);
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return IRQ_HANDLED;
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}
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if (drv_data->tx == drv_data->tx_end) {
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u32 bytes_left;
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u32 sccr1_reg;
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sccr1_reg = read_SSCR1(reg);
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sccr1_reg &= ~SSCR1_TIE;
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/*
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* PXA25x_SSP has no timeout, set up rx threshould for the
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* remaining RX bytes.
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*/
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if (pxa25x_ssp_comp(drv_data)) {
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sccr1_reg &= ~SSCR1_RFT;
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bytes_left = drv_data->rx_end - drv_data->rx;
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switch (drv_data->n_bytes) {
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case 4:
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bytes_left >>= 1;
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case 2:
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bytes_left >>= 1;
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}
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if (bytes_left > RX_THRESH_DFLT)
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bytes_left = RX_THRESH_DFLT;
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sccr1_reg |= SSCR1_RxTresh(bytes_left);
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}
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write_SSCR1(sccr1_reg, reg);
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}
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/* We did something */
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return IRQ_HANDLED;
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}
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static irqreturn_t ssp_int(int irq, void *dev_id)
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{
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struct driver_data *drv_data = dev_id;
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void __iomem *reg = drv_data->ioaddr;
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u32 sccr1_reg = read_SSCR1(reg);
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u32 mask = drv_data->mask_sr;
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u32 status;
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status = read_SSSR(reg);
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/* Ignore possible writes if we don't need to write */
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if (!(sccr1_reg & SSCR1_TIE))
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mask &= ~SSSR_TFS;
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if (!(status & mask))
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return IRQ_NONE;
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if (!drv_data->cur_msg) {
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write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
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write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
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if (!pxa25x_ssp_comp(drv_data))
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write_SSTO(0, reg);
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write_SSSR_CS(drv_data, drv_data->clear_sr);
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dev_err(&drv_data->pdev->dev, "bad message state "
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"in interrupt handler\n");
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/* Never fail */
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return IRQ_HANDLED;
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}
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return drv_data->transfer_handler(drv_data);
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}
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static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
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{
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unsigned long ssp_clk = drv_data->max_clk_rate;
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const struct ssp_device *ssp = drv_data->ssp;
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rate = min_t(int, ssp_clk, rate);
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if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
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return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
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else
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return ((ssp_clk / rate - 1) & 0xfff) << 8;
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}
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static void pump_transfers(unsigned long data)
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{
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struct driver_data *drv_data = (struct driver_data *)data;
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struct spi_message *message = NULL;
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struct spi_transfer *transfer = NULL;
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struct spi_transfer *previous = NULL;
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struct chip_data *chip = NULL;
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void __iomem *reg = drv_data->ioaddr;
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u32 clk_div = 0;
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u8 bits = 0;
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u32 speed = 0;
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u32 cr0;
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u32 cr1;
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u32 dma_thresh = drv_data->cur_chip->dma_threshold;
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u32 dma_burst = drv_data->cur_chip->dma_burst_size;
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/* Get current state information */
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message = drv_data->cur_msg;
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transfer = drv_data->cur_transfer;
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chip = drv_data->cur_chip;
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/* Handle for abort */
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if (message->state == ERROR_STATE) {
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message->status = -EIO;
|
|
giveback(drv_data);
|
|
return;
|
|
}
|
|
|
|
/* Handle end of message */
|
|
if (message->state == DONE_STATE) {
|
|
message->status = 0;
|
|
giveback(drv_data);
|
|
return;
|
|
}
|
|
|
|
/* Delay if requested at end of transfer before CS change */
|
|
if (message->state == RUNNING_STATE) {
|
|
previous = list_entry(transfer->transfer_list.prev,
|
|
struct spi_transfer,
|
|
transfer_list);
|
|
if (previous->delay_usecs)
|
|
udelay(previous->delay_usecs);
|
|
|
|
/* Drop chip select only if cs_change is requested */
|
|
if (previous->cs_change)
|
|
cs_deassert(drv_data);
|
|
}
|
|
|
|
/* Check if we can DMA this transfer */
|
|
if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) {
|
|
|
|
/* reject already-mapped transfers; PIO won't always work */
|
|
if (message->is_dma_mapped
|
|
|| transfer->rx_dma || transfer->tx_dma) {
|
|
dev_err(&drv_data->pdev->dev,
|
|
"pump_transfers: mapped transfer length "
|
|
"of %u is greater than %d\n",
|
|
transfer->len, MAX_DMA_LEN);
|
|
message->status = -EINVAL;
|
|
giveback(drv_data);
|
|
return;
|
|
}
|
|
|
|
/* warn ... we force this to PIO mode */
|
|
if (printk_ratelimit())
|
|
dev_warn(&message->spi->dev, "pump_transfers: "
|
|
"DMA disabled for transfer length %ld "
|
|
"greater than %d\n",
|
|
(long)drv_data->len, MAX_DMA_LEN);
|
|
}
|
|
|
|
/* Setup the transfer state based on the type of transfer */
|
|
if (pxa2xx_spi_flush(drv_data) == 0) {
|
|
dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
|
|
message->status = -EIO;
|
|
giveback(drv_data);
|
|
return;
|
|
}
|
|
drv_data->n_bytes = chip->n_bytes;
|
|
drv_data->tx = (void *)transfer->tx_buf;
|
|
drv_data->tx_end = drv_data->tx + transfer->len;
|
|
drv_data->rx = transfer->rx_buf;
|
|
drv_data->rx_end = drv_data->rx + transfer->len;
|
|
drv_data->rx_dma = transfer->rx_dma;
|
|
drv_data->tx_dma = transfer->tx_dma;
|
|
drv_data->len = transfer->len;
|
|
drv_data->write = drv_data->tx ? chip->write : null_writer;
|
|
drv_data->read = drv_data->rx ? chip->read : null_reader;
|
|
|
|
/* Change speed and bit per word on a per transfer */
|
|
cr0 = chip->cr0;
|
|
if (transfer->speed_hz || transfer->bits_per_word) {
|
|
|
|
bits = chip->bits_per_word;
|
|
speed = chip->speed_hz;
|
|
|
|
if (transfer->speed_hz)
|
|
speed = transfer->speed_hz;
|
|
|
|
if (transfer->bits_per_word)
|
|
bits = transfer->bits_per_word;
|
|
|
|
clk_div = ssp_get_clk_div(drv_data, speed);
|
|
|
|
if (bits <= 8) {
|
|
drv_data->n_bytes = 1;
|
|
drv_data->read = drv_data->read != null_reader ?
|
|
u8_reader : null_reader;
|
|
drv_data->write = drv_data->write != null_writer ?
|
|
u8_writer : null_writer;
|
|
} else if (bits <= 16) {
|
|
drv_data->n_bytes = 2;
|
|
drv_data->read = drv_data->read != null_reader ?
|
|
u16_reader : null_reader;
|
|
drv_data->write = drv_data->write != null_writer ?
|
|
u16_writer : null_writer;
|
|
} else if (bits <= 32) {
|
|
drv_data->n_bytes = 4;
|
|
drv_data->read = drv_data->read != null_reader ?
|
|
u32_reader : null_reader;
|
|
drv_data->write = drv_data->write != null_writer ?
|
|
u32_writer : null_writer;
|
|
}
|
|
/* if bits/word is changed in dma mode, then must check the
|
|
* thresholds and burst also */
|
|
if (chip->enable_dma) {
|
|
if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
|
|
message->spi,
|
|
bits, &dma_burst,
|
|
&dma_thresh))
|
|
if (printk_ratelimit())
|
|
dev_warn(&message->spi->dev,
|
|
"pump_transfers: "
|
|
"DMA burst size reduced to "
|
|
"match bits_per_word\n");
|
|
}
|
|
|
|
cr0 = clk_div
|
|
| SSCR0_Motorola
|
|
| SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
|
|
| SSCR0_SSE
|
|
| (bits > 16 ? SSCR0_EDSS : 0);
|
|
}
|
|
|
|
message->state = RUNNING_STATE;
|
|
|
|
drv_data->dma_mapped = 0;
|
|
if (pxa2xx_spi_dma_is_possible(drv_data->len))
|
|
drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
|
|
if (drv_data->dma_mapped) {
|
|
|
|
/* Ensure we have the correct interrupt handler */
|
|
drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
|
|
|
|
pxa2xx_spi_dma_prepare(drv_data, dma_burst);
|
|
|
|
/* Clear status and start DMA engine */
|
|
cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
|
|
write_SSSR(drv_data->clear_sr, reg);
|
|
|
|
pxa2xx_spi_dma_start(drv_data);
|
|
} else {
|
|
/* Ensure we have the correct interrupt handler */
|
|
drv_data->transfer_handler = interrupt_transfer;
|
|
|
|
/* Clear status */
|
|
cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
|
|
write_SSSR_CS(drv_data, drv_data->clear_sr);
|
|
}
|
|
|
|
/* see if we need to reload the config registers */
|
|
if ((read_SSCR0(reg) != cr0)
|
|
|| (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
|
|
(cr1 & SSCR1_CHANGE_MASK)) {
|
|
|
|
/* stop the SSP, and update the other bits */
|
|
write_SSCR0(cr0 & ~SSCR0_SSE, reg);
|
|
if (!pxa25x_ssp_comp(drv_data))
|
|
write_SSTO(chip->timeout, reg);
|
|
/* first set CR1 without interrupt and service enables */
|
|
write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
|
|
/* restart the SSP */
|
|
write_SSCR0(cr0, reg);
|
|
|
|
} else {
|
|
if (!pxa25x_ssp_comp(drv_data))
|
|
write_SSTO(chip->timeout, reg);
|
|
}
|
|
|
|
cs_assert(drv_data);
|
|
|
|
/* after chip select, release the data by enabling service
|
|
* requests and interrupts, without changing any mode bits */
|
|
write_SSCR1(cr1, reg);
|
|
}
|
|
|
|
static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
|
|
struct spi_message *msg)
|
|
{
|
|
struct driver_data *drv_data = spi_master_get_devdata(master);
|
|
|
|
drv_data->cur_msg = msg;
|
|
/* Initial message state*/
|
|
drv_data->cur_msg->state = START_STATE;
|
|
drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
|
|
struct spi_transfer,
|
|
transfer_list);
|
|
|
|
/* prepare to setup the SSP, in pump_transfers, using the per
|
|
* chip configuration */
|
|
drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
|
|
|
|
/* Mark as busy and launch transfers */
|
|
tasklet_schedule(&drv_data->pump_transfers);
|
|
return 0;
|
|
}
|
|
|
|
static int setup_cs(struct spi_device *spi, struct chip_data *chip,
|
|
struct pxa2xx_spi_chip *chip_info)
|
|
{
|
|
int err = 0;
|
|
|
|
if (chip == NULL || chip_info == NULL)
|
|
return 0;
|
|
|
|
/* NOTE: setup() can be called multiple times, possibly with
|
|
* different chip_info, release previously requested GPIO
|
|
*/
|
|
if (gpio_is_valid(chip->gpio_cs))
|
|
gpio_free(chip->gpio_cs);
|
|
|
|
/* If (*cs_control) is provided, ignore GPIO chip select */
|
|
if (chip_info->cs_control) {
|
|
chip->cs_control = chip_info->cs_control;
|
|
return 0;
|
|
}
|
|
|
|
if (gpio_is_valid(chip_info->gpio_cs)) {
|
|
err = gpio_request(chip_info->gpio_cs, "SPI_CS");
|
|
if (err) {
|
|
dev_err(&spi->dev, "failed to request chip select "
|
|
"GPIO%d\n", chip_info->gpio_cs);
|
|
return err;
|
|
}
|
|
|
|
chip->gpio_cs = chip_info->gpio_cs;
|
|
chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
|
|
|
|
err = gpio_direction_output(chip->gpio_cs,
|
|
!chip->gpio_cs_inverted);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
static int setup(struct spi_device *spi)
|
|
{
|
|
struct pxa2xx_spi_chip *chip_info = NULL;
|
|
struct chip_data *chip;
|
|
struct driver_data *drv_data = spi_master_get_devdata(spi->master);
|
|
unsigned int clk_div;
|
|
uint tx_thres = TX_THRESH_DFLT;
|
|
uint rx_thres = RX_THRESH_DFLT;
|
|
|
|
if (!pxa25x_ssp_comp(drv_data)
|
|
&& (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {
|
|
dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
|
|
"b/w not 4-32 for type non-PXA25x_SSP\n",
|
|
drv_data->ssp_type, spi->bits_per_word);
|
|
return -EINVAL;
|
|
} else if (pxa25x_ssp_comp(drv_data)
|
|
&& (spi->bits_per_word < 4
|
|
|| spi->bits_per_word > 16)) {
|
|
dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
|
|
"b/w not 4-16 for type PXA25x_SSP\n",
|
|
drv_data->ssp_type, spi->bits_per_word);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Only alloc on first setup */
|
|
chip = spi_get_ctldata(spi);
|
|
if (!chip) {
|
|
chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
|
|
if (!chip) {
|
|
dev_err(&spi->dev,
|
|
"failed setup: can't allocate chip data\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
if (drv_data->ssp_type == CE4100_SSP) {
|
|
if (spi->chip_select > 4) {
|
|
dev_err(&spi->dev, "failed setup: "
|
|
"cs number must not be > 4.\n");
|
|
kfree(chip);
|
|
return -EINVAL;
|
|
}
|
|
|
|
chip->frm = spi->chip_select;
|
|
} else
|
|
chip->gpio_cs = -1;
|
|
chip->enable_dma = 0;
|
|
chip->timeout = TIMOUT_DFLT;
|
|
}
|
|
|
|
/* protocol drivers may change the chip settings, so...
|
|
* if chip_info exists, use it */
|
|
chip_info = spi->controller_data;
|
|
|
|
/* chip_info isn't always needed */
|
|
chip->cr1 = 0;
|
|
if (chip_info) {
|
|
if (chip_info->timeout)
|
|
chip->timeout = chip_info->timeout;
|
|
if (chip_info->tx_threshold)
|
|
tx_thres = chip_info->tx_threshold;
|
|
if (chip_info->rx_threshold)
|
|
rx_thres = chip_info->rx_threshold;
|
|
chip->enable_dma = drv_data->master_info->enable_dma;
|
|
chip->dma_threshold = 0;
|
|
if (chip_info->enable_loopback)
|
|
chip->cr1 = SSCR1_LBM;
|
|
}
|
|
|
|
chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
|
|
(SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
|
|
|
|
/* set dma burst and threshold outside of chip_info path so that if
|
|
* chip_info goes away after setting chip->enable_dma, the
|
|
* burst and threshold can still respond to changes in bits_per_word */
|
|
if (chip->enable_dma) {
|
|
/* set up legal burst and threshold for dma */
|
|
if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
|
|
spi->bits_per_word,
|
|
&chip->dma_burst_size,
|
|
&chip->dma_threshold)) {
|
|
dev_warn(&spi->dev, "in setup: DMA burst size reduced "
|
|
"to match bits_per_word\n");
|
|
}
|
|
}
|
|
|
|
clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz);
|
|
chip->speed_hz = spi->max_speed_hz;
|
|
|
|
chip->cr0 = clk_div
|
|
| SSCR0_Motorola
|
|
| SSCR0_DataSize(spi->bits_per_word > 16 ?
|
|
spi->bits_per_word - 16 : spi->bits_per_word)
|
|
| SSCR0_SSE
|
|
| (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
|
|
chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
|
|
chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
|
|
| (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
|
|
|
|
/* NOTE: PXA25x_SSP _could_ use external clocking ... */
|
|
if (!pxa25x_ssp_comp(drv_data))
|
|
dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
|
|
drv_data->max_clk_rate
|
|
/ (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),
|
|
chip->enable_dma ? "DMA" : "PIO");
|
|
else
|
|
dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
|
|
drv_data->max_clk_rate / 2
|
|
/ (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)),
|
|
chip->enable_dma ? "DMA" : "PIO");
|
|
|
|
if (spi->bits_per_word <= 8) {
|
|
chip->n_bytes = 1;
|
|
chip->read = u8_reader;
|
|
chip->write = u8_writer;
|
|
} else if (spi->bits_per_word <= 16) {
|
|
chip->n_bytes = 2;
|
|
chip->read = u16_reader;
|
|
chip->write = u16_writer;
|
|
} else if (spi->bits_per_word <= 32) {
|
|
chip->cr0 |= SSCR0_EDSS;
|
|
chip->n_bytes = 4;
|
|
chip->read = u32_reader;
|
|
chip->write = u32_writer;
|
|
} else {
|
|
dev_err(&spi->dev, "invalid wordsize\n");
|
|
return -ENODEV;
|
|
}
|
|
chip->bits_per_word = spi->bits_per_word;
|
|
|
|
spi_set_ctldata(spi, chip);
|
|
|
|
if (drv_data->ssp_type == CE4100_SSP)
|
|
return 0;
|
|
|
|
return setup_cs(spi, chip, chip_info);
|
|
}
|
|
|
|
static void cleanup(struct spi_device *spi)
|
|
{
|
|
struct chip_data *chip = spi_get_ctldata(spi);
|
|
struct driver_data *drv_data = spi_master_get_devdata(spi->master);
|
|
|
|
if (!chip)
|
|
return;
|
|
|
|
if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
|
|
gpio_free(chip->gpio_cs);
|
|
|
|
kfree(chip);
|
|
}
|
|
|
|
static int pxa2xx_spi_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct pxa2xx_spi_master *platform_info;
|
|
struct spi_master *master;
|
|
struct driver_data *drv_data;
|
|
struct ssp_device *ssp;
|
|
int status;
|
|
|
|
platform_info = dev_get_platdata(dev);
|
|
if (!platform_info) {
|
|
dev_err(&pdev->dev, "missing platform data\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
ssp = pxa_ssp_request(pdev->id, pdev->name);
|
|
if (!ssp)
|
|
ssp = &platform_info->ssp;
|
|
|
|
if (!ssp->mmio_base) {
|
|
dev_err(&pdev->dev, "failed to get ssp\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* Allocate master with space for drv_data and null dma buffer */
|
|
master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
|
|
if (!master) {
|
|
dev_err(&pdev->dev, "cannot alloc spi_master\n");
|
|
pxa_ssp_free(ssp);
|
|
return -ENOMEM;
|
|
}
|
|
drv_data = spi_master_get_devdata(master);
|
|
drv_data->master = master;
|
|
drv_data->master_info = platform_info;
|
|
drv_data->pdev = pdev;
|
|
drv_data->ssp = ssp;
|
|
|
|
master->dev.parent = &pdev->dev;
|
|
master->dev.of_node = pdev->dev.of_node;
|
|
/* the spi->mode bits understood by this driver: */
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
|
|
|
|
master->bus_num = ssp->port_id;
|
|
master->num_chipselect = platform_info->num_chipselect;
|
|
master->dma_alignment = DMA_ALIGNMENT;
|
|
master->cleanup = cleanup;
|
|
master->setup = setup;
|
|
master->transfer_one_message = pxa2xx_spi_transfer_one_message;
|
|
|
|
drv_data->ssp_type = ssp->type;
|
|
drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT);
|
|
|
|
drv_data->ioaddr = ssp->mmio_base;
|
|
drv_data->ssdr_physical = ssp->phys_base + SSDR;
|
|
if (pxa25x_ssp_comp(drv_data)) {
|
|
drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
|
|
drv_data->dma_cr1 = 0;
|
|
drv_data->clear_sr = SSSR_ROR;
|
|
drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
|
|
} else {
|
|
drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
|
|
drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE;
|
|
drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
|
|
drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
|
|
}
|
|
|
|
status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
|
|
drv_data);
|
|
if (status < 0) {
|
|
dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
|
|
goto out_error_master_alloc;
|
|
}
|
|
|
|
/* Setup DMA if requested */
|
|
drv_data->tx_channel = -1;
|
|
drv_data->rx_channel = -1;
|
|
if (platform_info->enable_dma) {
|
|
status = pxa2xx_spi_dma_setup(drv_data);
|
|
if (status) {
|
|
dev_warn(dev, "failed to setup DMA, using PIO\n");
|
|
platform_info->enable_dma = false;
|
|
}
|
|
}
|
|
|
|
/* Enable SOC clock */
|
|
clk_prepare_enable(ssp->clk);
|
|
|
|
drv_data->max_clk_rate = clk_get_rate(ssp->clk);
|
|
|
|
/* Load default SSP configuration */
|
|
write_SSCR0(0, drv_data->ioaddr);
|
|
write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
|
|
SSCR1_TxTresh(TX_THRESH_DFLT),
|
|
drv_data->ioaddr);
|
|
write_SSCR0(SSCR0_SCR(2)
|
|
| SSCR0_Motorola
|
|
| SSCR0_DataSize(8),
|
|
drv_data->ioaddr);
|
|
if (!pxa25x_ssp_comp(drv_data))
|
|
write_SSTO(0, drv_data->ioaddr);
|
|
write_SSPSP(0, drv_data->ioaddr);
|
|
|
|
tasklet_init(&drv_data->pump_transfers, pump_transfers,
|
|
(unsigned long)drv_data);
|
|
|
|
/* Register with the SPI framework */
|
|
platform_set_drvdata(pdev, drv_data);
|
|
status = spi_register_master(master);
|
|
if (status != 0) {
|
|
dev_err(&pdev->dev, "problem registering spi master\n");
|
|
goto out_error_clock_enabled;
|
|
}
|
|
|
|
return status;
|
|
|
|
out_error_clock_enabled:
|
|
clk_disable_unprepare(ssp->clk);
|
|
pxa2xx_spi_dma_release(drv_data);
|
|
free_irq(ssp->irq, drv_data);
|
|
|
|
out_error_master_alloc:
|
|
spi_master_put(master);
|
|
pxa_ssp_free(ssp);
|
|
return status;
|
|
}
|
|
|
|
static int pxa2xx_spi_remove(struct platform_device *pdev)
|
|
{
|
|
struct driver_data *drv_data = platform_get_drvdata(pdev);
|
|
struct ssp_device *ssp;
|
|
|
|
if (!drv_data)
|
|
return 0;
|
|
ssp = drv_data->ssp;
|
|
|
|
/* Disable the SSP at the peripheral and SOC level */
|
|
write_SSCR0(0, drv_data->ioaddr);
|
|
clk_disable_unprepare(ssp->clk);
|
|
|
|
/* Release DMA */
|
|
if (drv_data->master_info->enable_dma)
|
|
pxa2xx_spi_dma_release(drv_data);
|
|
|
|
/* Release IRQ */
|
|
free_irq(ssp->irq, drv_data);
|
|
|
|
/* Release SSP */
|
|
pxa_ssp_free(ssp);
|
|
|
|
/* Disconnect from the SPI framework */
|
|
spi_unregister_master(drv_data->master);
|
|
|
|
/* Prevent double remove */
|
|
platform_set_drvdata(pdev, NULL);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void pxa2xx_spi_shutdown(struct platform_device *pdev)
|
|
{
|
|
int status = 0;
|
|
|
|
if ((status = pxa2xx_spi_remove(pdev)) != 0)
|
|
dev_err(&pdev->dev, "shutdown failed with %d\n", status);
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static int pxa2xx_spi_suspend(struct device *dev)
|
|
{
|
|
struct driver_data *drv_data = dev_get_drvdata(dev);
|
|
struct ssp_device *ssp = drv_data->ssp;
|
|
int status = 0;
|
|
|
|
status = spi_master_suspend(drv_data->master);
|
|
if (status != 0)
|
|
return status;
|
|
write_SSCR0(0, drv_data->ioaddr);
|
|
clk_disable_unprepare(ssp->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pxa2xx_spi_resume(struct device *dev)
|
|
{
|
|
struct driver_data *drv_data = dev_get_drvdata(dev);
|
|
struct ssp_device *ssp = drv_data->ssp;
|
|
int status = 0;
|
|
|
|
pxa2xx_spi_dma_resume(drv_data);
|
|
|
|
/* Enable the SSP clock */
|
|
clk_prepare_enable(ssp->clk);
|
|
|
|
/* Start the queue running */
|
|
status = spi_master_resume(drv_data->master);
|
|
if (status != 0) {
|
|
dev_err(dev, "problem starting queue (%d)\n", status);
|
|
return status;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
|
|
.suspend = pxa2xx_spi_suspend,
|
|
.resume = pxa2xx_spi_resume,
|
|
};
|
|
#endif
|
|
|
|
static struct platform_driver driver = {
|
|
.driver = {
|
|
.name = "pxa2xx-spi",
|
|
.owner = THIS_MODULE,
|
|
#ifdef CONFIG_PM
|
|
.pm = &pxa2xx_spi_pm_ops,
|
|
#endif
|
|
},
|
|
.probe = pxa2xx_spi_probe,
|
|
.remove = pxa2xx_spi_remove,
|
|
.shutdown = pxa2xx_spi_shutdown,
|
|
};
|
|
|
|
static int __init pxa2xx_spi_init(void)
|
|
{
|
|
return platform_driver_register(&driver);
|
|
}
|
|
subsys_initcall(pxa2xx_spi_init);
|
|
|
|
static void __exit pxa2xx_spi_exit(void)
|
|
{
|
|
platform_driver_unregister(&driver);
|
|
}
|
|
module_exit(pxa2xx_spi_exit);
|