![Hartley Sweeten](/assets/img/avatar_default.png)
Fix trivial build warning due to incompatible pointer type. ep93xx_timer_interrupt() has the wrong return type causing a warning during the build. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
563 lines
15 KiB
C
563 lines
15 KiB
C
/*
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* arch/arm/mach-ep93xx/core.c
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* Core routines for Cirrus EP93xx chips.
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*
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* Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
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* Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
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*
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* Thanks go to Michael Burian and Ray Lehtiniemi for their key
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* role in the ep93xx linux community.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/serial.h>
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#include <linux/tty.h>
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#include <linux/bitops.h>
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#include <linux/serial_8250.h>
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#include <linux/serial_core.h>
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#include <linux/device.h>
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#include <linux/mm.h>
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#include <linux/dma-mapping.h>
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#include <linux/time.h>
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#include <linux/timex.h>
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#include <linux/delay.h>
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#include <linux/termios.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/serial.h>
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#include <linux/io.h>
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#include <linux/i2c.h>
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#include <linux/i2c-gpio.h>
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#include <asm/types.h>
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#include <asm/setup.h>
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#include <asm/memory.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/system.h>
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#include <asm/tlbflush.h>
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#include <asm/pgtable.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <asm/mach/irq.h>
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#include <mach/gpio.h>
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#include <asm/hardware/vic.h>
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/*************************************************************************
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* Static I/O mappings that are needed for all EP93xx platforms
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*************************************************************************/
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static struct map_desc ep93xx_io_desc[] __initdata = {
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{
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.virtual = EP93XX_AHB_VIRT_BASE,
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.pfn = __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
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.length = EP93XX_AHB_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = EP93XX_APB_VIRT_BASE,
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.pfn = __phys_to_pfn(EP93XX_APB_PHYS_BASE),
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.length = EP93XX_APB_SIZE,
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.type = MT_DEVICE,
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},
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};
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void __init ep93xx_map_io(void)
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{
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iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
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}
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/*************************************************************************
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* Timer handling for EP93xx
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*************************************************************************
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* The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
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* 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
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* an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
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* is free-running, and can't generate interrupts.
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*
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* The 508 kHz timers are ideal for use for the timer interrupt, as the
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* most common values of HZ divide 508 kHz nicely. We pick one of the 16
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* bit timers (timer 1) since we don't need more than 16 bits of reload
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* value as long as HZ >= 8.
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*
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* The higher clock rate of timer 4 makes it a better choice than the
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* other timers for use in gettimeoffset(), while the fact that it can't
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* generate interrupts means we don't have to worry about not being able
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* to use this timer for something else. We also use timer 4 for keeping
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* track of lost jiffies.
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*/
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static unsigned int last_jiffy_time;
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#define TIMER4_TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
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static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
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{
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__raw_writel(1, EP93XX_TIMER1_CLEAR);
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while ((signed long)
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(__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
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>= TIMER4_TICKS_PER_JIFFY) {
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last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
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timer_tick();
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}
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return IRQ_HANDLED;
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}
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static struct irqaction ep93xx_timer_irq = {
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.name = "ep93xx timer",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = ep93xx_timer_interrupt,
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};
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static void __init ep93xx_timer_init(void)
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{
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/* Enable periodic HZ timer. */
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__raw_writel(0x48, EP93XX_TIMER1_CONTROL);
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__raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD);
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__raw_writel(0xc8, EP93XX_TIMER1_CONTROL);
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/* Enable lost jiffy timer. */
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__raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);
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setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
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}
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static unsigned long ep93xx_gettimeoffset(void)
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{
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int offset;
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offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
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/* Calculate (1000000 / 983040) * offset. */
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return offset + (53 * offset / 3072);
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}
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struct sys_timer ep93xx_timer = {
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.init = ep93xx_timer_init,
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.offset = ep93xx_gettimeoffset,
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};
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/*************************************************************************
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* GPIO handling for EP93xx
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*************************************************************************/
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static unsigned char gpio_int_unmasked[3];
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static unsigned char gpio_int_enabled[3];
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static unsigned char gpio_int_type1[3];
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static unsigned char gpio_int_type2[3];
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static unsigned char gpio_int_debouce[3];
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/* Port ordering is: A B F */
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static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
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static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
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static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
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static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
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static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
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void ep93xx_gpio_update_int_params(unsigned port)
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{
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BUG_ON(port > 2);
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__raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
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__raw_writeb(gpio_int_type2[port],
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EP93XX_GPIO_REG(int_type2_register_offset[port]));
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__raw_writeb(gpio_int_type1[port],
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EP93XX_GPIO_REG(int_type1_register_offset[port]));
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__raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
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EP93XX_GPIO_REG(int_en_register_offset[port]));
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}
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void ep93xx_gpio_int_mask(unsigned line)
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{
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gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
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}
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void ep93xx_gpio_int_debounce(unsigned int irq, int enable)
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{
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int line = irq_to_gpio(irq);
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int port = line >> 3;
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int port_mask = 1 << (line & 7);
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if (enable)
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gpio_int_debouce[port] |= port_mask;
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else
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gpio_int_debouce[port] &= ~port_mask;
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__raw_writeb(gpio_int_debouce[port],
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EP93XX_GPIO_REG(int_debounce_register_offset[port]));
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}
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EXPORT_SYMBOL(ep93xx_gpio_int_debounce);
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/*************************************************************************
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* EP93xx IRQ handling
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*************************************************************************/
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static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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unsigned char status;
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int i;
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status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
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for (i = 0; i < 8; i++) {
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if (status & (1 << i)) {
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int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
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generic_handle_irq(gpio_irq);
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}
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}
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status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
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for (i = 0; i < 8; i++) {
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if (status & (1 << i)) {
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int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
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desc = irq_desc + gpio_irq;
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generic_handle_irq(gpio_irq);
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}
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}
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}
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static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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/*
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* map discontiguous hw irq range to continous sw irq range:
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*
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* IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
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*/
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int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
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int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
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generic_handle_irq(gpio_irq);
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}
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static void ep93xx_gpio_irq_ack(unsigned int irq)
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{
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int line = irq_to_gpio(irq);
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int port = line >> 3;
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int port_mask = 1 << (line & 7);
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if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
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gpio_int_type2[port] ^= port_mask; /* switch edge direction */
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ep93xx_gpio_update_int_params(port);
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}
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__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
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}
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static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
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{
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int line = irq_to_gpio(irq);
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int port = line >> 3;
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int port_mask = 1 << (line & 7);
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if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
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gpio_int_type2[port] ^= port_mask; /* switch edge direction */
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gpio_int_unmasked[port] &= ~port_mask;
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ep93xx_gpio_update_int_params(port);
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__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
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}
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static void ep93xx_gpio_irq_mask(unsigned int irq)
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{
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int line = irq_to_gpio(irq);
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int port = line >> 3;
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gpio_int_unmasked[port] &= ~(1 << (line & 7));
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ep93xx_gpio_update_int_params(port);
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}
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static void ep93xx_gpio_irq_unmask(unsigned int irq)
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{
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int line = irq_to_gpio(irq);
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int port = line >> 3;
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gpio_int_unmasked[port] |= 1 << (line & 7);
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ep93xx_gpio_update_int_params(port);
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}
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/*
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* gpio_int_type1 controls whether the interrupt is level (0) or
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* edge (1) triggered, while gpio_int_type2 controls whether it
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* triggers on low/falling (0) or high/rising (1).
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*/
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static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
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{
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struct irq_desc *desc = irq_desc + irq;
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const int gpio = irq_to_gpio(irq);
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const int port = gpio >> 3;
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const int port_mask = 1 << (gpio & 7);
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gpio_direction_input(gpio);
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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gpio_int_type1[port] |= port_mask;
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gpio_int_type2[port] |= port_mask;
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desc->handle_irq = handle_edge_irq;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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gpio_int_type1[port] |= port_mask;
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gpio_int_type2[port] &= ~port_mask;
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desc->handle_irq = handle_edge_irq;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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gpio_int_type1[port] &= ~port_mask;
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gpio_int_type2[port] |= port_mask;
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desc->handle_irq = handle_level_irq;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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gpio_int_type1[port] &= ~port_mask;
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gpio_int_type2[port] &= ~port_mask;
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desc->handle_irq = handle_level_irq;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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gpio_int_type1[port] |= port_mask;
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/* set initial polarity based on current input level */
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if (gpio_get_value(gpio))
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gpio_int_type2[port] &= ~port_mask; /* falling */
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else
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gpio_int_type2[port] |= port_mask; /* rising */
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desc->handle_irq = handle_edge_irq;
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break;
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default:
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pr_err("ep93xx: failed to set irq type %d for gpio %d\n",
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type, gpio);
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return -EINVAL;
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}
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gpio_int_enabled[port] |= port_mask;
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desc->status &= ~IRQ_TYPE_SENSE_MASK;
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desc->status |= type & IRQ_TYPE_SENSE_MASK;
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ep93xx_gpio_update_int_params(port);
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return 0;
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}
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static struct irq_chip ep93xx_gpio_irq_chip = {
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.name = "GPIO",
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.ack = ep93xx_gpio_irq_ack,
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.mask_ack = ep93xx_gpio_irq_mask_ack,
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.mask = ep93xx_gpio_irq_mask,
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.unmask = ep93xx_gpio_irq_unmask,
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.set_type = ep93xx_gpio_irq_type,
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};
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void __init ep93xx_init_irq(void)
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{
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int gpio_irq;
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vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK);
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vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK);
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for (gpio_irq = gpio_to_irq(0);
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gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
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set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
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set_irq_handler(gpio_irq, handle_level_irq);
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set_irq_flags(gpio_irq, IRQF_VALID);
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}
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set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
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set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
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set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
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set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
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set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
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set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
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set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
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set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
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set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
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}
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/*************************************************************************
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* EP93xx peripheral handling
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*************************************************************************/
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#define EP93XX_UART_MCR_OFFSET (0x0100)
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static void ep93xx_uart_set_mctrl(struct amba_device *dev,
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void __iomem *base, unsigned int mctrl)
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{
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unsigned int mcr;
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mcr = 0;
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if (!(mctrl & TIOCM_RTS))
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mcr |= 2;
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if (!(mctrl & TIOCM_DTR))
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mcr |= 1;
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__raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
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}
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static struct amba_pl010_data ep93xx_uart_data = {
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.set_mctrl = ep93xx_uart_set_mctrl,
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};
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static struct amba_device uart1_device = {
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.dev = {
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.init_name = "apb:uart1",
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.platform_data = &ep93xx_uart_data,
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},
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.res = {
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.start = EP93XX_UART1_PHYS_BASE,
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.end = EP93XX_UART1_PHYS_BASE + 0x0fff,
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.flags = IORESOURCE_MEM,
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},
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.irq = { IRQ_EP93XX_UART1, NO_IRQ },
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.periphid = 0x00041010,
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};
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static struct amba_device uart2_device = {
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.dev = {
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.init_name = "apb:uart2",
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.platform_data = &ep93xx_uart_data,
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},
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.res = {
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.start = EP93XX_UART2_PHYS_BASE,
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.end = EP93XX_UART2_PHYS_BASE + 0x0fff,
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.flags = IORESOURCE_MEM,
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},
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.irq = { IRQ_EP93XX_UART2, NO_IRQ },
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.periphid = 0x00041010,
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};
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static struct amba_device uart3_device = {
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.dev = {
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.init_name = "apb:uart3",
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.platform_data = &ep93xx_uart_data,
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},
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.res = {
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.start = EP93XX_UART3_PHYS_BASE,
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.end = EP93XX_UART3_PHYS_BASE + 0x0fff,
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.flags = IORESOURCE_MEM,
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},
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.irq = { IRQ_EP93XX_UART3, NO_IRQ },
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.periphid = 0x00041010,
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};
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static struct platform_device ep93xx_rtc_device = {
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.name = "ep93xx-rtc",
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.id = -1,
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.num_resources = 0,
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};
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static struct resource ep93xx_ohci_resources[] = {
|
|
[0] = {
|
|
.start = EP93XX_USB_PHYS_BASE,
|
|
.end = EP93XX_USB_PHYS_BASE + 0x0fff,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = IRQ_EP93XX_USB,
|
|
.end = IRQ_EP93XX_USB,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
|
|
static struct platform_device ep93xx_ohci_device = {
|
|
.name = "ep93xx-ohci",
|
|
.id = -1,
|
|
.dev = {
|
|
.dma_mask = &ep93xx_ohci_device.dev.coherent_dma_mask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
},
|
|
.num_resources = ARRAY_SIZE(ep93xx_ohci_resources),
|
|
.resource = ep93xx_ohci_resources,
|
|
};
|
|
|
|
static struct ep93xx_eth_data ep93xx_eth_data;
|
|
|
|
static struct resource ep93xx_eth_resource[] = {
|
|
{
|
|
.start = EP93XX_ETHERNET_PHYS_BASE,
|
|
.end = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
|
|
.flags = IORESOURCE_MEM,
|
|
}, {
|
|
.start = IRQ_EP93XX_ETHERNET,
|
|
.end = IRQ_EP93XX_ETHERNET,
|
|
.flags = IORESOURCE_IRQ,
|
|
}
|
|
};
|
|
|
|
static struct platform_device ep93xx_eth_device = {
|
|
.name = "ep93xx-eth",
|
|
.id = -1,
|
|
.dev = {
|
|
.platform_data = &ep93xx_eth_data,
|
|
},
|
|
.num_resources = ARRAY_SIZE(ep93xx_eth_resource),
|
|
.resource = ep93xx_eth_resource,
|
|
};
|
|
|
|
void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr)
|
|
{
|
|
if (copy_addr) {
|
|
memcpy(data->dev_addr,
|
|
(void *)(EP93XX_ETHERNET_BASE + 0x50), 6);
|
|
}
|
|
|
|
ep93xx_eth_data = *data;
|
|
platform_device_register(&ep93xx_eth_device);
|
|
}
|
|
|
|
static struct i2c_gpio_platform_data ep93xx_i2c_data = {
|
|
.sda_pin = EP93XX_GPIO_LINE_EEDAT,
|
|
.sda_is_open_drain = 0,
|
|
.scl_pin = EP93XX_GPIO_LINE_EECLK,
|
|
.scl_is_open_drain = 0,
|
|
.udelay = 2,
|
|
};
|
|
|
|
static struct platform_device ep93xx_i2c_device = {
|
|
.name = "i2c-gpio",
|
|
.id = 0,
|
|
.dev.platform_data = &ep93xx_i2c_data,
|
|
};
|
|
|
|
void __init ep93xx_register_i2c(struct i2c_board_info *devices, int num)
|
|
{
|
|
i2c_register_board_info(0, devices, num);
|
|
platform_device_register(&ep93xx_i2c_device);
|
|
}
|
|
|
|
extern void ep93xx_gpio_init(void);
|
|
|
|
void __init ep93xx_init_devices(void)
|
|
{
|
|
unsigned int v;
|
|
|
|
/*
|
|
* Disallow access to MaverickCrunch initially.
|
|
*/
|
|
v = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG);
|
|
v &= ~EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE;
|
|
__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
|
|
__raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG);
|
|
|
|
ep93xx_gpio_init();
|
|
|
|
amba_device_register(&uart1_device, &iomem_resource);
|
|
amba_device_register(&uart2_device, &iomem_resource);
|
|
amba_device_register(&uart3_device, &iomem_resource);
|
|
|
|
platform_device_register(&ep93xx_rtc_device);
|
|
platform_device_register(&ep93xx_ohci_device);
|
|
}
|