c0bf31320d
This roughly corresponds with OMAP commits: 7d06c48, 3241b19, 88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8. For both OMAP2 and OMAP3, we note the reference and bypass clocks in the DPLL data structure. Whenever we modify the DPLL rate, we first ensure that both the reference and bypass clocks are enabled. Then, we decide whether to use the reference and DPLL, or the bypass clock if the desired rate is identical to the bypass rate, and program the DPLL appropriately. Finally, we update the clock's parent, and then disable the unused clocks. This keeps the parents correctly balanced, and more importantly ensures that the bypass clock is running whenever we reprogram the DPLL. This is especially important because the procedure for reprogramming the DPLL involves switching to the bypass clock. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
164 lines
4.1 KiB
C
164 lines
4.1 KiB
C
/*
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* linux/arch/arm/mach-omap2/sdrc2xxx.c
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*
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* SDRAM timing related functions for OMAP2xxx
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*
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* Copyright (C) 2005, 2008 Texas Instruments Inc.
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* Copyright (C) 2005, 2008 Nokia Corporation
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*
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* Tony Lindgren <tony@atomide.com>
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* Paul Walmsley
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <mach/common.h>
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#include <mach/clock.h>
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#include <mach/sram.h>
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#include "prm.h"
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#include "clock.h"
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#include <mach/sdrc.h>
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#include "sdrc.h"
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/* Memory timing, DLL mode flags */
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#define M_DDR 1
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#define M_LOCK_CTRL (1 << 2)
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#define M_UNLOCK 0
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#define M_LOCK 1
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static struct memory_timings mem_timings;
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static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
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static u32 omap2xxx_sdrc_get_slow_dll_ctrl(void)
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{
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return mem_timings.slow_dll_ctrl;
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}
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static u32 omap2xxx_sdrc_get_fast_dll_ctrl(void)
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{
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return mem_timings.fast_dll_ctrl;
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}
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static u32 omap2xxx_sdrc_get_type(void)
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{
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return mem_timings.m_type;
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}
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/*
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* Check the DLL lock state, and return tue if running in unlock mode.
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* This is needed to compensate for the shifted DLL value in unlock mode.
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*/
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u32 omap2xxx_sdrc_dll_is_unlocked(void)
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{
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/* dlla and dllb are a set */
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u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL);
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if ((dll_state & (1 << 2)) == (1 << 2))
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return 1;
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else
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return 0;
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}
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/*
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* 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
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* Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
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* CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
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*
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* Used by the clock framework during CORE DPLL changes
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*/
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u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
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{
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u32 dll_ctrl, m_type;
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u32 prev = curr_perf_level;
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unsigned long flags;
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if ((curr_perf_level == level) && !force)
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return prev;
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if (level == CORE_CLK_SRC_DPLL)
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dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl();
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else if (level == CORE_CLK_SRC_DPLL_X2)
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dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl();
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else
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return prev;
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m_type = omap2xxx_sdrc_get_type();
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local_irq_save(flags);
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__raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP);
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omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
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curr_perf_level = level;
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local_irq_restore(flags);
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return prev;
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}
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/* Used by the clock framework during CORE DPLL changes */
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void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode)
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{
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unsigned long dll_cnt;
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u32 fast_dll = 0;
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/* DDR = 1, SDR = 0 */
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mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1);
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/* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
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* In the case of 2422, its ok to use CS1 instead of CS0.
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*/
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if (cpu_is_omap2422())
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mem_timings.base_cs = 1;
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else
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mem_timings.base_cs = 0;
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if (mem_timings.m_type != M_DDR)
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return;
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/* With DDR we need to determine the low frequency DLL value */
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if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
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mem_timings.dll_mode = M_UNLOCK;
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else
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mem_timings.dll_mode = M_LOCK;
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if (mem_timings.base_cs == 0) {
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fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
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dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
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} else {
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fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
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dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
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}
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if (force_lock_to_unlock_mode) {
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fast_dll &= ~0xff00;
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fast_dll |= dll_cnt; /* Current lock mode */
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}
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/* set fast timings with DLL filter disabled */
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mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));
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/* No disruptions, DDR will be offline & C-ABI not followed */
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omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
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mem_timings.fast_dll_ctrl,
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mem_timings.base_cs,
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force_lock_to_unlock_mode);
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mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */
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/* Turn status into unlock ctrl */
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mem_timings.slow_dll_ctrl |=
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((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
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/* 90 degree phase for anything below 133Mhz + disable DLL filter */
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mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
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}
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