![Will Deacon](/assets/img/avatar_default.png)
force_signal_inject is a little flakey: * It only knows about SIGILL and SIGSEGV, so can potentially deliver other signals based on a partially initialised siginfo_t * It sets si_addr to point at the PC for SIGSEGV * It always operates on current, so doesn't need the regs argument This patch fixes these issues by always assigning the si_addr field to the address parameter of the function and updates the callers (including those that indirectly call via arm64_notify_segfault) accordingly. Signed-off-by: Will Deacon <will.deacon@arm.com>
646 lines
16 KiB
C
646 lines
16 KiB
C
/*
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* Copyright (C) 2014 ARM Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/cpu.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/perf_event.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/sysctl.h>
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#include <asm/cpufeature.h>
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#include <asm/insn.h>
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#include <asm/sysreg.h>
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#include <asm/system_misc.h>
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#include <asm/traps.h>
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#include <asm/kprobes.h>
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#include <linux/uaccess.h>
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#include <asm/cpufeature.h>
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#define CREATE_TRACE_POINTS
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#include "trace-events-emulation.h"
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/*
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* The runtime support for deprecated instruction support can be in one of
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* following three states -
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*
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* 0 = undef
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* 1 = emulate (software emulation)
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* 2 = hw (supported in hardware)
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*/
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enum insn_emulation_mode {
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INSN_UNDEF,
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INSN_EMULATE,
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INSN_HW,
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};
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enum legacy_insn_status {
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INSN_DEPRECATED,
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INSN_OBSOLETE,
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};
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struct insn_emulation_ops {
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const char *name;
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enum legacy_insn_status status;
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struct undef_hook *hooks;
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int (*set_hw_mode)(bool enable);
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};
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struct insn_emulation {
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struct list_head node;
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struct insn_emulation_ops *ops;
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int current_mode;
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int min;
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int max;
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};
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static LIST_HEAD(insn_emulation);
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static int nr_insn_emulated __initdata;
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static DEFINE_RAW_SPINLOCK(insn_emulation_lock);
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static void register_emulation_hooks(struct insn_emulation_ops *ops)
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{
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struct undef_hook *hook;
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BUG_ON(!ops->hooks);
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for (hook = ops->hooks; hook->instr_mask; hook++)
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register_undef_hook(hook);
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pr_notice("Registered %s emulation handler\n", ops->name);
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}
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static void remove_emulation_hooks(struct insn_emulation_ops *ops)
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{
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struct undef_hook *hook;
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BUG_ON(!ops->hooks);
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for (hook = ops->hooks; hook->instr_mask; hook++)
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unregister_undef_hook(hook);
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pr_notice("Removed %s emulation handler\n", ops->name);
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}
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static void enable_insn_hw_mode(void *data)
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{
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struct insn_emulation *insn = (struct insn_emulation *)data;
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if (insn->ops->set_hw_mode)
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insn->ops->set_hw_mode(true);
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}
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static void disable_insn_hw_mode(void *data)
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{
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struct insn_emulation *insn = (struct insn_emulation *)data;
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if (insn->ops->set_hw_mode)
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insn->ops->set_hw_mode(false);
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}
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/* Run set_hw_mode(mode) on all active CPUs */
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static int run_all_cpu_set_hw_mode(struct insn_emulation *insn, bool enable)
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{
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if (!insn->ops->set_hw_mode)
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return -EINVAL;
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if (enable)
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on_each_cpu(enable_insn_hw_mode, (void *)insn, true);
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else
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on_each_cpu(disable_insn_hw_mode, (void *)insn, true);
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return 0;
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}
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/*
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* Run set_hw_mode for all insns on a starting CPU.
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* Returns:
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* 0 - If all the hooks ran successfully.
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* -EINVAL - At least one hook is not supported by the CPU.
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*/
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static int run_all_insn_set_hw_mode(unsigned int cpu)
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{
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int rc = 0;
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unsigned long flags;
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struct insn_emulation *insn;
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raw_spin_lock_irqsave(&insn_emulation_lock, flags);
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list_for_each_entry(insn, &insn_emulation, node) {
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bool enable = (insn->current_mode == INSN_HW);
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if (insn->ops->set_hw_mode && insn->ops->set_hw_mode(enable)) {
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pr_warn("CPU[%u] cannot support the emulation of %s",
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cpu, insn->ops->name);
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rc = -EINVAL;
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}
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}
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raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
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return rc;
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}
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static int update_insn_emulation_mode(struct insn_emulation *insn,
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enum insn_emulation_mode prev)
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{
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int ret = 0;
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switch (prev) {
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case INSN_UNDEF: /* Nothing to be done */
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break;
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case INSN_EMULATE:
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remove_emulation_hooks(insn->ops);
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break;
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case INSN_HW:
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if (!run_all_cpu_set_hw_mode(insn, false))
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pr_notice("Disabled %s support\n", insn->ops->name);
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break;
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}
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switch (insn->current_mode) {
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case INSN_UNDEF:
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break;
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case INSN_EMULATE:
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register_emulation_hooks(insn->ops);
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break;
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case INSN_HW:
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ret = run_all_cpu_set_hw_mode(insn, true);
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if (!ret)
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pr_notice("Enabled %s support\n", insn->ops->name);
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break;
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}
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return ret;
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}
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static void __init register_insn_emulation(struct insn_emulation_ops *ops)
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{
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unsigned long flags;
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struct insn_emulation *insn;
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insn = kzalloc(sizeof(*insn), GFP_KERNEL);
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insn->ops = ops;
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insn->min = INSN_UNDEF;
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switch (ops->status) {
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case INSN_DEPRECATED:
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insn->current_mode = INSN_EMULATE;
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/* Disable the HW mode if it was turned on at early boot time */
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run_all_cpu_set_hw_mode(insn, false);
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insn->max = INSN_HW;
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break;
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case INSN_OBSOLETE:
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insn->current_mode = INSN_UNDEF;
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insn->max = INSN_EMULATE;
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break;
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}
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raw_spin_lock_irqsave(&insn_emulation_lock, flags);
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list_add(&insn->node, &insn_emulation);
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nr_insn_emulated++;
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raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
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/* Register any handlers if required */
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update_insn_emulation_mode(insn, INSN_UNDEF);
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}
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static int emulation_proc_handler(struct ctl_table *table, int write,
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void __user *buffer, size_t *lenp,
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loff_t *ppos)
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{
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int ret = 0;
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struct insn_emulation *insn = (struct insn_emulation *) table->data;
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enum insn_emulation_mode prev_mode = insn->current_mode;
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table->data = &insn->current_mode;
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ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
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if (ret || !write || prev_mode == insn->current_mode)
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goto ret;
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ret = update_insn_emulation_mode(insn, prev_mode);
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if (ret) {
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/* Mode change failed, revert to previous mode. */
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insn->current_mode = prev_mode;
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update_insn_emulation_mode(insn, INSN_UNDEF);
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}
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ret:
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table->data = insn;
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return ret;
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}
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static void __init register_insn_emulation_sysctl(void)
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{
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unsigned long flags;
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int i = 0;
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struct insn_emulation *insn;
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struct ctl_table *insns_sysctl, *sysctl;
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insns_sysctl = kzalloc(sizeof(*sysctl) * (nr_insn_emulated + 1),
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GFP_KERNEL);
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raw_spin_lock_irqsave(&insn_emulation_lock, flags);
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list_for_each_entry(insn, &insn_emulation, node) {
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sysctl = &insns_sysctl[i];
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sysctl->mode = 0644;
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sysctl->maxlen = sizeof(int);
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sysctl->procname = insn->ops->name;
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sysctl->data = insn;
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sysctl->extra1 = &insn->min;
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sysctl->extra2 = &insn->max;
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sysctl->proc_handler = emulation_proc_handler;
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i++;
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}
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raw_spin_unlock_irqrestore(&insn_emulation_lock, flags);
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register_sysctl("abi", insns_sysctl);
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}
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/*
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* Implement emulation of the SWP/SWPB instructions using load-exclusive and
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* store-exclusive.
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*
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* Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>]
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* Where: Rt = destination
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* Rt2 = source
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* Rn = address
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*/
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/*
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* Error-checking SWP macros implemented using ldxr{b}/stxr{b}
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*/
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/* Arbitrary constant to ensure forward-progress of the LL/SC loop */
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#define __SWP_LL_SC_LOOPS 4
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#define __user_swpX_asm(data, addr, res, temp, temp2, B) \
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do { \
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uaccess_enable(); \
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__asm__ __volatile__( \
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" mov %w3, %w7\n" \
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"0: ldxr"B" %w2, [%4]\n" \
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"1: stxr"B" %w0, %w1, [%4]\n" \
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" cbz %w0, 2f\n" \
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" sub %w3, %w3, #1\n" \
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" cbnz %w3, 0b\n" \
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" mov %w0, %w5\n" \
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" b 3f\n" \
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"2:\n" \
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" mov %w1, %w2\n" \
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"3:\n" \
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" .pushsection .fixup,\"ax\"\n" \
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" .align 2\n" \
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"4: mov %w0, %w6\n" \
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" b 3b\n" \
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" .popsection" \
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_ASM_EXTABLE(0b, 4b) \
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_ASM_EXTABLE(1b, 4b) \
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: "=&r" (res), "+r" (data), "=&r" (temp), "=&r" (temp2) \
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: "r" ((unsigned long)addr), "i" (-EAGAIN), \
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"i" (-EFAULT), \
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"i" (__SWP_LL_SC_LOOPS) \
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: "memory"); \
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uaccess_disable(); \
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} while (0)
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#define __user_swp_asm(data, addr, res, temp, temp2) \
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__user_swpX_asm(data, addr, res, temp, temp2, "")
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#define __user_swpb_asm(data, addr, res, temp, temp2) \
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__user_swpX_asm(data, addr, res, temp, temp2, "b")
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/*
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* Bit 22 of the instruction encoding distinguishes between
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* the SWP and SWPB variants (bit set means SWPB).
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*/
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#define TYPE_SWPB (1 << 22)
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static int emulate_swpX(unsigned int address, unsigned int *data,
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unsigned int type)
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{
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unsigned int res = 0;
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if ((type != TYPE_SWPB) && (address & 0x3)) {
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/* SWP to unaligned address not permitted */
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pr_debug("SWP instruction on unaligned pointer!\n");
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return -EFAULT;
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}
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while (1) {
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unsigned long temp, temp2;
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if (type == TYPE_SWPB)
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__user_swpb_asm(*data, address, res, temp, temp2);
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else
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__user_swp_asm(*data, address, res, temp, temp2);
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if (likely(res != -EAGAIN) || signal_pending(current))
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break;
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cond_resched();
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}
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return res;
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}
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#define ARM_OPCODE_CONDTEST_FAIL 0
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#define ARM_OPCODE_CONDTEST_PASS 1
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#define ARM_OPCODE_CONDTEST_UNCOND 2
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#define ARM_OPCODE_CONDITION_UNCOND 0xf
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static unsigned int __kprobes aarch32_check_condition(u32 opcode, u32 psr)
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{
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u32 cc_bits = opcode >> 28;
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if (cc_bits != ARM_OPCODE_CONDITION_UNCOND) {
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if ((*aarch32_opcode_cond_checks[cc_bits])(psr))
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return ARM_OPCODE_CONDTEST_PASS;
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else
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return ARM_OPCODE_CONDTEST_FAIL;
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}
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return ARM_OPCODE_CONDTEST_UNCOND;
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}
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/*
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* swp_handler logs the id of calling process, dissects the instruction, sanity
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* checks the memory location, calls emulate_swpX for the actual operation and
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* deals with fixup/error handling before returning
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*/
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static int swp_handler(struct pt_regs *regs, u32 instr)
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{
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u32 destreg, data, type, address = 0;
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const void __user *user_ptr;
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int rn, rt2, res = 0;
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perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
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type = instr & TYPE_SWPB;
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switch (aarch32_check_condition(instr, regs->pstate)) {
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case ARM_OPCODE_CONDTEST_PASS:
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break;
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case ARM_OPCODE_CONDTEST_FAIL:
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/* Condition failed - return to next instruction */
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goto ret;
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case ARM_OPCODE_CONDTEST_UNCOND:
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/* If unconditional encoding - not a SWP, undef */
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return -EFAULT;
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default:
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return -EINVAL;
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}
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rn = aarch32_insn_extract_reg_num(instr, A32_RN_OFFSET);
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rt2 = aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET);
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address = (u32)regs->user_regs.regs[rn];
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data = (u32)regs->user_regs.regs[rt2];
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destreg = aarch32_insn_extract_reg_num(instr, A32_RT_OFFSET);
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pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n",
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rn, address, destreg,
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aarch32_insn_extract_reg_num(instr, A32_RT2_OFFSET), data);
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/* Check access in reasonable access range for both SWP and SWPB */
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user_ptr = (const void __user *)(unsigned long)(address & ~3);
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if (!access_ok(VERIFY_WRITE, user_ptr, 4)) {
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pr_debug("SWP{B} emulation: access to 0x%08x not allowed!\n",
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address);
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goto fault;
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}
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res = emulate_swpX(address, &data, type);
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if (res == -EFAULT)
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goto fault;
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else if (res == 0)
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regs->user_regs.regs[destreg] = data;
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ret:
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if (type == TYPE_SWPB)
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trace_instruction_emulation("swpb", regs->pc);
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else
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trace_instruction_emulation("swp", regs->pc);
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pr_warn_ratelimited("\"%s\" (%ld) uses obsolete SWP{B} instruction at 0x%llx\n",
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current->comm, (unsigned long)current->pid, regs->pc);
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arm64_skip_faulting_instruction(regs, 4);
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return 0;
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fault:
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pr_debug("SWP{B} emulation: access caused memory abort!\n");
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arm64_notify_segfault(address);
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return 0;
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}
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/*
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* Only emulate SWP/SWPB executed in ARM state/User mode.
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* The kernel must be SWP free and SWP{B} does not exist in Thumb.
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*/
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static struct undef_hook swp_hooks[] = {
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{
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.instr_mask = 0x0fb00ff0,
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.instr_val = 0x01000090,
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.pstate_mask = COMPAT_PSR_MODE_MASK,
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.pstate_val = COMPAT_PSR_MODE_USR,
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.fn = swp_handler
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},
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{ }
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};
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static struct insn_emulation_ops swp_ops = {
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.name = "swp",
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.status = INSN_OBSOLETE,
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.hooks = swp_hooks,
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.set_hw_mode = NULL,
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};
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static int cp15barrier_handler(struct pt_regs *regs, u32 instr)
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{
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perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
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switch (aarch32_check_condition(instr, regs->pstate)) {
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case ARM_OPCODE_CONDTEST_PASS:
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break;
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case ARM_OPCODE_CONDTEST_FAIL:
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/* Condition failed - return to next instruction */
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goto ret;
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case ARM_OPCODE_CONDTEST_UNCOND:
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/* If unconditional encoding - not a barrier instruction */
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return -EFAULT;
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default:
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return -EINVAL;
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}
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switch (aarch32_insn_mcr_extract_crm(instr)) {
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case 10:
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/*
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* dmb - mcr p15, 0, Rt, c7, c10, 5
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* dsb - mcr p15, 0, Rt, c7, c10, 4
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*/
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if (aarch32_insn_mcr_extract_opc2(instr) == 5) {
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dmb(sy);
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trace_instruction_emulation(
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"mcr p15, 0, Rt, c7, c10, 5 ; dmb", regs->pc);
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} else {
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dsb(sy);
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trace_instruction_emulation(
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"mcr p15, 0, Rt, c7, c10, 4 ; dsb", regs->pc);
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}
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break;
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case 5:
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/*
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* isb - mcr p15, 0, Rt, c7, c5, 4
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*
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* Taking an exception or returning from one acts as an
|
|
* instruction barrier. So no explicit barrier needed here.
|
|
*/
|
|
trace_instruction_emulation(
|
|
"mcr p15, 0, Rt, c7, c5, 4 ; isb", regs->pc);
|
|
break;
|
|
}
|
|
|
|
ret:
|
|
pr_warn_ratelimited("\"%s\" (%ld) uses deprecated CP15 Barrier instruction at 0x%llx\n",
|
|
current->comm, (unsigned long)current->pid, regs->pc);
|
|
|
|
arm64_skip_faulting_instruction(regs, 4);
|
|
return 0;
|
|
}
|
|
|
|
static int cp15_barrier_set_hw_mode(bool enable)
|
|
{
|
|
if (enable)
|
|
config_sctlr_el1(0, SCTLR_EL1_CP15BEN);
|
|
else
|
|
config_sctlr_el1(SCTLR_EL1_CP15BEN, 0);
|
|
return 0;
|
|
}
|
|
|
|
static struct undef_hook cp15_barrier_hooks[] = {
|
|
{
|
|
.instr_mask = 0x0fff0fdf,
|
|
.instr_val = 0x0e070f9a,
|
|
.pstate_mask = COMPAT_PSR_MODE_MASK,
|
|
.pstate_val = COMPAT_PSR_MODE_USR,
|
|
.fn = cp15barrier_handler,
|
|
},
|
|
{
|
|
.instr_mask = 0x0fff0fff,
|
|
.instr_val = 0x0e070f95,
|
|
.pstate_mask = COMPAT_PSR_MODE_MASK,
|
|
.pstate_val = COMPAT_PSR_MODE_USR,
|
|
.fn = cp15barrier_handler,
|
|
},
|
|
{ }
|
|
};
|
|
|
|
static struct insn_emulation_ops cp15_barrier_ops = {
|
|
.name = "cp15_barrier",
|
|
.status = INSN_DEPRECATED,
|
|
.hooks = cp15_barrier_hooks,
|
|
.set_hw_mode = cp15_barrier_set_hw_mode,
|
|
};
|
|
|
|
static int setend_set_hw_mode(bool enable)
|
|
{
|
|
if (!cpu_supports_mixed_endian_el0())
|
|
return -EINVAL;
|
|
|
|
if (enable)
|
|
config_sctlr_el1(SCTLR_EL1_SED, 0);
|
|
else
|
|
config_sctlr_el1(0, SCTLR_EL1_SED);
|
|
return 0;
|
|
}
|
|
|
|
static int compat_setend_handler(struct pt_regs *regs, u32 big_endian)
|
|
{
|
|
char *insn;
|
|
|
|
perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
|
|
|
|
if (big_endian) {
|
|
insn = "setend be";
|
|
regs->pstate |= COMPAT_PSR_E_BIT;
|
|
} else {
|
|
insn = "setend le";
|
|
regs->pstate &= ~COMPAT_PSR_E_BIT;
|
|
}
|
|
|
|
trace_instruction_emulation(insn, regs->pc);
|
|
pr_warn_ratelimited("\"%s\" (%ld) uses deprecated setend instruction at 0x%llx\n",
|
|
current->comm, (unsigned long)current->pid, regs->pc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int a32_setend_handler(struct pt_regs *regs, u32 instr)
|
|
{
|
|
int rc = compat_setend_handler(regs, (instr >> 9) & 1);
|
|
arm64_skip_faulting_instruction(regs, 4);
|
|
return rc;
|
|
}
|
|
|
|
static int t16_setend_handler(struct pt_regs *regs, u32 instr)
|
|
{
|
|
int rc = compat_setend_handler(regs, (instr >> 3) & 1);
|
|
arm64_skip_faulting_instruction(regs, 2);
|
|
return rc;
|
|
}
|
|
|
|
static struct undef_hook setend_hooks[] = {
|
|
{
|
|
.instr_mask = 0xfffffdff,
|
|
.instr_val = 0xf1010000,
|
|
.pstate_mask = COMPAT_PSR_MODE_MASK,
|
|
.pstate_val = COMPAT_PSR_MODE_USR,
|
|
.fn = a32_setend_handler,
|
|
},
|
|
{
|
|
/* Thumb mode */
|
|
.instr_mask = 0x0000fff7,
|
|
.instr_val = 0x0000b650,
|
|
.pstate_mask = (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_MASK),
|
|
.pstate_val = (COMPAT_PSR_T_BIT | COMPAT_PSR_MODE_USR),
|
|
.fn = t16_setend_handler,
|
|
},
|
|
{}
|
|
};
|
|
|
|
static struct insn_emulation_ops setend_ops = {
|
|
.name = "setend",
|
|
.status = INSN_DEPRECATED,
|
|
.hooks = setend_hooks,
|
|
.set_hw_mode = setend_set_hw_mode,
|
|
};
|
|
|
|
/*
|
|
* Invoked as late_initcall, since not needed before init spawned.
|
|
*/
|
|
static int __init armv8_deprecated_init(void)
|
|
{
|
|
if (IS_ENABLED(CONFIG_SWP_EMULATION))
|
|
register_insn_emulation(&swp_ops);
|
|
|
|
if (IS_ENABLED(CONFIG_CP15_BARRIER_EMULATION))
|
|
register_insn_emulation(&cp15_barrier_ops);
|
|
|
|
if (IS_ENABLED(CONFIG_SETEND_EMULATION)) {
|
|
if(system_supports_mixed_endian_el0())
|
|
register_insn_emulation(&setend_ops);
|
|
else
|
|
pr_info("setend instruction emulation is not supported on this system\n");
|
|
}
|
|
|
|
cpuhp_setup_state_nocalls(CPUHP_AP_ARM64_ISNDEP_STARTING,
|
|
"arm64/isndep:starting",
|
|
run_all_insn_set_hw_mode, NULL);
|
|
register_insn_emulation_sysctl();
|
|
|
|
return 0;
|
|
}
|
|
|
|
core_initcall(armv8_deprecated_init);
|