6b88a32c7a
With ARM64_SW_TTBR0_PAN enabled, the exception entry code checks the active ASID to decide whether user access was enabled (non-zero ASID) when the exception was taken. On return from exception, if user access was previously disabled, it re-instates TTBR0_EL1 from the per-thread saved value (updated in switch_mm() or efi_set_pgd()). Commit7655abb953("arm64: mm: Move ASID from TTBR0 to TTBR1") makes a TTBR0_EL1 + ASID switching non-atomic. Subsequently, commit27a921e757("arm64: mm: Fix and re-enable ARM64_SW_TTBR0_PAN") changes the __uaccess_ttbr0_disable() function and asm macro to first write the reserved TTBR0_EL1 followed by the ASID=0 update in TTBR1_EL1. If an exception occurs between these two, the exception return code will re-instate a valid TTBR0_EL1. Similar scenario can happen in cpu_switch_mm() between setting the reserved TTBR0_EL1 and the ASID update in cpu_do_switch_mm(). This patch reverts the entry.S check for ASID == 0 to TTBR0_EL1 and disables the interrupts around the TTBR0_EL1 and ASID switching code in __uaccess_ttbr0_disable(). It also ensures that, when returning from the EFI runtime services, efi_set_pgd() doesn't leave a non-zero ASID in TTBR1_EL1 by using uaccess_ttbr0_{enable,disable}. The accesses to current_thread_info()->ttbr0 are updated to use READ_ONCE/WRITE_ONCE. As a safety measure, __uaccess_ttbr0_enable() always masks out any existing non-zero ASID TTBR1_EL1 before writing in the new ASID. Fixes:27a921e757("arm64: mm: Fix and re-enable ARM64_SW_TTBR0_PAN") Acked-by: Will Deacon <will.deacon@arm.com> Reported-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: James Morse <james.morse@arm.com> Tested-by: James Morse <james.morse@arm.com> Co-developed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
80 lines
1.8 KiB
ArmAsm
80 lines
1.8 KiB
ArmAsm
/*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/linkage.h>
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#include <asm/cache.h>
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#include <asm/asm-uaccess.h>
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/*
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* Copy from user space to a kernel buffer (alignment handled by the hardware)
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*
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* Parameters:
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* x0 - to
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* x1 - from
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* x2 - n
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* Returns:
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* x0 - bytes not copied
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*/
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.macro ldrb1 ptr, regB, val
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uao_user_alternative 9998f, ldrb, ldtrb, \ptr, \regB, \val
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.endm
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.macro strb1 ptr, regB, val
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strb \ptr, [\regB], \val
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.endm
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.macro ldrh1 ptr, regB, val
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uao_user_alternative 9998f, ldrh, ldtrh, \ptr, \regB, \val
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.endm
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.macro strh1 ptr, regB, val
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strh \ptr, [\regB], \val
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.endm
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.macro ldr1 ptr, regB, val
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uao_user_alternative 9998f, ldr, ldtr, \ptr, \regB, \val
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.endm
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.macro str1 ptr, regB, val
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str \ptr, [\regB], \val
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.endm
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.macro ldp1 ptr, regB, regC, val
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uao_ldp 9998f, \ptr, \regB, \regC, \val
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.endm
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.macro stp1 ptr, regB, regC, val
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stp \ptr, \regB, [\regC], \val
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.endm
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end .req x5
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ENTRY(__arch_copy_from_user)
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uaccess_enable_not_uao x3, x4, x5
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add end, x0, x2
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#include "copy_template.S"
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uaccess_disable_not_uao x3, x4
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mov x0, #0 // Nothing to copy
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ret
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ENDPROC(__arch_copy_from_user)
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.section .fixup,"ax"
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.align 2
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9998: sub x0, end, dst // bytes not copied
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ret
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.previous
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