25d8b92e0a
In this sequence the 'move' is assumed in the delay slot of the 'beq',
but head.S is in reorder mode and the former gets pushed one 'nop'
farther by the assembler.
The corrected behavior made booting with an UHI supplied dtb erratic.
Fixes: 15f37e1588 ("MIPS: store the appended dtb address in a variable")
Signed-off-by: Karl Beldan <karl.beldan+oss@gmail.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: Jonas Gorski <jogo@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/16614/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
175 lines
4 KiB
ArmAsm
175 lines
4 KiB
ArmAsm
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994, 1995 Waldorf Electronics
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* Written by Ralf Baechle and Andreas Busse
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* Copyright (C) 1994 - 99, 2003, 06 Ralf Baechle
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* Copyright (C) 1996 Paul M. Antoine
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* Modified for DECStation and hence R3000 support by Paul M. Antoine
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* Further modifications by David S. Miller and Harald Koerfgen
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* Copyright (C) 1999 Silicon Graphics, Inc.
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* Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
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*/
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#include <linux/init.h>
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#include <linux/threads.h>
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#include <asm/addrspace.h>
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#include <asm/asm.h>
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#include <asm/asmmacro.h>
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#include <asm/irqflags.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/stackframe.h>
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#include <kernel-entry-init.h>
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/*
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* For the moment disable interrupts, mark the kernel mode and
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* set ST0_KX so that the CPU does not spit fire when using
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* 64-bit addresses. A full initialization of the CPU's status
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* register is done later in per_cpu_trap_init().
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*/
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.macro setup_c0_status set clr
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.set push
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mfc0 t0, CP0_STATUS
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or t0, ST0_CU0|\set|0x1f|\clr
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xor t0, 0x1f|\clr
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mtc0 t0, CP0_STATUS
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.set noreorder
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sll zero,3 # ehb
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.set pop
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.endm
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.macro setup_c0_status_pri
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#ifdef CONFIG_64BIT
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setup_c0_status ST0_KX 0
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#else
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setup_c0_status 0 0
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#endif
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.endm
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.macro setup_c0_status_sec
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#ifdef CONFIG_64BIT
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setup_c0_status ST0_KX ST0_BEV
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#else
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setup_c0_status 0 ST0_BEV
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#endif
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.endm
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#ifndef CONFIG_NO_EXCEPT_FILL
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/*
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* Reserved space for exception handlers.
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* Necessary for machines which link their kernels at KSEG0.
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*/
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.fill 0x400
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#endif
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EXPORT(_stext)
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#ifdef CONFIG_BOOT_RAW
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/*
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* Give us a fighting chance of running if execution beings at the
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* kernel load address. This is needed because this platform does
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* not have a ELF loader yet.
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*/
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FEXPORT(__kernel_entry)
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j kernel_entry
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#endif
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__REF
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NESTED(kernel_entry, 16, sp) # kernel entry point
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kernel_entry_setup # cpu specific setup
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setup_c0_status_pri
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/* We might not get launched at the address the kernel is linked to,
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so we jump there. */
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PTR_LA t0, 0f
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jr t0
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0:
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#ifdef CONFIG_USE_OF
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#ifdef CONFIG_MIPS_RAW_APPENDED_DTB
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PTR_LA t2, __appended_dtb
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#ifdef CONFIG_CPU_BIG_ENDIAN
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li t1, 0xd00dfeed
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#else
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li t1, 0xedfe0dd0
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#endif
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lw t0, (t2)
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beq t0, t1, dtb_found
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#endif
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li t1, -2
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move t2, a1
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beq a0, t1, dtb_found
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li t2, 0
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dtb_found:
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#endif
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PTR_LA t0, __bss_start # clear .bss
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LONG_S zero, (t0)
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PTR_LA t1, __bss_stop - LONGSIZE
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1:
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PTR_ADDIU t0, LONGSIZE
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LONG_S zero, (t0)
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bne t0, t1, 1b
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LONG_S a0, fw_arg0 # firmware arguments
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LONG_S a1, fw_arg1
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LONG_S a2, fw_arg2
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LONG_S a3, fw_arg3
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#ifdef CONFIG_USE_OF
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LONG_S t2, fw_passed_dtb
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#endif
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MTC0 zero, CP0_CONTEXT # clear context register
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PTR_LA $28, init_thread_union
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/* Set the SP after an empty pt_regs. */
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PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE
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PTR_ADDU sp, $28
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back_to_back_c0_hazard
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set_saved_sp sp, t0, t1
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PTR_SUBU sp, 4 * SZREG # init stack pointer
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#ifdef CONFIG_RELOCATABLE
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/* Copy kernel and apply the relocations */
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jal relocate_kernel
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/* Repoint the sp into the new kernel image */
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PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE
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PTR_ADDU sp, $28
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set_saved_sp sp, t0, t1
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PTR_SUBU sp, 4 * SZREG # init stack pointer
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/*
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* relocate_kernel returns the entry point either
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* in the relocated kernel or the original if for
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* some reason relocation failed - jump there now
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* with instruction hazard barrier because of the
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* newly sync'd icache.
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*/
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jr.hb v0
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#else
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j start_kernel
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#endif
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END(kernel_entry)
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#ifdef CONFIG_SMP
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/*
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* SMP slave cpus entry point. Board specific code for bootstrap calls this
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* function after setting up the stack and gp registers.
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*/
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NESTED(smp_bootstrap, 16, sp)
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smp_slave_setup
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setup_c0_status_sec
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j start_secondary
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END(smp_bootstrap)
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#endif /* CONFIG_SMP */
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