![Arbel Moshe](/assets/img/avatar_default.png)
VMware exposes the following Pseudo PMCs: 0x10000: Physical host TSC 0x10001: Elapsed real time in ns 0x10002: Elapsed apparent time in ns For more info refer to: https://www.vmware.com/files/pdf/techpaper/Timekeeping-In-VirtualMachines.pdf VMware allows access to these Pseduo-PMCs even when read via RDPMC in Ring3 and CR4.PCE=0. Therefore, commit modifies x86 emulator to allow access to these PMCs in this situation. In addition, emulation of these PMCs were added to kvm_pmu_rdpmc(). Signed-off-by: Arbel Moshe <arbel.moshe@oracle.com> Signed-off-by: Liran Alon <liran.alon@oracle.com> Reviewed-by: Radim Krčmář <rkrcmar@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
354 lines
9.5 KiB
C
354 lines
9.5 KiB
C
/*
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* Kernel-based Virtual Machine -- Performance Monitoring Unit support
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*
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* Copyright 2015 Red Hat, Inc. and/or its affiliates.
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*
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* Authors:
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* Avi Kivity <avi@redhat.com>
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* Gleb Natapov <gleb@redhat.com>
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* Wei Huang <wei@redhat.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See
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* the COPYING file in the top-level directory.
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*
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*/
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#include <linux/types.h>
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#include <linux/kvm_host.h>
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#include <linux/perf_event.h>
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#include <asm/perf_event.h>
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#include "x86.h"
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#include "cpuid.h"
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#include "lapic.h"
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#include "pmu.h"
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/* NOTE:
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* - Each perf counter is defined as "struct kvm_pmc";
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* - There are two types of perf counters: general purpose (gp) and fixed.
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* gp counters are stored in gp_counters[] and fixed counters are stored
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* in fixed_counters[] respectively. Both of them are part of "struct
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* kvm_pmu";
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* - pmu.c understands the difference between gp counters and fixed counters.
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* However AMD doesn't support fixed-counters;
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* - There are three types of index to access perf counters (PMC):
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* 1. MSR (named msr): For example Intel has MSR_IA32_PERFCTRn and AMD
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* has MSR_K7_PERFCTRn.
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* 2. MSR Index (named idx): This normally is used by RDPMC instruction.
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* For instance AMD RDPMC instruction uses 0000_0003h in ECX to access
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* C001_0007h (MSR_K7_PERCTR3). Intel has a similar mechanism, except
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* that it also supports fixed counters. idx can be used to as index to
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* gp and fixed counters.
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* 3. Global PMC Index (named pmc): pmc is an index specific to PMU
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* code. Each pmc, stored in kvm_pmc.idx field, is unique across
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* all perf counters (both gp and fixed). The mapping relationship
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* between pmc and perf counters is as the following:
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* * Intel: [0 .. INTEL_PMC_MAX_GENERIC-1] <=> gp counters
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* [INTEL_PMC_IDX_FIXED .. INTEL_PMC_IDX_FIXED + 2] <=> fixed
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* * AMD: [0 .. AMD64_NUM_COUNTERS-1] <=> gp counters
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*/
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static void kvm_pmi_trigger_fn(struct irq_work *irq_work)
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{
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struct kvm_pmu *pmu = container_of(irq_work, struct kvm_pmu, irq_work);
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struct kvm_vcpu *vcpu = pmu_to_vcpu(pmu);
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kvm_pmu_deliver_pmi(vcpu);
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}
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static void kvm_perf_overflow(struct perf_event *perf_event,
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struct perf_sample_data *data,
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struct pt_regs *regs)
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{
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struct kvm_pmc *pmc = perf_event->overflow_handler_context;
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struct kvm_pmu *pmu = pmc_to_pmu(pmc);
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if (!test_and_set_bit(pmc->idx,
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(unsigned long *)&pmu->reprogram_pmi)) {
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__set_bit(pmc->idx, (unsigned long *)&pmu->global_status);
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kvm_make_request(KVM_REQ_PMU, pmc->vcpu);
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}
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}
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static void kvm_perf_overflow_intr(struct perf_event *perf_event,
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struct perf_sample_data *data,
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struct pt_regs *regs)
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{
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struct kvm_pmc *pmc = perf_event->overflow_handler_context;
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struct kvm_pmu *pmu = pmc_to_pmu(pmc);
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if (!test_and_set_bit(pmc->idx,
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(unsigned long *)&pmu->reprogram_pmi)) {
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__set_bit(pmc->idx, (unsigned long *)&pmu->global_status);
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kvm_make_request(KVM_REQ_PMU, pmc->vcpu);
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/*
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* Inject PMI. If vcpu was in a guest mode during NMI PMI
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* can be ejected on a guest mode re-entry. Otherwise we can't
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* be sure that vcpu wasn't executing hlt instruction at the
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* time of vmexit and is not going to re-enter guest mode until
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* woken up. So we should wake it, but this is impossible from
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* NMI context. Do it from irq work instead.
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*/
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if (!kvm_is_in_guest())
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irq_work_queue(&pmc_to_pmu(pmc)->irq_work);
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else
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kvm_make_request(KVM_REQ_PMI, pmc->vcpu);
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}
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}
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static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type,
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unsigned config, bool exclude_user,
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bool exclude_kernel, bool intr,
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bool in_tx, bool in_tx_cp)
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{
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struct perf_event *event;
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struct perf_event_attr attr = {
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.type = type,
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.size = sizeof(attr),
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.pinned = true,
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.exclude_idle = true,
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.exclude_host = 1,
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.exclude_user = exclude_user,
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.exclude_kernel = exclude_kernel,
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.config = config,
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};
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attr.sample_period = (-pmc->counter) & pmc_bitmask(pmc);
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if (in_tx)
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attr.config |= HSW_IN_TX;
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if (in_tx_cp) {
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/*
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* HSW_IN_TX_CHECKPOINTED is not supported with nonzero
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* period. Just clear the sample period so at least
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* allocating the counter doesn't fail.
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*/
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attr.sample_period = 0;
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attr.config |= HSW_IN_TX_CHECKPOINTED;
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}
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event = perf_event_create_kernel_counter(&attr, -1, current,
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intr ? kvm_perf_overflow_intr :
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kvm_perf_overflow, pmc);
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if (IS_ERR(event)) {
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printk_once("kvm_pmu: event creation failed %ld\n",
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PTR_ERR(event));
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return;
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}
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pmc->perf_event = event;
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clear_bit(pmc->idx, (unsigned long*)&pmc_to_pmu(pmc)->reprogram_pmi);
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}
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void reprogram_gp_counter(struct kvm_pmc *pmc, u64 eventsel)
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{
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unsigned config, type = PERF_TYPE_RAW;
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u8 event_select, unit_mask;
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if (eventsel & ARCH_PERFMON_EVENTSEL_PIN_CONTROL)
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printk_once("kvm pmu: pin control bit is ignored\n");
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pmc->eventsel = eventsel;
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pmc_stop_counter(pmc);
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if (!(eventsel & ARCH_PERFMON_EVENTSEL_ENABLE) || !pmc_is_enabled(pmc))
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return;
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event_select = eventsel & ARCH_PERFMON_EVENTSEL_EVENT;
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unit_mask = (eventsel & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
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if (!(eventsel & (ARCH_PERFMON_EVENTSEL_EDGE |
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ARCH_PERFMON_EVENTSEL_INV |
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ARCH_PERFMON_EVENTSEL_CMASK |
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HSW_IN_TX |
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HSW_IN_TX_CHECKPOINTED))) {
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config = kvm_x86_ops->pmu_ops->find_arch_event(pmc_to_pmu(pmc),
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event_select,
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unit_mask);
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if (config != PERF_COUNT_HW_MAX)
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type = PERF_TYPE_HARDWARE;
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}
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if (type == PERF_TYPE_RAW)
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config = eventsel & X86_RAW_EVENT_MASK;
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pmc_reprogram_counter(pmc, type, config,
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!(eventsel & ARCH_PERFMON_EVENTSEL_USR),
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!(eventsel & ARCH_PERFMON_EVENTSEL_OS),
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eventsel & ARCH_PERFMON_EVENTSEL_INT,
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(eventsel & HSW_IN_TX),
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(eventsel & HSW_IN_TX_CHECKPOINTED));
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}
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EXPORT_SYMBOL_GPL(reprogram_gp_counter);
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void reprogram_fixed_counter(struct kvm_pmc *pmc, u8 ctrl, int idx)
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{
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unsigned en_field = ctrl & 0x3;
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bool pmi = ctrl & 0x8;
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pmc_stop_counter(pmc);
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if (!en_field || !pmc_is_enabled(pmc))
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return;
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pmc_reprogram_counter(pmc, PERF_TYPE_HARDWARE,
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kvm_x86_ops->pmu_ops->find_fixed_event(idx),
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!(en_field & 0x2), /* exclude user */
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!(en_field & 0x1), /* exclude kernel */
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pmi, false, false);
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}
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EXPORT_SYMBOL_GPL(reprogram_fixed_counter);
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void reprogram_counter(struct kvm_pmu *pmu, int pmc_idx)
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{
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struct kvm_pmc *pmc = kvm_x86_ops->pmu_ops->pmc_idx_to_pmc(pmu, pmc_idx);
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if (!pmc)
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return;
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if (pmc_is_gp(pmc))
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reprogram_gp_counter(pmc, pmc->eventsel);
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else {
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int idx = pmc_idx - INTEL_PMC_IDX_FIXED;
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u8 ctrl = fixed_ctrl_field(pmu->fixed_ctr_ctrl, idx);
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reprogram_fixed_counter(pmc, ctrl, idx);
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}
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}
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EXPORT_SYMBOL_GPL(reprogram_counter);
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void kvm_pmu_handle_event(struct kvm_vcpu *vcpu)
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{
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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u64 bitmask;
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int bit;
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bitmask = pmu->reprogram_pmi;
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for_each_set_bit(bit, (unsigned long *)&bitmask, X86_PMC_IDX_MAX) {
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struct kvm_pmc *pmc = kvm_x86_ops->pmu_ops->pmc_idx_to_pmc(pmu, bit);
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if (unlikely(!pmc || !pmc->perf_event)) {
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clear_bit(bit, (unsigned long *)&pmu->reprogram_pmi);
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continue;
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}
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reprogram_counter(pmu, bit);
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}
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}
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/* check if idx is a valid index to access PMU */
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int kvm_pmu_is_valid_msr_idx(struct kvm_vcpu *vcpu, unsigned idx)
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{
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return kvm_x86_ops->pmu_ops->is_valid_msr_idx(vcpu, idx);
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}
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bool is_vmware_backdoor_pmc(u32 pmc_idx)
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{
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switch (pmc_idx) {
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case VMWARE_BACKDOOR_PMC_HOST_TSC:
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case VMWARE_BACKDOOR_PMC_REAL_TIME:
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case VMWARE_BACKDOOR_PMC_APPARENT_TIME:
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return true;
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}
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return false;
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}
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static int kvm_pmu_rdpmc_vmware(struct kvm_vcpu *vcpu, unsigned idx, u64 *data)
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{
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u64 ctr_val;
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switch (idx) {
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case VMWARE_BACKDOOR_PMC_HOST_TSC:
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ctr_val = rdtsc();
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break;
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case VMWARE_BACKDOOR_PMC_REAL_TIME:
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ctr_val = ktime_get_boot_ns();
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break;
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case VMWARE_BACKDOOR_PMC_APPARENT_TIME:
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ctr_val = ktime_get_boot_ns() +
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vcpu->kvm->arch.kvmclock_offset;
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break;
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default:
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return 1;
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}
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*data = ctr_val;
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return 0;
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}
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int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned idx, u64 *data)
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{
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bool fast_mode = idx & (1u << 31);
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struct kvm_pmc *pmc;
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u64 ctr_val;
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if (is_vmware_backdoor_pmc(idx))
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return kvm_pmu_rdpmc_vmware(vcpu, idx, data);
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pmc = kvm_x86_ops->pmu_ops->msr_idx_to_pmc(vcpu, idx);
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if (!pmc)
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return 1;
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ctr_val = pmc_read_counter(pmc);
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if (fast_mode)
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ctr_val = (u32)ctr_val;
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*data = ctr_val;
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return 0;
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}
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void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu)
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{
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if (lapic_in_kernel(vcpu))
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kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTPC);
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}
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bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
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{
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return kvm_x86_ops->pmu_ops->is_valid_msr(vcpu, msr);
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}
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int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
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{
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return kvm_x86_ops->pmu_ops->get_msr(vcpu, msr, data);
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}
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int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
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{
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return kvm_x86_ops->pmu_ops->set_msr(vcpu, msr_info);
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}
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/* refresh PMU settings. This function generally is called when underlying
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* settings are changed (such as changes of PMU CPUID by guest VMs), which
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* should rarely happen.
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*/
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void kvm_pmu_refresh(struct kvm_vcpu *vcpu)
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{
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kvm_x86_ops->pmu_ops->refresh(vcpu);
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}
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void kvm_pmu_reset(struct kvm_vcpu *vcpu)
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{
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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irq_work_sync(&pmu->irq_work);
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kvm_x86_ops->pmu_ops->reset(vcpu);
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}
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void kvm_pmu_init(struct kvm_vcpu *vcpu)
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{
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struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
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memset(pmu, 0, sizeof(*pmu));
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kvm_x86_ops->pmu_ops->init(vcpu);
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init_irq_work(&pmu->irq_work, kvm_pmi_trigger_fn);
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kvm_pmu_refresh(vcpu);
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}
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void kvm_pmu_destroy(struct kvm_vcpu *vcpu)
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{
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kvm_pmu_reset(vcpu);
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}
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