![Kirill A. Shutemov](/assets/img/avatar_default.png)
This patch converts the of CONFIG_X86_5LEVEL check to runtime checks for p4d folding. Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Arjan van de Ven <arjan@linux.intel.com> Cc: Borislav Petkov <bp@suse.de> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mm@kvack.org Link: http://lkml.kernel.org/r/20180214182542.69302-9-kirill.shutemov@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
220 lines
6.3 KiB
C
220 lines
6.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* This file implements KASLR memory randomization for x86_64. It randomizes
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* the virtual address space of kernel memory regions (physical memory
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* mapping, vmalloc & vmemmap) for x86_64. This security feature mitigates
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* exploits relying on predictable kernel addresses.
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*
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* Entropy is generated using the KASLR early boot functions now shared in
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* the lib directory (originally written by Kees Cook). Randomization is
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* done on PGD & P4D/PUD page table levels to increase possible addresses.
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* The physical memory mapping code was adapted to support P4D/PUD level
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* virtual addresses. This implementation on the best configuration provides
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* 30,000 possible virtual addresses in average for each memory region.
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* An additional low memory page is used to ensure each CPU can start with
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* a PGD aligned virtual address (for realmode).
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*
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* The order of each memory region is not changed. The feature looks at
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* the available space for the regions based on different configuration
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* options and randomizes the base and space between each. The size of the
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* physical memory mapping is the available physical memory.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/random.h>
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#include <asm/pgalloc.h>
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#include <asm/pgtable.h>
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#include <asm/setup.h>
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#include <asm/kaslr.h>
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#include "mm_internal.h"
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#define TB_SHIFT 40
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/*
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* The end address could depend on more configuration options to make the
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* highest amount of space for randomization available, but that's too hard
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* to keep straight and caused issues already.
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*/
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static const unsigned long vaddr_end = CPU_ENTRY_AREA_BASE;
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/*
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* Memory regions randomized by KASLR (except modules that use a separate logic
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* earlier during boot). The list is ordered based on virtual addresses. This
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* order is kept after randomization.
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*/
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static __initdata struct kaslr_memory_region {
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unsigned long *base;
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unsigned long size_tb;
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} kaslr_regions[] = {
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{ &page_offset_base, 0 },
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{ &vmalloc_base, 0 },
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{ &vmemmap_base, 1 },
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};
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/* Get size in bytes used by the memory region */
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static inline unsigned long get_padding(struct kaslr_memory_region *region)
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{
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return (region->size_tb << TB_SHIFT);
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}
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/*
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* Apply no randomization if KASLR was disabled at boot or if KASAN
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* is enabled. KASAN shadow mappings rely on regions being PGD aligned.
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*/
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static inline bool kaslr_memory_enabled(void)
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{
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return kaslr_enabled() && !IS_ENABLED(CONFIG_KASAN);
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}
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/* Initialize base and padding for each memory region randomized with KASLR */
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void __init kernel_randomize_memory(void)
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{
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size_t i;
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unsigned long vaddr_start, vaddr;
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unsigned long rand, memory_tb;
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struct rnd_state rand_state;
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unsigned long remain_entropy;
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vaddr_start = pgtable_l5_enabled ? __PAGE_OFFSET_BASE_L5 : __PAGE_OFFSET_BASE_L4;
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vaddr = vaddr_start;
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/*
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* These BUILD_BUG_ON checks ensure the memory layout is consistent
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* with the vaddr_start/vaddr_end variables. These checks are very
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* limited....
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*/
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BUILD_BUG_ON(vaddr_start >= vaddr_end);
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BUILD_BUG_ON(vaddr_end != CPU_ENTRY_AREA_BASE);
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BUILD_BUG_ON(vaddr_end > __START_KERNEL_map);
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if (!kaslr_memory_enabled())
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return;
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kaslr_regions[0].size_tb = 1 << (__PHYSICAL_MASK_SHIFT - TB_SHIFT);
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kaslr_regions[1].size_tb = VMALLOC_SIZE_TB;
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/*
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* Update Physical memory mapping to available and
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* add padding if needed (especially for memory hotplug support).
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*/
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BUG_ON(kaslr_regions[0].base != &page_offset_base);
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memory_tb = DIV_ROUND_UP(max_pfn << PAGE_SHIFT, 1UL << TB_SHIFT) +
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CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING;
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/* Adapt phyiscal memory region size based on available memory */
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if (memory_tb < kaslr_regions[0].size_tb)
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kaslr_regions[0].size_tb = memory_tb;
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/* Calculate entropy available between regions */
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remain_entropy = vaddr_end - vaddr_start;
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for (i = 0; i < ARRAY_SIZE(kaslr_regions); i++)
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remain_entropy -= get_padding(&kaslr_regions[i]);
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prandom_seed_state(&rand_state, kaslr_get_random_long("Memory"));
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for (i = 0; i < ARRAY_SIZE(kaslr_regions); i++) {
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unsigned long entropy;
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/*
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* Select a random virtual address using the extra entropy
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* available.
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*/
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entropy = remain_entropy / (ARRAY_SIZE(kaslr_regions) - i);
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prandom_bytes_state(&rand_state, &rand, sizeof(rand));
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if (pgtable_l5_enabled)
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entropy = (rand % (entropy + 1)) & P4D_MASK;
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else
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entropy = (rand % (entropy + 1)) & PUD_MASK;
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vaddr += entropy;
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*kaslr_regions[i].base = vaddr;
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/*
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* Jump the region and add a minimum padding based on
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* randomization alignment.
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*/
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vaddr += get_padding(&kaslr_regions[i]);
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if (pgtable_l5_enabled)
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vaddr = round_up(vaddr + 1, P4D_SIZE);
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else
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vaddr = round_up(vaddr + 1, PUD_SIZE);
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remain_entropy -= entropy;
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}
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}
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static void __meminit init_trampoline_pud(void)
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{
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unsigned long paddr, paddr_next;
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pgd_t *pgd;
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pud_t *pud_page, *pud_page_tramp;
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int i;
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pud_page_tramp = alloc_low_page();
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paddr = 0;
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pgd = pgd_offset_k((unsigned long)__va(paddr));
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pud_page = (pud_t *) pgd_page_vaddr(*pgd);
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for (i = pud_index(paddr); i < PTRS_PER_PUD; i++, paddr = paddr_next) {
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pud_t *pud, *pud_tramp;
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unsigned long vaddr = (unsigned long)__va(paddr);
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pud_tramp = pud_page_tramp + pud_index(paddr);
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pud = pud_page + pud_index(vaddr);
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paddr_next = (paddr & PUD_MASK) + PUD_SIZE;
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*pud_tramp = *pud;
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}
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set_pgd(&trampoline_pgd_entry,
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__pgd(_KERNPG_TABLE | __pa(pud_page_tramp)));
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}
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static void __meminit init_trampoline_p4d(void)
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{
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unsigned long paddr, paddr_next;
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pgd_t *pgd;
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p4d_t *p4d_page, *p4d_page_tramp;
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int i;
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p4d_page_tramp = alloc_low_page();
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paddr = 0;
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pgd = pgd_offset_k((unsigned long)__va(paddr));
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p4d_page = (p4d_t *) pgd_page_vaddr(*pgd);
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for (i = p4d_index(paddr); i < PTRS_PER_P4D; i++, paddr = paddr_next) {
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p4d_t *p4d, *p4d_tramp;
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unsigned long vaddr = (unsigned long)__va(paddr);
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p4d_tramp = p4d_page_tramp + p4d_index(paddr);
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p4d = p4d_page + p4d_index(vaddr);
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paddr_next = (paddr & P4D_MASK) + P4D_SIZE;
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*p4d_tramp = *p4d;
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}
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set_pgd(&trampoline_pgd_entry,
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__pgd(_KERNPG_TABLE | __pa(p4d_page_tramp)));
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}
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/*
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* Create PGD aligned trampoline table to allow real mode initialization
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* of additional CPUs. Consume only 1 low memory page.
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*/
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void __meminit init_trampoline(void)
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{
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if (!kaslr_memory_enabled()) {
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init_trampoline_default();
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return;
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}
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if (pgtable_l5_enabled)
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init_trampoline_p4d();
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else
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init_trampoline_pud();
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}
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