![David Daney](/assets/img/avatar_default.png)
The Octeon SOC has two types of Ethernet ports, each type with its own driver. However, the PHYs for all the ports are controlled by a common MDIO bus. Because the mdio driver is not associated with a particular driver, but is instead a system level resource, we create s stand-alone driver for it. As for the driver, we put the register definitions in arch/mips/include/asm/octeon where most of the other Octeon register definitions live. This is a platform driver with the platform device for "mdio-octeon" being registered in the platform startup code. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
181 lines
4 KiB
C
181 lines
4 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2009 Cavium Networks
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/phy.h>
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-smix-defs.h>
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#define DRV_VERSION "1.0"
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#define DRV_DESCRIPTION "Cavium Networks Octeon SMI/MDIO driver"
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struct octeon_mdiobus {
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struct mii_bus *mii_bus;
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int unit;
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int phy_irq[PHY_MAX_ADDR];
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};
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static int octeon_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum)
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{
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struct octeon_mdiobus *p = bus->priv;
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union cvmx_smix_cmd smi_cmd;
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union cvmx_smix_rd_dat smi_rd;
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int timeout = 1000;
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smi_cmd.u64 = 0;
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smi_cmd.s.phy_op = 1; /* MDIO_CLAUSE_22_READ */
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smi_cmd.s.phy_adr = phy_id;
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smi_cmd.s.reg_adr = regnum;
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cvmx_write_csr(CVMX_SMIX_CMD(p->unit), smi_cmd.u64);
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do {
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/*
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* Wait 1000 clocks so we don't saturate the RSL bus
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* doing reads.
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*/
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cvmx_wait(1000);
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smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(p->unit));
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} while (smi_rd.s.pending && --timeout);
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if (smi_rd.s.val)
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return smi_rd.s.dat;
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else
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return -EIO;
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}
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static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id,
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int regnum, u16 val)
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{
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struct octeon_mdiobus *p = bus->priv;
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union cvmx_smix_cmd smi_cmd;
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union cvmx_smix_wr_dat smi_wr;
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int timeout = 1000;
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smi_wr.u64 = 0;
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smi_wr.s.dat = val;
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cvmx_write_csr(CVMX_SMIX_WR_DAT(p->unit), smi_wr.u64);
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smi_cmd.u64 = 0;
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smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_22_WRITE */
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smi_cmd.s.phy_adr = phy_id;
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smi_cmd.s.reg_adr = regnum;
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cvmx_write_csr(CVMX_SMIX_CMD(p->unit), smi_cmd.u64);
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do {
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/*
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* Wait 1000 clocks so we don't saturate the RSL bus
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* doing reads.
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*/
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cvmx_wait(1000);
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smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(p->unit));
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} while (smi_wr.s.pending && --timeout);
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if (timeout <= 0)
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return -EIO;
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return 0;
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}
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static int __init octeon_mdiobus_probe(struct platform_device *pdev)
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{
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struct octeon_mdiobus *bus;
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int i;
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int err = -ENOENT;
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bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
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if (!bus)
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return -ENOMEM;
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/* The platform_device id is our unit number. */
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bus->unit = pdev->id;
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bus->mii_bus = mdiobus_alloc();
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if (!bus->mii_bus)
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goto err;
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/*
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* Standard Octeon evaluation boards don't support phy
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* interrupts, we need to poll.
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*/
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for (i = 0; i < PHY_MAX_ADDR; i++)
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bus->phy_irq[i] = PHY_POLL;
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bus->mii_bus->priv = bus;
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bus->mii_bus->irq = bus->phy_irq;
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bus->mii_bus->name = "mdio-octeon";
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snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%x", bus->unit);
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bus->mii_bus->parent = &pdev->dev;
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bus->mii_bus->read = octeon_mdiobus_read;
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bus->mii_bus->write = octeon_mdiobus_write;
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dev_set_drvdata(&pdev->dev, bus);
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err = mdiobus_register(bus->mii_bus);
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if (err)
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goto err_register;
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dev_info(&pdev->dev, "Version " DRV_VERSION "\n");
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return 0;
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err_register:
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mdiobus_free(bus->mii_bus);
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err:
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devm_kfree(&pdev->dev, bus);
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return err;
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}
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static int __exit octeon_mdiobus_remove(struct platform_device *pdev)
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{
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struct octeon_mdiobus *bus;
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bus = dev_get_drvdata(&pdev->dev);
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mdiobus_unregister(bus->mii_bus);
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mdiobus_free(bus->mii_bus);
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return 0;
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}
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static struct platform_driver octeon_mdiobus_driver = {
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.driver = {
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.name = "mdio-octeon",
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.owner = THIS_MODULE,
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},
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.probe = octeon_mdiobus_probe,
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.remove = __exit_p(octeon_mdiobus_remove),
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};
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void octeon_mdiobus_force_mod_depencency(void)
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{
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/* Let ethernet drivers force us to be loaded. */
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}
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EXPORT_SYMBOL(octeon_mdiobus_force_mod_depencency);
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static int __init octeon_mdiobus_mod_init(void)
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{
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return platform_driver_register(&octeon_mdiobus_driver);
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}
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static void __exit octeon_mdiobus_mod_exit(void)
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{
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platform_driver_unregister(&octeon_mdiobus_driver);
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}
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module_init(octeon_mdiobus_mod_init);
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module_exit(octeon_mdiobus_mod_exit);
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MODULE_DESCRIPTION(DRV_DESCRIPTION);
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MODULE_VERSION(DRV_VERSION);
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MODULE_AUTHOR("David Daney");
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MODULE_LICENSE("GPL");
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