![Daniel Mack](/assets/img/avatar_default.png)
In particular, several occurances of funny versions of 'success', 'unknown', 'therefore', 'acknowledge', 'argument', 'achieve', 'address', 'beginning', 'desirable', 'separate' and 'necessary' are fixed. Signed-off-by: Daniel Mack <daniel@caiaq.de> Cc: Joe Perches <joe@perches.com> Cc: Junio C Hamano <gitster@pobox.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
955 lines
26 KiB
C
955 lines
26 KiB
C
/*
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* IBM eServer eHCA Infiniband device driver for Linux on POWER
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*
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* post_send/recv, poll_cq, req_notify
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*
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* Authors: Hoang-Nam Nguyen <hnguyen@de.ibm.com>
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* Waleri Fomin <fomin@de.ibm.com>
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* Joachim Fenkes <fenkes@de.ibm.com>
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* Reinhard Ernst <rernst@de.ibm.com>
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*
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* Copyright (c) 2005 IBM Corporation
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*
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* All rights reserved.
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*
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* This source code is distributed under a dual license of GPL v2.0 and OpenIB
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* BSD.
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*
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* OpenIB BSD License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials
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* provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <asm/system.h>
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#include "ehca_classes.h"
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#include "ehca_tools.h"
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#include "ehca_qes.h"
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#include "ehca_iverbs.h"
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#include "hcp_if.h"
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#include "hipz_fns.h"
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/* in RC traffic, insert an empty RDMA READ every this many packets */
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#define ACK_CIRC_THRESHOLD 2000000
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static u64 replace_wr_id(u64 wr_id, u16 idx)
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{
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u64 ret;
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ret = wr_id & ~QMAP_IDX_MASK;
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ret |= idx & QMAP_IDX_MASK;
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return ret;
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}
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static u16 get_app_wr_id(u64 wr_id)
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{
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return wr_id & QMAP_IDX_MASK;
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}
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static inline int ehca_write_rwqe(struct ipz_queue *ipz_rqueue,
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struct ehca_wqe *wqe_p,
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struct ib_recv_wr *recv_wr,
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u32 rq_map_idx)
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{
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u8 cnt_ds;
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if (unlikely((recv_wr->num_sge < 0) ||
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(recv_wr->num_sge > ipz_rqueue->act_nr_of_sg))) {
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ehca_gen_err("Invalid number of WQE SGE. "
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"num_sqe=%x max_nr_of_sg=%x",
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recv_wr->num_sge, ipz_rqueue->act_nr_of_sg);
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return -EINVAL; /* invalid SG list length */
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}
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/* clear wqe header until sglist */
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memset(wqe_p, 0, offsetof(struct ehca_wqe, u.ud_av.sg_list));
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wqe_p->work_request_id = replace_wr_id(recv_wr->wr_id, rq_map_idx);
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wqe_p->nr_of_data_seg = recv_wr->num_sge;
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for (cnt_ds = 0; cnt_ds < recv_wr->num_sge; cnt_ds++) {
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wqe_p->u.all_rcv.sg_list[cnt_ds].vaddr =
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recv_wr->sg_list[cnt_ds].addr;
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wqe_p->u.all_rcv.sg_list[cnt_ds].lkey =
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recv_wr->sg_list[cnt_ds].lkey;
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wqe_p->u.all_rcv.sg_list[cnt_ds].length =
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recv_wr->sg_list[cnt_ds].length;
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}
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if (ehca_debug_level >= 3) {
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ehca_gen_dbg("RECEIVE WQE written into ipz_rqueue=%p",
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ipz_rqueue);
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ehca_dmp(wqe_p, 16*(6 + wqe_p->nr_of_data_seg), "recv wqe");
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}
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return 0;
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}
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#if defined(DEBUG_GSI_SEND_WR)
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/* need ib_mad struct */
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#include <rdma/ib_mad.h>
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static void trace_send_wr_ud(const struct ib_send_wr *send_wr)
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{
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int idx;
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int j;
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while (send_wr) {
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struct ib_mad_hdr *mad_hdr = send_wr->wr.ud.mad_hdr;
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struct ib_sge *sge = send_wr->sg_list;
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ehca_gen_dbg("send_wr#%x wr_id=%lx num_sge=%x "
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"send_flags=%x opcode=%x", idx, send_wr->wr_id,
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send_wr->num_sge, send_wr->send_flags,
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send_wr->opcode);
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if (mad_hdr) {
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ehca_gen_dbg("send_wr#%x mad_hdr base_version=%x "
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"mgmt_class=%x class_version=%x method=%x "
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"status=%x class_specific=%x tid=%lx "
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"attr_id=%x resv=%x attr_mod=%x",
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idx, mad_hdr->base_version,
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mad_hdr->mgmt_class,
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mad_hdr->class_version, mad_hdr->method,
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mad_hdr->status, mad_hdr->class_specific,
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mad_hdr->tid, mad_hdr->attr_id,
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mad_hdr->resv,
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mad_hdr->attr_mod);
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}
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for (j = 0; j < send_wr->num_sge; j++) {
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u8 *data = (u8 *)abs_to_virt(sge->addr);
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ehca_gen_dbg("send_wr#%x sge#%x addr=%p length=%x "
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"lkey=%x",
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idx, j, data, sge->length, sge->lkey);
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/* assume length is n*16 */
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ehca_dmp(data, sge->length, "send_wr#%x sge#%x",
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idx, j);
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sge++;
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} /* eof for j */
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idx++;
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send_wr = send_wr->next;
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} /* eof while send_wr */
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}
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#endif /* DEBUG_GSI_SEND_WR */
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static inline int ehca_write_swqe(struct ehca_qp *qp,
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struct ehca_wqe *wqe_p,
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const struct ib_send_wr *send_wr,
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u32 sq_map_idx,
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int hidden)
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{
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u32 idx;
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u64 dma_length;
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struct ehca_av *my_av;
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u32 remote_qkey = send_wr->wr.ud.remote_qkey;
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struct ehca_qmap_entry *qmap_entry = &qp->sq_map.map[sq_map_idx];
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if (unlikely((send_wr->num_sge < 0) ||
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(send_wr->num_sge > qp->ipz_squeue.act_nr_of_sg))) {
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ehca_gen_err("Invalid number of WQE SGE. "
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"num_sqe=%x max_nr_of_sg=%x",
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send_wr->num_sge, qp->ipz_squeue.act_nr_of_sg);
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return -EINVAL; /* invalid SG list length */
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}
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/* clear wqe header until sglist */
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memset(wqe_p, 0, offsetof(struct ehca_wqe, u.ud_av.sg_list));
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wqe_p->work_request_id = replace_wr_id(send_wr->wr_id, sq_map_idx);
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qmap_entry->app_wr_id = get_app_wr_id(send_wr->wr_id);
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qmap_entry->reported = 0;
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qmap_entry->cqe_req = 0;
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switch (send_wr->opcode) {
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case IB_WR_SEND:
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case IB_WR_SEND_WITH_IMM:
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wqe_p->optype = WQE_OPTYPE_SEND;
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break;
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case IB_WR_RDMA_WRITE:
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case IB_WR_RDMA_WRITE_WITH_IMM:
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wqe_p->optype = WQE_OPTYPE_RDMAWRITE;
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break;
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case IB_WR_RDMA_READ:
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wqe_p->optype = WQE_OPTYPE_RDMAREAD;
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break;
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default:
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ehca_gen_err("Invalid opcode=%x", send_wr->opcode);
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return -EINVAL; /* invalid opcode */
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}
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wqe_p->wqef = (send_wr->opcode) & WQEF_HIGH_NIBBLE;
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wqe_p->wr_flag = 0;
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if ((send_wr->send_flags & IB_SEND_SIGNALED ||
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qp->init_attr.sq_sig_type == IB_SIGNAL_ALL_WR)
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&& !hidden) {
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wqe_p->wr_flag |= WQE_WRFLAG_REQ_SIGNAL_COM;
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qmap_entry->cqe_req = 1;
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}
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if (send_wr->opcode == IB_WR_SEND_WITH_IMM ||
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send_wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) {
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/* this might not work as long as HW does not support it */
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wqe_p->immediate_data = be32_to_cpu(send_wr->ex.imm_data);
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wqe_p->wr_flag |= WQE_WRFLAG_IMM_DATA_PRESENT;
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}
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wqe_p->nr_of_data_seg = send_wr->num_sge;
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switch (qp->qp_type) {
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case IB_QPT_SMI:
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case IB_QPT_GSI:
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/* no break is intential here */
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case IB_QPT_UD:
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/* IB 1.2 spec C10-15 compliance */
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if (send_wr->wr.ud.remote_qkey & 0x80000000)
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remote_qkey = qp->qkey;
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wqe_p->destination_qp_number = send_wr->wr.ud.remote_qpn << 8;
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wqe_p->local_ee_context_qkey = remote_qkey;
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if (unlikely(!send_wr->wr.ud.ah)) {
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ehca_gen_err("wr.ud.ah is NULL. qp=%p", qp);
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return -EINVAL;
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}
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if (unlikely(send_wr->wr.ud.remote_qpn == 0)) {
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ehca_gen_err("dest QP# is 0. qp=%x", qp->real_qp_num);
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return -EINVAL;
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}
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my_av = container_of(send_wr->wr.ud.ah, struct ehca_av, ib_ah);
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wqe_p->u.ud_av.ud_av = my_av->av;
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/*
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* omitted check of IB_SEND_INLINE
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* since HW does not support it
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*/
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for (idx = 0; idx < send_wr->num_sge; idx++) {
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wqe_p->u.ud_av.sg_list[idx].vaddr =
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send_wr->sg_list[idx].addr;
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wqe_p->u.ud_av.sg_list[idx].lkey =
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send_wr->sg_list[idx].lkey;
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wqe_p->u.ud_av.sg_list[idx].length =
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send_wr->sg_list[idx].length;
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} /* eof for idx */
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if (qp->qp_type == IB_QPT_SMI ||
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qp->qp_type == IB_QPT_GSI)
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wqe_p->u.ud_av.ud_av.pmtu = 1;
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if (qp->qp_type == IB_QPT_GSI) {
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wqe_p->pkeyi = send_wr->wr.ud.pkey_index;
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#ifdef DEBUG_GSI_SEND_WR
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trace_send_wr_ud(send_wr);
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#endif /* DEBUG_GSI_SEND_WR */
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}
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break;
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case IB_QPT_UC:
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if (send_wr->send_flags & IB_SEND_FENCE)
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wqe_p->wr_flag |= WQE_WRFLAG_FENCE;
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/* no break is intentional here */
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case IB_QPT_RC:
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/* TODO: atomic not implemented */
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wqe_p->u.nud.remote_virtual_address =
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send_wr->wr.rdma.remote_addr;
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wqe_p->u.nud.rkey = send_wr->wr.rdma.rkey;
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/*
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* omitted checking of IB_SEND_INLINE
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* since HW does not support it
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*/
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dma_length = 0;
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for (idx = 0; idx < send_wr->num_sge; idx++) {
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wqe_p->u.nud.sg_list[idx].vaddr =
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send_wr->sg_list[idx].addr;
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wqe_p->u.nud.sg_list[idx].lkey =
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send_wr->sg_list[idx].lkey;
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wqe_p->u.nud.sg_list[idx].length =
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send_wr->sg_list[idx].length;
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dma_length += send_wr->sg_list[idx].length;
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} /* eof idx */
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wqe_p->u.nud.atomic_1st_op_dma_len = dma_length;
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/* unsolicited ack circumvention */
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if (send_wr->opcode == IB_WR_RDMA_READ) {
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/* on RDMA read, switch on and reset counters */
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qp->message_count = qp->packet_count = 0;
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qp->unsol_ack_circ = 1;
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} else
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/* else estimate #packets */
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qp->packet_count += (dma_length >> qp->mtu_shift) + 1;
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break;
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default:
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ehca_gen_err("Invalid qptype=%x", qp->qp_type);
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return -EINVAL;
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}
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if (ehca_debug_level >= 3) {
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ehca_gen_dbg("SEND WQE written into queue qp=%p ", qp);
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ehca_dmp( wqe_p, 16*(6 + wqe_p->nr_of_data_seg), "send wqe");
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}
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return 0;
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}
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/* map_ib_wc_status converts raw cqe_status to ib_wc_status */
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static inline void map_ib_wc_status(u32 cqe_status,
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enum ib_wc_status *wc_status)
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{
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if (unlikely(cqe_status & WC_STATUS_ERROR_BIT)) {
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switch (cqe_status & 0x3F) {
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case 0x01:
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case 0x21:
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*wc_status = IB_WC_LOC_LEN_ERR;
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break;
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case 0x02:
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case 0x22:
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*wc_status = IB_WC_LOC_QP_OP_ERR;
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break;
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case 0x03:
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case 0x23:
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*wc_status = IB_WC_LOC_EEC_OP_ERR;
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break;
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case 0x04:
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case 0x24:
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*wc_status = IB_WC_LOC_PROT_ERR;
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break;
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case 0x05:
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case 0x25:
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*wc_status = IB_WC_WR_FLUSH_ERR;
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break;
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case 0x06:
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*wc_status = IB_WC_MW_BIND_ERR;
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break;
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case 0x07: /* remote error - look into bits 20:24 */
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switch ((cqe_status
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& WC_STATUS_REMOTE_ERROR_FLAGS) >> 11) {
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case 0x0:
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/*
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* PSN Sequence Error!
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* couldn't find a matching status!
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*/
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*wc_status = IB_WC_GENERAL_ERR;
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break;
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case 0x1:
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*wc_status = IB_WC_REM_INV_REQ_ERR;
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break;
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case 0x2:
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*wc_status = IB_WC_REM_ACCESS_ERR;
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break;
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case 0x3:
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*wc_status = IB_WC_REM_OP_ERR;
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break;
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case 0x4:
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*wc_status = IB_WC_REM_INV_RD_REQ_ERR;
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break;
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}
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break;
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case 0x08:
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*wc_status = IB_WC_RETRY_EXC_ERR;
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break;
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case 0x09:
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*wc_status = IB_WC_RNR_RETRY_EXC_ERR;
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break;
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case 0x0A:
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case 0x2D:
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*wc_status = IB_WC_REM_ABORT_ERR;
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break;
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case 0x0B:
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case 0x2E:
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*wc_status = IB_WC_INV_EECN_ERR;
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break;
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case 0x0C:
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case 0x2F:
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*wc_status = IB_WC_INV_EEC_STATE_ERR;
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break;
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case 0x0D:
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*wc_status = IB_WC_BAD_RESP_ERR;
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break;
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case 0x10:
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/* WQE purged */
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*wc_status = IB_WC_WR_FLUSH_ERR;
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break;
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default:
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*wc_status = IB_WC_FATAL_ERR;
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}
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} else
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*wc_status = IB_WC_SUCCESS;
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}
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static inline int post_one_send(struct ehca_qp *my_qp,
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struct ib_send_wr *cur_send_wr,
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int hidden)
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{
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struct ehca_wqe *wqe_p;
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int ret;
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u32 sq_map_idx;
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u64 start_offset = my_qp->ipz_squeue.current_q_offset;
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/* get pointer next to free WQE */
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wqe_p = ipz_qeit_get_inc(&my_qp->ipz_squeue);
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if (unlikely(!wqe_p)) {
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/* too many posted work requests: queue overflow */
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ehca_err(my_qp->ib_qp.device, "Too many posted WQEs "
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"qp_num=%x", my_qp->ib_qp.qp_num);
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return -ENOMEM;
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}
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/*
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* Get the index of the WQE in the send queue. The same index is used
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* for writing into the sq_map.
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*/
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sq_map_idx = start_offset / my_qp->ipz_squeue.qe_size;
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/* write a SEND WQE into the QUEUE */
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ret = ehca_write_swqe(my_qp, wqe_p, cur_send_wr, sq_map_idx, hidden);
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/*
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* if something failed,
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* reset the free entry pointer to the start value
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*/
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if (unlikely(ret)) {
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my_qp->ipz_squeue.current_q_offset = start_offset;
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ehca_err(my_qp->ib_qp.device, "Could not write WQE "
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"qp_num=%x", my_qp->ib_qp.qp_num);
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return -EINVAL;
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}
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return 0;
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}
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int ehca_post_send(struct ib_qp *qp,
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struct ib_send_wr *send_wr,
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struct ib_send_wr **bad_send_wr)
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{
|
|
struct ehca_qp *my_qp = container_of(qp, struct ehca_qp, ib_qp);
|
|
int wqe_cnt = 0;
|
|
int ret = 0;
|
|
unsigned long flags;
|
|
|
|
/* Reject WR if QP is in RESET, INIT or RTR state */
|
|
if (unlikely(my_qp->state < IB_QPS_RTS)) {
|
|
ehca_err(qp->device, "Invalid QP state qp_state=%d qpn=%x",
|
|
my_qp->state, qp->qp_num);
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
/* LOCK the QUEUE */
|
|
spin_lock_irqsave(&my_qp->spinlock_s, flags);
|
|
|
|
/* Send an empty extra RDMA read if:
|
|
* 1) there has been an RDMA read on this connection before
|
|
* 2) no RDMA read occurred for ACK_CIRC_THRESHOLD link packets
|
|
* 3) we can be sure that any previous extra RDMA read has been
|
|
* processed so we don't overflow the SQ
|
|
*/
|
|
if (unlikely(my_qp->unsol_ack_circ &&
|
|
my_qp->packet_count > ACK_CIRC_THRESHOLD &&
|
|
my_qp->message_count > my_qp->init_attr.cap.max_send_wr)) {
|
|
/* insert an empty RDMA READ to fix up the remote QP state */
|
|
struct ib_send_wr circ_wr;
|
|
memset(&circ_wr, 0, sizeof(circ_wr));
|
|
circ_wr.opcode = IB_WR_RDMA_READ;
|
|
post_one_send(my_qp, &circ_wr, 1); /* ignore retcode */
|
|
wqe_cnt++;
|
|
ehca_dbg(qp->device, "posted circ wr qp_num=%x", qp->qp_num);
|
|
my_qp->message_count = my_qp->packet_count = 0;
|
|
}
|
|
|
|
/* loop processes list of send reqs */
|
|
while (send_wr) {
|
|
ret = post_one_send(my_qp, send_wr, 0);
|
|
if (unlikely(ret)) {
|
|
goto post_send_exit0;
|
|
}
|
|
wqe_cnt++;
|
|
send_wr = send_wr->next;
|
|
}
|
|
|
|
post_send_exit0:
|
|
iosync(); /* serialize GAL register access */
|
|
hipz_update_sqa(my_qp, wqe_cnt);
|
|
if (unlikely(ret || ehca_debug_level >= 2))
|
|
ehca_dbg(qp->device, "ehca_qp=%p qp_num=%x wqe_cnt=%d ret=%i",
|
|
my_qp, qp->qp_num, wqe_cnt, ret);
|
|
my_qp->message_count += wqe_cnt;
|
|
spin_unlock_irqrestore(&my_qp->spinlock_s, flags);
|
|
|
|
out:
|
|
if (ret)
|
|
*bad_send_wr = send_wr;
|
|
return ret;
|
|
}
|
|
|
|
static int internal_post_recv(struct ehca_qp *my_qp,
|
|
struct ib_device *dev,
|
|
struct ib_recv_wr *recv_wr,
|
|
struct ib_recv_wr **bad_recv_wr)
|
|
{
|
|
struct ehca_wqe *wqe_p;
|
|
int wqe_cnt = 0;
|
|
int ret = 0;
|
|
u32 rq_map_idx;
|
|
unsigned long flags;
|
|
struct ehca_qmap_entry *qmap_entry;
|
|
|
|
if (unlikely(!HAS_RQ(my_qp))) {
|
|
ehca_err(dev, "QP has no RQ ehca_qp=%p qp_num=%x ext_type=%d",
|
|
my_qp, my_qp->real_qp_num, my_qp->ext_type);
|
|
ret = -ENODEV;
|
|
goto out;
|
|
}
|
|
|
|
/* LOCK the QUEUE */
|
|
spin_lock_irqsave(&my_qp->spinlock_r, flags);
|
|
|
|
/* loop processes list of recv reqs */
|
|
while (recv_wr) {
|
|
u64 start_offset = my_qp->ipz_rqueue.current_q_offset;
|
|
/* get pointer next to free WQE */
|
|
wqe_p = ipz_qeit_get_inc(&my_qp->ipz_rqueue);
|
|
if (unlikely(!wqe_p)) {
|
|
/* too many posted work requests: queue overflow */
|
|
ret = -ENOMEM;
|
|
ehca_err(dev, "Too many posted WQEs "
|
|
"qp_num=%x", my_qp->real_qp_num);
|
|
goto post_recv_exit0;
|
|
}
|
|
/*
|
|
* Get the index of the WQE in the recv queue. The same index
|
|
* is used for writing into the rq_map.
|
|
*/
|
|
rq_map_idx = start_offset / my_qp->ipz_rqueue.qe_size;
|
|
|
|
/* write a RECV WQE into the QUEUE */
|
|
ret = ehca_write_rwqe(&my_qp->ipz_rqueue, wqe_p, recv_wr,
|
|
rq_map_idx);
|
|
/*
|
|
* if something failed,
|
|
* reset the free entry pointer to the start value
|
|
*/
|
|
if (unlikely(ret)) {
|
|
my_qp->ipz_rqueue.current_q_offset = start_offset;
|
|
ret = -EINVAL;
|
|
ehca_err(dev, "Could not write WQE "
|
|
"qp_num=%x", my_qp->real_qp_num);
|
|
goto post_recv_exit0;
|
|
}
|
|
|
|
qmap_entry = &my_qp->rq_map.map[rq_map_idx];
|
|
qmap_entry->app_wr_id = get_app_wr_id(recv_wr->wr_id);
|
|
qmap_entry->reported = 0;
|
|
qmap_entry->cqe_req = 1;
|
|
|
|
wqe_cnt++;
|
|
recv_wr = recv_wr->next;
|
|
} /* eof for recv_wr */
|
|
|
|
post_recv_exit0:
|
|
iosync(); /* serialize GAL register access */
|
|
hipz_update_rqa(my_qp, wqe_cnt);
|
|
if (unlikely(ret || ehca_debug_level >= 2))
|
|
ehca_dbg(dev, "ehca_qp=%p qp_num=%x wqe_cnt=%d ret=%i",
|
|
my_qp, my_qp->real_qp_num, wqe_cnt, ret);
|
|
spin_unlock_irqrestore(&my_qp->spinlock_r, flags);
|
|
|
|
out:
|
|
if (ret)
|
|
*bad_recv_wr = recv_wr;
|
|
|
|
return ret;
|
|
}
|
|
|
|
int ehca_post_recv(struct ib_qp *qp,
|
|
struct ib_recv_wr *recv_wr,
|
|
struct ib_recv_wr **bad_recv_wr)
|
|
{
|
|
struct ehca_qp *my_qp = container_of(qp, struct ehca_qp, ib_qp);
|
|
|
|
/* Reject WR if QP is in RESET state */
|
|
if (unlikely(my_qp->state == IB_QPS_RESET)) {
|
|
ehca_err(qp->device, "Invalid QP state qp_state=%d qpn=%x",
|
|
my_qp->state, qp->qp_num);
|
|
*bad_recv_wr = recv_wr;
|
|
return -EINVAL;
|
|
}
|
|
|
|
return internal_post_recv(my_qp, qp->device, recv_wr, bad_recv_wr);
|
|
}
|
|
|
|
int ehca_post_srq_recv(struct ib_srq *srq,
|
|
struct ib_recv_wr *recv_wr,
|
|
struct ib_recv_wr **bad_recv_wr)
|
|
{
|
|
return internal_post_recv(container_of(srq, struct ehca_qp, ib_srq),
|
|
srq->device, recv_wr, bad_recv_wr);
|
|
}
|
|
|
|
/*
|
|
* ib_wc_opcode table converts ehca wc opcode to ib
|
|
* Since we use zero to indicate invalid opcode, the actual ib opcode must
|
|
* be decremented!!!
|
|
*/
|
|
static const u8 ib_wc_opcode[255] = {
|
|
[0x01] = IB_WC_RECV+1,
|
|
[0x02] = IB_WC_RECV_RDMA_WITH_IMM+1,
|
|
[0x04] = IB_WC_BIND_MW+1,
|
|
[0x08] = IB_WC_FETCH_ADD+1,
|
|
[0x10] = IB_WC_COMP_SWAP+1,
|
|
[0x20] = IB_WC_RDMA_WRITE+1,
|
|
[0x40] = IB_WC_RDMA_READ+1,
|
|
[0x80] = IB_WC_SEND+1
|
|
};
|
|
|
|
/* internal function to poll one entry of cq */
|
|
static inline int ehca_poll_cq_one(struct ib_cq *cq, struct ib_wc *wc)
|
|
{
|
|
int ret = 0, qmap_tail_idx;
|
|
struct ehca_cq *my_cq = container_of(cq, struct ehca_cq, ib_cq);
|
|
struct ehca_cqe *cqe;
|
|
struct ehca_qp *my_qp;
|
|
struct ehca_qmap_entry *qmap_entry;
|
|
struct ehca_queue_map *qmap;
|
|
int cqe_count = 0, is_error;
|
|
|
|
repoll:
|
|
cqe = (struct ehca_cqe *)
|
|
ipz_qeit_get_inc_valid(&my_cq->ipz_queue);
|
|
if (!cqe) {
|
|
ret = -EAGAIN;
|
|
if (ehca_debug_level >= 3)
|
|
ehca_dbg(cq->device, "Completion queue is empty "
|
|
"my_cq=%p cq_num=%x", my_cq, my_cq->cq_number);
|
|
goto poll_cq_one_exit0;
|
|
}
|
|
|
|
/* prevents loads being reordered across this point */
|
|
rmb();
|
|
|
|
cqe_count++;
|
|
if (unlikely(cqe->status & WC_STATUS_PURGE_BIT)) {
|
|
struct ehca_qp *qp;
|
|
int purgeflag;
|
|
unsigned long flags;
|
|
|
|
qp = ehca_cq_get_qp(my_cq, cqe->local_qp_number);
|
|
if (!qp) {
|
|
ehca_err(cq->device, "cq_num=%x qp_num=%x "
|
|
"could not find qp -> ignore cqe",
|
|
my_cq->cq_number, cqe->local_qp_number);
|
|
ehca_dmp(cqe, 64, "cq_num=%x qp_num=%x",
|
|
my_cq->cq_number, cqe->local_qp_number);
|
|
/* ignore this purged cqe */
|
|
goto repoll;
|
|
}
|
|
spin_lock_irqsave(&qp->spinlock_s, flags);
|
|
purgeflag = qp->sqerr_purgeflag;
|
|
spin_unlock_irqrestore(&qp->spinlock_s, flags);
|
|
|
|
if (purgeflag) {
|
|
ehca_dbg(cq->device,
|
|
"Got CQE with purged bit qp_num=%x src_qp=%x",
|
|
cqe->local_qp_number, cqe->remote_qp_number);
|
|
if (ehca_debug_level >= 2)
|
|
ehca_dmp(cqe, 64, "qp_num=%x src_qp=%x",
|
|
cqe->local_qp_number,
|
|
cqe->remote_qp_number);
|
|
/*
|
|
* ignore this to avoid double cqes of bad wqe
|
|
* that caused sqe and turn off purge flag
|
|
*/
|
|
qp->sqerr_purgeflag = 0;
|
|
goto repoll;
|
|
}
|
|
}
|
|
|
|
is_error = cqe->status & WC_STATUS_ERROR_BIT;
|
|
|
|
/* trace error CQEs if debug_level >= 1, trace all CQEs if >= 3 */
|
|
if (unlikely(ehca_debug_level >= 3 || (ehca_debug_level && is_error))) {
|
|
ehca_dbg(cq->device,
|
|
"Received %sCOMPLETION ehca_cq=%p cq_num=%x -----",
|
|
is_error ? "ERROR " : "", my_cq, my_cq->cq_number);
|
|
ehca_dmp(cqe, 64, "ehca_cq=%p cq_num=%x",
|
|
my_cq, my_cq->cq_number);
|
|
ehca_dbg(cq->device,
|
|
"ehca_cq=%p cq_num=%x -------------------------",
|
|
my_cq, my_cq->cq_number);
|
|
}
|
|
|
|
read_lock(&ehca_qp_idr_lock);
|
|
my_qp = idr_find(&ehca_qp_idr, cqe->qp_token);
|
|
read_unlock(&ehca_qp_idr_lock);
|
|
if (!my_qp)
|
|
goto repoll;
|
|
wc->qp = &my_qp->ib_qp;
|
|
|
|
qmap_tail_idx = get_app_wr_id(cqe->work_request_id);
|
|
if (!(cqe->w_completion_flags & WC_SEND_RECEIVE_BIT))
|
|
/* We got a send completion. */
|
|
qmap = &my_qp->sq_map;
|
|
else
|
|
/* We got a receive completion. */
|
|
qmap = &my_qp->rq_map;
|
|
|
|
/* advance the tail pointer */
|
|
qmap->tail = qmap_tail_idx;
|
|
|
|
if (is_error) {
|
|
/*
|
|
* set left_to_poll to 0 because in error state, we will not
|
|
* get any additional CQEs
|
|
*/
|
|
my_qp->sq_map.next_wqe_idx = next_index(my_qp->sq_map.tail,
|
|
my_qp->sq_map.entries);
|
|
my_qp->sq_map.left_to_poll = 0;
|
|
ehca_add_to_err_list(my_qp, 1);
|
|
|
|
my_qp->rq_map.next_wqe_idx = next_index(my_qp->rq_map.tail,
|
|
my_qp->rq_map.entries);
|
|
my_qp->rq_map.left_to_poll = 0;
|
|
if (HAS_RQ(my_qp))
|
|
ehca_add_to_err_list(my_qp, 0);
|
|
}
|
|
|
|
qmap_entry = &qmap->map[qmap_tail_idx];
|
|
if (qmap_entry->reported) {
|
|
ehca_warn(cq->device, "Double cqe on qp_num=%#x",
|
|
my_qp->real_qp_num);
|
|
/* found a double cqe, discard it and read next one */
|
|
goto repoll;
|
|
}
|
|
|
|
wc->wr_id = replace_wr_id(cqe->work_request_id, qmap_entry->app_wr_id);
|
|
qmap_entry->reported = 1;
|
|
|
|
/* if left_to_poll is decremented to 0, add the QP to the error list */
|
|
if (qmap->left_to_poll > 0) {
|
|
qmap->left_to_poll--;
|
|
if ((my_qp->sq_map.left_to_poll == 0) &&
|
|
(my_qp->rq_map.left_to_poll == 0)) {
|
|
ehca_add_to_err_list(my_qp, 1);
|
|
if (HAS_RQ(my_qp))
|
|
ehca_add_to_err_list(my_qp, 0);
|
|
}
|
|
}
|
|
|
|
/* eval ib_wc_opcode */
|
|
wc->opcode = ib_wc_opcode[cqe->optype]-1;
|
|
if (unlikely(wc->opcode == -1)) {
|
|
ehca_err(cq->device, "Invalid cqe->OPType=%x cqe->status=%x "
|
|
"ehca_cq=%p cq_num=%x",
|
|
cqe->optype, cqe->status, my_cq, my_cq->cq_number);
|
|
/* dump cqe for other infos */
|
|
ehca_dmp(cqe, 64, "ehca_cq=%p cq_num=%x",
|
|
my_cq, my_cq->cq_number);
|
|
/* update also queue adder to throw away this entry!!! */
|
|
goto repoll;
|
|
}
|
|
|
|
/* eval ib_wc_status */
|
|
if (unlikely(is_error)) {
|
|
/* complete with errors */
|
|
map_ib_wc_status(cqe->status, &wc->status);
|
|
wc->vendor_err = wc->status;
|
|
} else
|
|
wc->status = IB_WC_SUCCESS;
|
|
|
|
wc->byte_len = cqe->nr_bytes_transferred;
|
|
wc->pkey_index = cqe->pkey_index;
|
|
wc->slid = cqe->rlid;
|
|
wc->dlid_path_bits = cqe->dlid;
|
|
wc->src_qp = cqe->remote_qp_number;
|
|
/*
|
|
* HW has "Immed data present" and "GRH present" in bits 6 and 5.
|
|
* SW defines those in bits 1 and 0, so we can just shift and mask.
|
|
*/
|
|
wc->wc_flags = (cqe->w_completion_flags >> 5) & 3;
|
|
wc->ex.imm_data = cpu_to_be32(cqe->immediate_data);
|
|
wc->sl = cqe->service_level;
|
|
|
|
poll_cq_one_exit0:
|
|
if (cqe_count > 0)
|
|
hipz_update_feca(my_cq, cqe_count);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int generate_flush_cqes(struct ehca_qp *my_qp, struct ib_cq *cq,
|
|
struct ib_wc *wc, int num_entries,
|
|
struct ipz_queue *ipz_queue, int on_sq)
|
|
{
|
|
int nr = 0;
|
|
struct ehca_wqe *wqe;
|
|
u64 offset;
|
|
struct ehca_queue_map *qmap;
|
|
struct ehca_qmap_entry *qmap_entry;
|
|
|
|
if (on_sq)
|
|
qmap = &my_qp->sq_map;
|
|
else
|
|
qmap = &my_qp->rq_map;
|
|
|
|
qmap_entry = &qmap->map[qmap->next_wqe_idx];
|
|
|
|
while ((nr < num_entries) && (qmap_entry->reported == 0)) {
|
|
/* generate flush CQE */
|
|
|
|
memset(wc, 0, sizeof(*wc));
|
|
|
|
offset = qmap->next_wqe_idx * ipz_queue->qe_size;
|
|
wqe = (struct ehca_wqe *)ipz_qeit_calc(ipz_queue, offset);
|
|
if (!wqe) {
|
|
ehca_err(cq->device, "Invalid wqe offset=%#llx on "
|
|
"qp_num=%#x", offset, my_qp->real_qp_num);
|
|
return nr;
|
|
}
|
|
|
|
wc->wr_id = replace_wr_id(wqe->work_request_id,
|
|
qmap_entry->app_wr_id);
|
|
|
|
if (on_sq) {
|
|
switch (wqe->optype) {
|
|
case WQE_OPTYPE_SEND:
|
|
wc->opcode = IB_WC_SEND;
|
|
break;
|
|
case WQE_OPTYPE_RDMAWRITE:
|
|
wc->opcode = IB_WC_RDMA_WRITE;
|
|
break;
|
|
case WQE_OPTYPE_RDMAREAD:
|
|
wc->opcode = IB_WC_RDMA_READ;
|
|
break;
|
|
default:
|
|
ehca_err(cq->device, "Invalid optype=%x",
|
|
wqe->optype);
|
|
return nr;
|
|
}
|
|
} else
|
|
wc->opcode = IB_WC_RECV;
|
|
|
|
if (wqe->wr_flag & WQE_WRFLAG_IMM_DATA_PRESENT) {
|
|
wc->ex.imm_data = wqe->immediate_data;
|
|
wc->wc_flags |= IB_WC_WITH_IMM;
|
|
}
|
|
|
|
wc->status = IB_WC_WR_FLUSH_ERR;
|
|
|
|
wc->qp = &my_qp->ib_qp;
|
|
|
|
/* mark as reported and advance next_wqe pointer */
|
|
qmap_entry->reported = 1;
|
|
qmap->next_wqe_idx = next_index(qmap->next_wqe_idx,
|
|
qmap->entries);
|
|
qmap_entry = &qmap->map[qmap->next_wqe_idx];
|
|
|
|
wc++; nr++;
|
|
}
|
|
|
|
return nr;
|
|
|
|
}
|
|
|
|
int ehca_poll_cq(struct ib_cq *cq, int num_entries, struct ib_wc *wc)
|
|
{
|
|
struct ehca_cq *my_cq = container_of(cq, struct ehca_cq, ib_cq);
|
|
int nr;
|
|
struct ehca_qp *err_qp;
|
|
struct ib_wc *current_wc = wc;
|
|
int ret = 0;
|
|
unsigned long flags;
|
|
int entries_left = num_entries;
|
|
|
|
if (num_entries < 1) {
|
|
ehca_err(cq->device, "Invalid num_entries=%d ehca_cq=%p "
|
|
"cq_num=%x", num_entries, my_cq, my_cq->cq_number);
|
|
ret = -EINVAL;
|
|
goto poll_cq_exit0;
|
|
}
|
|
|
|
spin_lock_irqsave(&my_cq->spinlock, flags);
|
|
|
|
/* generate flush cqes for send queues */
|
|
list_for_each_entry(err_qp, &my_cq->sqp_err_list, sq_err_node) {
|
|
nr = generate_flush_cqes(err_qp, cq, current_wc, entries_left,
|
|
&err_qp->ipz_squeue, 1);
|
|
entries_left -= nr;
|
|
current_wc += nr;
|
|
|
|
if (entries_left == 0)
|
|
break;
|
|
}
|
|
|
|
/* generate flush cqes for receive queues */
|
|
list_for_each_entry(err_qp, &my_cq->rqp_err_list, rq_err_node) {
|
|
nr = generate_flush_cqes(err_qp, cq, current_wc, entries_left,
|
|
&err_qp->ipz_rqueue, 0);
|
|
entries_left -= nr;
|
|
current_wc += nr;
|
|
|
|
if (entries_left == 0)
|
|
break;
|
|
}
|
|
|
|
for (nr = 0; nr < entries_left; nr++) {
|
|
ret = ehca_poll_cq_one(cq, current_wc);
|
|
if (ret)
|
|
break;
|
|
current_wc++;
|
|
} /* eof for nr */
|
|
entries_left -= nr;
|
|
|
|
spin_unlock_irqrestore(&my_cq->spinlock, flags);
|
|
if (ret == -EAGAIN || !ret)
|
|
ret = num_entries - entries_left;
|
|
|
|
poll_cq_exit0:
|
|
return ret;
|
|
}
|
|
|
|
int ehca_req_notify_cq(struct ib_cq *cq, enum ib_cq_notify_flags notify_flags)
|
|
{
|
|
struct ehca_cq *my_cq = container_of(cq, struct ehca_cq, ib_cq);
|
|
int ret = 0;
|
|
|
|
switch (notify_flags & IB_CQ_SOLICITED_MASK) {
|
|
case IB_CQ_SOLICITED:
|
|
hipz_set_cqx_n0(my_cq, 1);
|
|
break;
|
|
case IB_CQ_NEXT_COMP:
|
|
hipz_set_cqx_n1(my_cq, 1);
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (notify_flags & IB_CQ_REPORT_MISSED_EVENTS) {
|
|
unsigned long spl_flags;
|
|
spin_lock_irqsave(&my_cq->spinlock, spl_flags);
|
|
ret = ipz_qeit_is_valid(&my_cq->ipz_queue);
|
|
spin_unlock_irqrestore(&my_cq->spinlock, spl_flags);
|
|
}
|
|
|
|
return ret;
|
|
}
|