e55645ec57
All the ia64 pvops code is now dead code since both xen and kvm support have been ripped out [0] [1]. Just that no one had troubled to rip this stuff out. The only useful remaining pieces were the old pvops docs but that was recently also generalized and moved out from ia64 [2]. This has been run time tested on an ia64 Madison system. [0]003f7de625"KVM: ia64: remove" since v3.19-rc1 [1]d52eefb47d"ia64/xen: Remove Xen support for ia64" since v3.14-rc1 [2] "virtual: Documentation: simplify and generalize paravirt_ops.txt" Signed-off-by: Luis R. Rodriguez <mcgrof@suse.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
118 lines
3.1 KiB
C
118 lines
3.1 KiB
C
#ifndef __ASM_IA64_IOSAPIC_H
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#define __ASM_IA64_IOSAPIC_H
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#define IOSAPIC_REG_SELECT 0x0
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#define IOSAPIC_WINDOW 0x10
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#define IOSAPIC_EOI 0x40
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#define IOSAPIC_VERSION 0x1
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/*
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* Redirection table entry
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*/
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#define IOSAPIC_RTE_LOW(i) (0x10+i*2)
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#define IOSAPIC_RTE_HIGH(i) (0x11+i*2)
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#define IOSAPIC_DEST_SHIFT 16
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/*
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* Delivery mode
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*/
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#define IOSAPIC_DELIVERY_SHIFT 8
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#define IOSAPIC_FIXED 0x0
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#define IOSAPIC_LOWEST_PRIORITY 0x1
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#define IOSAPIC_PMI 0x2
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#define IOSAPIC_NMI 0x4
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#define IOSAPIC_INIT 0x5
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#define IOSAPIC_EXTINT 0x7
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/*
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* Interrupt polarity
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*/
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#define IOSAPIC_POLARITY_SHIFT 13
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#define IOSAPIC_POL_HIGH 0
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#define IOSAPIC_POL_LOW 1
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/*
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* Trigger mode
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*/
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#define IOSAPIC_TRIGGER_SHIFT 15
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#define IOSAPIC_EDGE 0
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#define IOSAPIC_LEVEL 1
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/*
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* Mask bit
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*/
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#define IOSAPIC_MASK_SHIFT 16
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#define IOSAPIC_MASK (1<<IOSAPIC_MASK_SHIFT)
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#define IOSAPIC_VECTOR_MASK 0xffffff00
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#ifndef __ASSEMBLY__
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#ifdef CONFIG_IOSAPIC
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#define NR_IOSAPICS 256
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#define iosapic_pcat_compat_init ia64_native_iosapic_pcat_compat_init
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#define __iosapic_read __ia64_native_iosapic_read
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#define __iosapic_write __ia64_native_iosapic_write
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#define iosapic_get_irq_chip ia64_native_iosapic_get_irq_chip
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extern void __init ia64_native_iosapic_pcat_compat_init(void);
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extern struct irq_chip *ia64_native_iosapic_get_irq_chip(unsigned long trigger);
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static inline unsigned int
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__ia64_native_iosapic_read(char __iomem *iosapic, unsigned int reg)
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{
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writel(reg, iosapic + IOSAPIC_REG_SELECT);
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return readl(iosapic + IOSAPIC_WINDOW);
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}
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static inline void
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__ia64_native_iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val)
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{
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writel(reg, iosapic + IOSAPIC_REG_SELECT);
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writel(val, iosapic + IOSAPIC_WINDOW);
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}
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static inline void iosapic_eoi(char __iomem *iosapic, u32 vector)
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{
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writel(vector, iosapic + IOSAPIC_EOI);
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}
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extern void __init iosapic_system_init (int pcat_compat);
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extern int iosapic_init (unsigned long address, unsigned int gsi_base);
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extern int iosapic_remove (unsigned int gsi_base);
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extern int gsi_to_irq (unsigned int gsi);
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extern int iosapic_register_intr (unsigned int gsi, unsigned long polarity,
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unsigned long trigger);
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extern void iosapic_unregister_intr (unsigned int irq);
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extern void iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
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unsigned long polarity,
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unsigned long trigger);
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extern int __init iosapic_register_platform_intr (u32 int_type,
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unsigned int gsi,
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int pmi_vector,
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u16 eid, u16 id,
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unsigned long polarity,
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unsigned long trigger);
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#ifdef CONFIG_NUMA
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extern void map_iosapic_to_node (unsigned int, int);
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#endif
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#else
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#define iosapic_system_init(pcat_compat) do { } while (0)
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#define iosapic_init(address,gsi_base) (-EINVAL)
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#define iosapic_remove(gsi_base) (-ENODEV)
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#define iosapic_register_intr(gsi,polarity,trigger) (gsi)
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#define iosapic_unregister_intr(irq) do { } while (0)
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#define iosapic_override_isa_irq(isa_irq,gsi,polarity,trigger) do { } while (0)
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#define iosapic_register_platform_intr(type,gsi,pmi,eid,id, \
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polarity,trigger) (gsi)
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#endif
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# endif /* !__ASSEMBLY__ */
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#endif /* __ASM_IA64_IOSAPIC_H */
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