![Feng Wu](/assets/img/avatar_default.png)
This patch adds SMAP handling logic when setting CR4 for guests Thanks a lot to Paolo Bonzini for his suggestion to use the branchless way to detect SMAP violation. Signed-off-by: Feng Wu <feng.wu@intel.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
994 lines
27 KiB
C
994 lines
27 KiB
C
/*
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* Kernel-based Virtual Machine driver for Linux
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*
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* This module enables machines with Intel VT-x extensions to run virtual
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* machines without emulation or binary translation.
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*
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* MMU support
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*
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* Copyright (C) 2006 Qumranet, Inc.
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* Copyright 2010 Red Hat, Inc. and/or its affiliates.
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*
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* Authors:
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* Yaniv Kamay <yaniv@qumranet.com>
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* Avi Kivity <avi@qumranet.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See
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* the COPYING file in the top-level directory.
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*
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*/
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/*
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* We need the mmu code to access both 32-bit and 64-bit guest ptes,
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* so the code in this file is compiled twice, once per pte size.
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*/
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/*
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* This is used to catch non optimized PT_GUEST_(DIRTY|ACCESS)_SHIFT macro
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* uses for EPT without A/D paging type.
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*/
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extern u64 __pure __using_nonexistent_pte_bit(void)
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__compiletime_error("wrong use of PT_GUEST_(DIRTY|ACCESS)_SHIFT");
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#if PTTYPE == 64
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#define pt_element_t u64
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#define guest_walker guest_walker64
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#define FNAME(name) paging##64_##name
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#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
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#define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
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#define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
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#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
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#define PT_LEVEL_BITS PT64_LEVEL_BITS
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#define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK
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#define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK
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#define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
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#define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
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#ifdef CONFIG_X86_64
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#define PT_MAX_FULL_LEVELS 4
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#define CMPXCHG cmpxchg
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#else
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#define CMPXCHG cmpxchg64
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#define PT_MAX_FULL_LEVELS 2
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#endif
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#elif PTTYPE == 32
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#define pt_element_t u32
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#define guest_walker guest_walker32
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#define FNAME(name) paging##32_##name
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#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
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#define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
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#define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
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#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
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#define PT_LEVEL_BITS PT32_LEVEL_BITS
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#define PT_MAX_FULL_LEVELS 2
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#define PT_GUEST_ACCESSED_MASK PT_ACCESSED_MASK
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#define PT_GUEST_DIRTY_MASK PT_DIRTY_MASK
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#define PT_GUEST_DIRTY_SHIFT PT_DIRTY_SHIFT
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#define PT_GUEST_ACCESSED_SHIFT PT_ACCESSED_SHIFT
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#define CMPXCHG cmpxchg
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#elif PTTYPE == PTTYPE_EPT
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#define pt_element_t u64
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#define guest_walker guest_walkerEPT
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#define FNAME(name) ept_##name
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#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
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#define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
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#define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
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#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
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#define PT_LEVEL_BITS PT64_LEVEL_BITS
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#define PT_GUEST_ACCESSED_MASK 0
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#define PT_GUEST_DIRTY_MASK 0
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#define PT_GUEST_DIRTY_SHIFT __using_nonexistent_pte_bit()
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#define PT_GUEST_ACCESSED_SHIFT __using_nonexistent_pte_bit()
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#define CMPXCHG cmpxchg64
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#define PT_MAX_FULL_LEVELS 4
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#else
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#error Invalid PTTYPE value
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#endif
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#define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
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#define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
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/*
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* The guest_walker structure emulates the behavior of the hardware page
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* table walker.
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*/
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struct guest_walker {
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int level;
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unsigned max_level;
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gfn_t table_gfn[PT_MAX_FULL_LEVELS];
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pt_element_t ptes[PT_MAX_FULL_LEVELS];
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pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
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gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
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pt_element_t __user *ptep_user[PT_MAX_FULL_LEVELS];
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bool pte_writable[PT_MAX_FULL_LEVELS];
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unsigned pt_access;
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unsigned pte_access;
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gfn_t gfn;
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struct x86_exception fault;
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};
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static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
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{
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return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
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}
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static inline void FNAME(protect_clean_gpte)(unsigned *access, unsigned gpte)
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{
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unsigned mask;
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/* dirty bit is not supported, so no need to track it */
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if (!PT_GUEST_DIRTY_MASK)
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return;
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BUILD_BUG_ON(PT_WRITABLE_MASK != ACC_WRITE_MASK);
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mask = (unsigned)~ACC_WRITE_MASK;
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/* Allow write access to dirty gptes */
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mask |= (gpte >> (PT_GUEST_DIRTY_SHIFT - PT_WRITABLE_SHIFT)) &
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PT_WRITABLE_MASK;
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*access &= mask;
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}
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static bool FNAME(is_rsvd_bits_set)(struct kvm_mmu *mmu, u64 gpte, int level)
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{
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int bit7 = (gpte >> 7) & 1, low6 = gpte & 0x3f;
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return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) |
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((mmu->bad_mt_xwr & (1ull << low6)) != 0);
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}
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static inline int FNAME(is_present_gpte)(unsigned long pte)
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{
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#if PTTYPE != PTTYPE_EPT
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return is_present_gpte(pte);
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#else
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return pte & 7;
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#endif
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}
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static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
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pt_element_t __user *ptep_user, unsigned index,
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pt_element_t orig_pte, pt_element_t new_pte)
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{
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int npages;
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pt_element_t ret;
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pt_element_t *table;
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struct page *page;
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npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page);
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/* Check if the user is doing something meaningless. */
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if (unlikely(npages != 1))
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return -EFAULT;
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table = kmap_atomic(page);
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ret = CMPXCHG(&table[index], orig_pte, new_pte);
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kunmap_atomic(table);
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kvm_release_page_dirty(page);
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return (ret != orig_pte);
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}
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static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
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struct kvm_mmu_page *sp, u64 *spte,
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u64 gpte)
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{
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if (FNAME(is_rsvd_bits_set)(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
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goto no_present;
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if (!FNAME(is_present_gpte)(gpte))
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goto no_present;
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/* if accessed bit is not supported prefetch non accessed gpte */
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if (PT_GUEST_ACCESSED_MASK && !(gpte & PT_GUEST_ACCESSED_MASK))
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goto no_present;
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return false;
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no_present:
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drop_spte(vcpu->kvm, spte);
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return true;
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}
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static inline unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, u64 gpte)
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{
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unsigned access;
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#if PTTYPE == PTTYPE_EPT
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access = ((gpte & VMX_EPT_WRITABLE_MASK) ? ACC_WRITE_MASK : 0) |
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((gpte & VMX_EPT_EXECUTABLE_MASK) ? ACC_EXEC_MASK : 0) |
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ACC_USER_MASK;
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#else
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access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
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access &= ~(gpte >> PT64_NX_SHIFT);
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#endif
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return access;
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}
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static int FNAME(update_accessed_dirty_bits)(struct kvm_vcpu *vcpu,
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struct kvm_mmu *mmu,
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struct guest_walker *walker,
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int write_fault)
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{
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unsigned level, index;
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pt_element_t pte, orig_pte;
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pt_element_t __user *ptep_user;
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gfn_t table_gfn;
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int ret;
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/* dirty/accessed bits are not supported, so no need to update them */
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if (!PT_GUEST_DIRTY_MASK)
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return 0;
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for (level = walker->max_level; level >= walker->level; --level) {
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pte = orig_pte = walker->ptes[level - 1];
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table_gfn = walker->table_gfn[level - 1];
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ptep_user = walker->ptep_user[level - 1];
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index = offset_in_page(ptep_user) / sizeof(pt_element_t);
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if (!(pte & PT_GUEST_ACCESSED_MASK)) {
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trace_kvm_mmu_set_accessed_bit(table_gfn, index, sizeof(pte));
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pte |= PT_GUEST_ACCESSED_MASK;
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}
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if (level == walker->level && write_fault &&
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!(pte & PT_GUEST_DIRTY_MASK)) {
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trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
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pte |= PT_GUEST_DIRTY_MASK;
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}
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if (pte == orig_pte)
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continue;
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/*
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* If the slot is read-only, simply do not process the accessed
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* and dirty bits. This is the correct thing to do if the slot
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* is ROM, and page tables in read-as-ROM/write-as-MMIO slots
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* are only supported if the accessed and dirty bits are already
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* set in the ROM (so that MMIO writes are never needed).
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*
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* Note that NPT does not allow this at all and faults, since
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* it always wants nested page table entries for the guest
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* page tables to be writable. And EPT works but will simply
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* overwrite the read-only memory to set the accessed and dirty
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* bits.
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*/
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if (unlikely(!walker->pte_writable[level - 1]))
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continue;
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ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index, orig_pte, pte);
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if (ret)
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return ret;
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mark_page_dirty(vcpu->kvm, table_gfn);
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walker->ptes[level] = pte;
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}
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return 0;
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}
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/*
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* Fetch a guest pte for a guest virtual address
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*/
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static int FNAME(walk_addr_generic)(struct guest_walker *walker,
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struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
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gva_t addr, u32 access)
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{
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int ret;
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pt_element_t pte;
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pt_element_t __user *uninitialized_var(ptep_user);
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gfn_t table_gfn;
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unsigned index, pt_access, pte_access, accessed_dirty;
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gpa_t pte_gpa;
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int offset;
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const int write_fault = access & PFERR_WRITE_MASK;
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const int user_fault = access & PFERR_USER_MASK;
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const int fetch_fault = access & PFERR_FETCH_MASK;
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u16 errcode = 0;
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gpa_t real_gpa;
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gfn_t gfn;
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trace_kvm_mmu_pagetable_walk(addr, access);
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retry_walk:
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walker->level = mmu->root_level;
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pte = mmu->get_cr3(vcpu);
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#if PTTYPE == 64
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if (walker->level == PT32E_ROOT_LEVEL) {
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pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3);
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trace_kvm_mmu_paging_element(pte, walker->level);
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if (!FNAME(is_present_gpte)(pte))
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goto error;
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--walker->level;
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}
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#endif
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walker->max_level = walker->level;
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ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
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(mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0);
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accessed_dirty = PT_GUEST_ACCESSED_MASK;
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pt_access = pte_access = ACC_ALL;
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++walker->level;
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do {
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gfn_t real_gfn;
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unsigned long host_addr;
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pt_access &= pte_access;
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--walker->level;
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index = PT_INDEX(addr, walker->level);
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table_gfn = gpte_to_gfn(pte);
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offset = index * sizeof(pt_element_t);
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pte_gpa = gfn_to_gpa(table_gfn) + offset;
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walker->table_gfn[walker->level - 1] = table_gfn;
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walker->pte_gpa[walker->level - 1] = pte_gpa;
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real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
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PFERR_USER_MASK|PFERR_WRITE_MASK);
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if (unlikely(real_gfn == UNMAPPED_GVA))
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goto error;
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real_gfn = gpa_to_gfn(real_gfn);
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host_addr = gfn_to_hva_prot(vcpu->kvm, real_gfn,
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&walker->pte_writable[walker->level - 1]);
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if (unlikely(kvm_is_error_hva(host_addr)))
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goto error;
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ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
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if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte))))
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goto error;
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walker->ptep_user[walker->level - 1] = ptep_user;
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trace_kvm_mmu_paging_element(pte, walker->level);
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if (unlikely(!FNAME(is_present_gpte)(pte)))
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goto error;
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if (unlikely(FNAME(is_rsvd_bits_set)(mmu, pte,
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walker->level))) {
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errcode |= PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
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goto error;
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}
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accessed_dirty &= pte;
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pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
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walker->ptes[walker->level - 1] = pte;
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} while (!is_last_gpte(mmu, walker->level, pte));
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if (unlikely(permission_fault(vcpu, mmu, pte_access, access))) {
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errcode |= PFERR_PRESENT_MASK;
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goto error;
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}
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gfn = gpte_to_gfn_lvl(pte, walker->level);
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gfn += (addr & PT_LVL_OFFSET_MASK(walker->level)) >> PAGE_SHIFT;
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if (PTTYPE == 32 && walker->level == PT_DIRECTORY_LEVEL && is_cpuid_PSE36())
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gfn += pse36_gfn_delta(pte);
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real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn), access);
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if (real_gpa == UNMAPPED_GVA)
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return 0;
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walker->gfn = real_gpa >> PAGE_SHIFT;
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if (!write_fault)
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FNAME(protect_clean_gpte)(&pte_access, pte);
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else
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/*
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* On a write fault, fold the dirty bit into accessed_dirty.
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* For modes without A/D bits support accessed_dirty will be
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* always clear.
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*/
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accessed_dirty &= pte >>
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(PT_GUEST_DIRTY_SHIFT - PT_GUEST_ACCESSED_SHIFT);
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if (unlikely(!accessed_dirty)) {
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ret = FNAME(update_accessed_dirty_bits)(vcpu, mmu, walker, write_fault);
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if (unlikely(ret < 0))
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goto error;
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else if (ret)
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goto retry_walk;
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}
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walker->pt_access = pt_access;
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walker->pte_access = pte_access;
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pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
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__func__, (u64)pte, pte_access, pt_access);
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return 1;
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error:
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errcode |= write_fault | user_fault;
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if (fetch_fault && (mmu->nx ||
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kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)))
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errcode |= PFERR_FETCH_MASK;
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walker->fault.vector = PF_VECTOR;
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walker->fault.error_code_valid = true;
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walker->fault.error_code = errcode;
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#if PTTYPE == PTTYPE_EPT
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/*
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* Use PFERR_RSVD_MASK in error_code to to tell if EPT
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* misconfiguration requires to be injected. The detection is
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* done by is_rsvd_bits_set() above.
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*
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* We set up the value of exit_qualification to inject:
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* [2:0] - Derive from [2:0] of real exit_qualification at EPT violation
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* [5:3] - Calculated by the page walk of the guest EPT page tables
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* [7:8] - Derived from [7:8] of real exit_qualification
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*
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* The other bits are set to 0.
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*/
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if (!(errcode & PFERR_RSVD_MASK)) {
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vcpu->arch.exit_qualification &= 0x187;
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vcpu->arch.exit_qualification |= ((pt_access & pte) & 0x7) << 3;
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}
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#endif
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walker->fault.address = addr;
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walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
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trace_kvm_mmu_walker_error(walker->fault.error_code);
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return 0;
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}
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static int FNAME(walk_addr)(struct guest_walker *walker,
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struct kvm_vcpu *vcpu, gva_t addr, u32 access)
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{
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return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
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access);
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}
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#if PTTYPE != PTTYPE_EPT
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static int FNAME(walk_addr_nested)(struct guest_walker *walker,
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struct kvm_vcpu *vcpu, gva_t addr,
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u32 access)
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{
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return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
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addr, access);
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}
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#endif
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static bool
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FNAME(prefetch_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
|
|
u64 *spte, pt_element_t gpte, bool no_dirty_log)
|
|
{
|
|
unsigned pte_access;
|
|
gfn_t gfn;
|
|
pfn_t pfn;
|
|
|
|
if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
|
|
return false;
|
|
|
|
pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
|
|
|
|
gfn = gpte_to_gfn(gpte);
|
|
pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
|
|
FNAME(protect_clean_gpte)(&pte_access, gpte);
|
|
pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
|
|
no_dirty_log && (pte_access & ACC_WRITE_MASK));
|
|
if (is_error_pfn(pfn))
|
|
return false;
|
|
|
|
/*
|
|
* we call mmu_set_spte() with host_writable = true because
|
|
* pte_prefetch_gfn_to_pfn always gets a writable pfn.
|
|
*/
|
|
mmu_set_spte(vcpu, spte, pte_access, 0, NULL, PT_PAGE_TABLE_LEVEL,
|
|
gfn, pfn, true, true);
|
|
|
|
return true;
|
|
}
|
|
|
|
static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
|
|
u64 *spte, const void *pte)
|
|
{
|
|
pt_element_t gpte = *(const pt_element_t *)pte;
|
|
|
|
FNAME(prefetch_gpte)(vcpu, sp, spte, gpte, false);
|
|
}
|
|
|
|
static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
|
|
struct guest_walker *gw, int level)
|
|
{
|
|
pt_element_t curr_pte;
|
|
gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
|
|
u64 mask;
|
|
int r, index;
|
|
|
|
if (level == PT_PAGE_TABLE_LEVEL) {
|
|
mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
|
|
base_gpa = pte_gpa & ~mask;
|
|
index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
|
|
|
|
r = kvm_read_guest_atomic(vcpu->kvm, base_gpa,
|
|
gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
|
|
curr_pte = gw->prefetch_ptes[index];
|
|
} else
|
|
r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa,
|
|
&curr_pte, sizeof(curr_pte));
|
|
|
|
return r || curr_pte != gw->ptes[level - 1];
|
|
}
|
|
|
|
static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
|
|
u64 *sptep)
|
|
{
|
|
struct kvm_mmu_page *sp;
|
|
pt_element_t *gptep = gw->prefetch_ptes;
|
|
u64 *spte;
|
|
int i;
|
|
|
|
sp = page_header(__pa(sptep));
|
|
|
|
if (sp->role.level > PT_PAGE_TABLE_LEVEL)
|
|
return;
|
|
|
|
if (sp->role.direct)
|
|
return __direct_pte_prefetch(vcpu, sp, sptep);
|
|
|
|
i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
|
|
spte = sp->spt + i;
|
|
|
|
for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
|
|
if (spte == sptep)
|
|
continue;
|
|
|
|
if (is_shadow_present_pte(*spte))
|
|
continue;
|
|
|
|
if (!FNAME(prefetch_gpte)(vcpu, sp, spte, gptep[i], true))
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Fetch a shadow pte for a specific level in the paging hierarchy.
|
|
* If the guest tries to write a write-protected page, we need to
|
|
* emulate this operation, return 1 to indicate this case.
|
|
*/
|
|
static int FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
|
|
struct guest_walker *gw,
|
|
int write_fault, int hlevel,
|
|
pfn_t pfn, bool map_writable, bool prefault)
|
|
{
|
|
struct kvm_mmu_page *sp = NULL;
|
|
struct kvm_shadow_walk_iterator it;
|
|
unsigned direct_access, access = gw->pt_access;
|
|
int top_level, emulate = 0;
|
|
|
|
direct_access = gw->pte_access;
|
|
|
|
top_level = vcpu->arch.mmu.root_level;
|
|
if (top_level == PT32E_ROOT_LEVEL)
|
|
top_level = PT32_ROOT_LEVEL;
|
|
/*
|
|
* Verify that the top-level gpte is still there. Since the page
|
|
* is a root page, it is either write protected (and cannot be
|
|
* changed from now on) or it is invalid (in which case, we don't
|
|
* really care if it changes underneath us after this point).
|
|
*/
|
|
if (FNAME(gpte_changed)(vcpu, gw, top_level))
|
|
goto out_gpte_changed;
|
|
|
|
if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
|
|
goto out_gpte_changed;
|
|
|
|
for (shadow_walk_init(&it, vcpu, addr);
|
|
shadow_walk_okay(&it) && it.level > gw->level;
|
|
shadow_walk_next(&it)) {
|
|
gfn_t table_gfn;
|
|
|
|
clear_sp_write_flooding_count(it.sptep);
|
|
drop_large_spte(vcpu, it.sptep);
|
|
|
|
sp = NULL;
|
|
if (!is_shadow_present_pte(*it.sptep)) {
|
|
table_gfn = gw->table_gfn[it.level - 2];
|
|
sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
|
|
false, access, it.sptep);
|
|
}
|
|
|
|
/*
|
|
* Verify that the gpte in the page we've just write
|
|
* protected is still there.
|
|
*/
|
|
if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
|
|
goto out_gpte_changed;
|
|
|
|
if (sp)
|
|
link_shadow_page(it.sptep, sp, PT_GUEST_ACCESSED_MASK);
|
|
}
|
|
|
|
for (;
|
|
shadow_walk_okay(&it) && it.level > hlevel;
|
|
shadow_walk_next(&it)) {
|
|
gfn_t direct_gfn;
|
|
|
|
clear_sp_write_flooding_count(it.sptep);
|
|
validate_direct_spte(vcpu, it.sptep, direct_access);
|
|
|
|
drop_large_spte(vcpu, it.sptep);
|
|
|
|
if (is_shadow_present_pte(*it.sptep))
|
|
continue;
|
|
|
|
direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
|
|
|
|
sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
|
|
true, direct_access, it.sptep);
|
|
link_shadow_page(it.sptep, sp, PT_GUEST_ACCESSED_MASK);
|
|
}
|
|
|
|
clear_sp_write_flooding_count(it.sptep);
|
|
mmu_set_spte(vcpu, it.sptep, gw->pte_access, write_fault, &emulate,
|
|
it.level, gw->gfn, pfn, prefault, map_writable);
|
|
FNAME(pte_prefetch)(vcpu, gw, it.sptep);
|
|
|
|
return emulate;
|
|
|
|
out_gpte_changed:
|
|
if (sp)
|
|
kvm_mmu_put_page(sp, it.sptep);
|
|
kvm_release_pfn_clean(pfn);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* To see whether the mapped gfn can write its page table in the current
|
|
* mapping.
|
|
*
|
|
* It is the helper function of FNAME(page_fault). When guest uses large page
|
|
* size to map the writable gfn which is used as current page table, we should
|
|
* force kvm to use small page size to map it because new shadow page will be
|
|
* created when kvm establishes shadow page table that stop kvm using large
|
|
* page size. Do it early can avoid unnecessary #PF and emulation.
|
|
*
|
|
* @write_fault_to_shadow_pgtable will return true if the fault gfn is
|
|
* currently used as its page table.
|
|
*
|
|
* Note: the PDPT page table is not checked for PAE-32 bit guest. It is ok
|
|
* since the PDPT is always shadowed, that means, we can not use large page
|
|
* size to map the gfn which is used as PDPT.
|
|
*/
|
|
static bool
|
|
FNAME(is_self_change_mapping)(struct kvm_vcpu *vcpu,
|
|
struct guest_walker *walker, int user_fault,
|
|
bool *write_fault_to_shadow_pgtable)
|
|
{
|
|
int level;
|
|
gfn_t mask = ~(KVM_PAGES_PER_HPAGE(walker->level) - 1);
|
|
bool self_changed = false;
|
|
|
|
if (!(walker->pte_access & ACC_WRITE_MASK ||
|
|
(!is_write_protection(vcpu) && !user_fault)))
|
|
return false;
|
|
|
|
for (level = walker->level; level <= walker->max_level; level++) {
|
|
gfn_t gfn = walker->gfn ^ walker->table_gfn[level - 1];
|
|
|
|
self_changed |= !(gfn & mask);
|
|
*write_fault_to_shadow_pgtable |= !gfn;
|
|
}
|
|
|
|
return self_changed;
|
|
}
|
|
|
|
/*
|
|
* Page fault handler. There are several causes for a page fault:
|
|
* - there is no shadow pte for the guest pte
|
|
* - write access through a shadow pte marked read only so that we can set
|
|
* the dirty bit
|
|
* - write access to a shadow pte marked read only so we can update the page
|
|
* dirty bitmap, when userspace requests it
|
|
* - mmio access; in this case we will never install a present shadow pte
|
|
* - normal guest page fault due to the guest pte marked not present, not
|
|
* writable, or not executable
|
|
*
|
|
* Returns: 1 if we need to emulate the instruction, 0 otherwise, or
|
|
* a negative value on error.
|
|
*/
|
|
static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
|
|
bool prefault)
|
|
{
|
|
int write_fault = error_code & PFERR_WRITE_MASK;
|
|
int user_fault = error_code & PFERR_USER_MASK;
|
|
struct guest_walker walker;
|
|
int r;
|
|
pfn_t pfn;
|
|
int level = PT_PAGE_TABLE_LEVEL;
|
|
int force_pt_level;
|
|
unsigned long mmu_seq;
|
|
bool map_writable, is_self_change_mapping;
|
|
|
|
pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
|
|
|
|
if (unlikely(error_code & PFERR_RSVD_MASK)) {
|
|
r = handle_mmio_page_fault(vcpu, addr, error_code,
|
|
mmu_is_nested(vcpu));
|
|
if (likely(r != RET_MMIO_PF_INVALID))
|
|
return r;
|
|
};
|
|
|
|
r = mmu_topup_memory_caches(vcpu);
|
|
if (r)
|
|
return r;
|
|
|
|
/*
|
|
* Look up the guest pte for the faulting address.
|
|
*/
|
|
r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
|
|
|
|
/*
|
|
* The page is not mapped by the guest. Let the guest handle it.
|
|
*/
|
|
if (!r) {
|
|
pgprintk("%s: guest page fault\n", __func__);
|
|
if (!prefault)
|
|
inject_page_fault(vcpu, &walker.fault);
|
|
|
|
return 0;
|
|
}
|
|
|
|
vcpu->arch.write_fault_to_shadow_pgtable = false;
|
|
|
|
is_self_change_mapping = FNAME(is_self_change_mapping)(vcpu,
|
|
&walker, user_fault, &vcpu->arch.write_fault_to_shadow_pgtable);
|
|
|
|
if (walker.level >= PT_DIRECTORY_LEVEL)
|
|
force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn)
|
|
|| is_self_change_mapping;
|
|
else
|
|
force_pt_level = 1;
|
|
if (!force_pt_level) {
|
|
level = min(walker.level, mapping_level(vcpu, walker.gfn));
|
|
walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
|
|
}
|
|
|
|
mmu_seq = vcpu->kvm->mmu_notifier_seq;
|
|
smp_rmb();
|
|
|
|
if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault,
|
|
&map_writable))
|
|
return 0;
|
|
|
|
if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr,
|
|
walker.gfn, pfn, walker.pte_access, &r))
|
|
return r;
|
|
|
|
/*
|
|
* Do not change pte_access if the pfn is a mmio page, otherwise
|
|
* we will cache the incorrect access into mmio spte.
|
|
*/
|
|
if (write_fault && !(walker.pte_access & ACC_WRITE_MASK) &&
|
|
!is_write_protection(vcpu) && !user_fault &&
|
|
!is_noslot_pfn(pfn)) {
|
|
walker.pte_access |= ACC_WRITE_MASK;
|
|
walker.pte_access &= ~ACC_USER_MASK;
|
|
|
|
/*
|
|
* If we converted a user page to a kernel page,
|
|
* so that the kernel can write to it when cr0.wp=0,
|
|
* then we should prevent the kernel from executing it
|
|
* if SMEP is enabled.
|
|
*/
|
|
if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
|
|
walker.pte_access &= ~ACC_EXEC_MASK;
|
|
}
|
|
|
|
spin_lock(&vcpu->kvm->mmu_lock);
|
|
if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
|
|
goto out_unlock;
|
|
|
|
kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
|
|
make_mmu_pages_available(vcpu);
|
|
if (!force_pt_level)
|
|
transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level);
|
|
r = FNAME(fetch)(vcpu, addr, &walker, write_fault,
|
|
level, pfn, map_writable, prefault);
|
|
++vcpu->stat.pf_fixed;
|
|
kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
|
|
spin_unlock(&vcpu->kvm->mmu_lock);
|
|
|
|
return r;
|
|
|
|
out_unlock:
|
|
spin_unlock(&vcpu->kvm->mmu_lock);
|
|
kvm_release_pfn_clean(pfn);
|
|
return 0;
|
|
}
|
|
|
|
static gpa_t FNAME(get_level1_sp_gpa)(struct kvm_mmu_page *sp)
|
|
{
|
|
int offset = 0;
|
|
|
|
WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL);
|
|
|
|
if (PTTYPE == 32)
|
|
offset = sp->role.quadrant << PT64_LEVEL_BITS;
|
|
|
|
return gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
|
|
}
|
|
|
|
static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
|
|
{
|
|
struct kvm_shadow_walk_iterator iterator;
|
|
struct kvm_mmu_page *sp;
|
|
int level;
|
|
u64 *sptep;
|
|
|
|
vcpu_clear_mmio_info(vcpu, gva);
|
|
|
|
/*
|
|
* No need to check return value here, rmap_can_add() can
|
|
* help us to skip pte prefetch later.
|
|
*/
|
|
mmu_topup_memory_caches(vcpu);
|
|
|
|
if (!VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
|
|
WARN_ON(1);
|
|
return;
|
|
}
|
|
|
|
spin_lock(&vcpu->kvm->mmu_lock);
|
|
for_each_shadow_entry(vcpu, gva, iterator) {
|
|
level = iterator.level;
|
|
sptep = iterator.sptep;
|
|
|
|
sp = page_header(__pa(sptep));
|
|
if (is_last_spte(*sptep, level)) {
|
|
pt_element_t gpte;
|
|
gpa_t pte_gpa;
|
|
|
|
if (!sp->unsync)
|
|
break;
|
|
|
|
pte_gpa = FNAME(get_level1_sp_gpa)(sp);
|
|
pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
|
|
|
|
if (mmu_page_zap_pte(vcpu->kvm, sp, sptep))
|
|
kvm_flush_remote_tlbs(vcpu->kvm);
|
|
|
|
if (!rmap_can_add(vcpu))
|
|
break;
|
|
|
|
if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
|
|
sizeof(pt_element_t)))
|
|
break;
|
|
|
|
FNAME(update_pte)(vcpu, sp, sptep, &gpte);
|
|
}
|
|
|
|
if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
|
|
break;
|
|
}
|
|
spin_unlock(&vcpu->kvm->mmu_lock);
|
|
}
|
|
|
|
static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
|
|
struct x86_exception *exception)
|
|
{
|
|
struct guest_walker walker;
|
|
gpa_t gpa = UNMAPPED_GVA;
|
|
int r;
|
|
|
|
r = FNAME(walk_addr)(&walker, vcpu, vaddr, access);
|
|
|
|
if (r) {
|
|
gpa = gfn_to_gpa(walker.gfn);
|
|
gpa |= vaddr & ~PAGE_MASK;
|
|
} else if (exception)
|
|
*exception = walker.fault;
|
|
|
|
return gpa;
|
|
}
|
|
|
|
#if PTTYPE != PTTYPE_EPT
|
|
static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
|
|
u32 access,
|
|
struct x86_exception *exception)
|
|
{
|
|
struct guest_walker walker;
|
|
gpa_t gpa = UNMAPPED_GVA;
|
|
int r;
|
|
|
|
r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
|
|
|
|
if (r) {
|
|
gpa = gfn_to_gpa(walker.gfn);
|
|
gpa |= vaddr & ~PAGE_MASK;
|
|
} else if (exception)
|
|
*exception = walker.fault;
|
|
|
|
return gpa;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Using the cached information from sp->gfns is safe because:
|
|
* - The spte has a reference to the struct page, so the pfn for a given gfn
|
|
* can't change unless all sptes pointing to it are nuked first.
|
|
*
|
|
* Note:
|
|
* We should flush all tlbs if spte is dropped even though guest is
|
|
* responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
|
|
* and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
|
|
* used by guest then tlbs are not flushed, so guest is allowed to access the
|
|
* freed pages.
|
|
* We set tlbs_dirty to let the notifier know this change and delay the flush
|
|
* until such a case actually happens.
|
|
*/
|
|
static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
|
|
{
|
|
int i, nr_present = 0;
|
|
bool host_writable;
|
|
gpa_t first_pte_gpa;
|
|
|
|
/* direct kvm_mmu_page can not be unsync. */
|
|
BUG_ON(sp->role.direct);
|
|
|
|
first_pte_gpa = FNAME(get_level1_sp_gpa)(sp);
|
|
|
|
for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
|
|
unsigned pte_access;
|
|
pt_element_t gpte;
|
|
gpa_t pte_gpa;
|
|
gfn_t gfn;
|
|
|
|
if (!sp->spt[i])
|
|
continue;
|
|
|
|
pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
|
|
|
|
if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
|
|
sizeof(pt_element_t)))
|
|
return -EINVAL;
|
|
|
|
if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
|
|
vcpu->kvm->tlbs_dirty = true;
|
|
continue;
|
|
}
|
|
|
|
gfn = gpte_to_gfn(gpte);
|
|
pte_access = sp->role.access;
|
|
pte_access &= FNAME(gpte_access)(vcpu, gpte);
|
|
FNAME(protect_clean_gpte)(&pte_access, gpte);
|
|
|
|
if (sync_mmio_spte(vcpu->kvm, &sp->spt[i], gfn, pte_access,
|
|
&nr_present))
|
|
continue;
|
|
|
|
if (gfn != sp->gfns[i]) {
|
|
drop_spte(vcpu->kvm, &sp->spt[i]);
|
|
vcpu->kvm->tlbs_dirty = true;
|
|
continue;
|
|
}
|
|
|
|
nr_present++;
|
|
|
|
host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE;
|
|
|
|
set_spte(vcpu, &sp->spt[i], pte_access,
|
|
PT_PAGE_TABLE_LEVEL, gfn,
|
|
spte_to_pfn(sp->spt[i]), true, false,
|
|
host_writable);
|
|
}
|
|
|
|
return !nr_present;
|
|
}
|
|
|
|
#undef pt_element_t
|
|
#undef guest_walker
|
|
#undef FNAME
|
|
#undef PT_BASE_ADDR_MASK
|
|
#undef PT_INDEX
|
|
#undef PT_LVL_ADDR_MASK
|
|
#undef PT_LVL_OFFSET_MASK
|
|
#undef PT_LEVEL_BITS
|
|
#undef PT_MAX_FULL_LEVELS
|
|
#undef gpte_to_gfn
|
|
#undef gpte_to_gfn_lvl
|
|
#undef CMPXCHG
|
|
#undef PT_GUEST_ACCESSED_MASK
|
|
#undef PT_GUEST_DIRTY_MASK
|
|
#undef PT_GUEST_DIRTY_SHIFT
|
|
#undef PT_GUEST_ACCESSED_SHIFT
|