![Greg Ungerer](/assets/img/avatar_default.png)
The ColdFire 528x family of CPUs does not have an MBAR register, so don't define its peripheral addresses relative to one. Its internal peripherals are relative to the IPSBAR register, so make sure to use that. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
321 lines
7.3 KiB
C
321 lines
7.3 KiB
C
/***************************************************************************/
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/*
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* linux/arch/m68knommu/platform/528x/config.c
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*
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* Sub-architcture dependant initialization code for the Freescale
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* 5280, 5281 and 5282 CPUs.
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*
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* Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com)
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* Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
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*/
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/***************************************************************************/
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/spi/spi.h>
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#include <linux/gpio.h>
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#include <asm/machdep.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#include <asm/mcfuart.h>
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#include <asm/mcfqspi.h>
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/***************************************************************************/
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static struct mcf_platform_uart m528x_uart_platform[] = {
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{
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.mapbase = MCFUART_BASE1,
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.irq = MCFINT_VECBASE + MCFINT_UART0,
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},
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{
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.mapbase = MCFUART_BASE2,
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.irq = MCFINT_VECBASE + MCFINT_UART0 + 1,
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},
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{
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.mapbase = MCFUART_BASE3,
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.irq = MCFINT_VECBASE + MCFINT_UART0 + 2,
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},
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{ },
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};
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static struct platform_device m528x_uart = {
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.name = "mcfuart",
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.id = 0,
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.dev.platform_data = m528x_uart_platform,
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};
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static struct resource m528x_fec_resources[] = {
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{
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.start = MCFFEC_BASE,
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.end = MCFFEC_BASE + MCFFEC_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = 64 + 23,
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.end = 64 + 23,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = 64 + 27,
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.end = 64 + 27,
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.flags = IORESOURCE_IRQ,
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},
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{
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.start = 64 + 29,
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.end = 64 + 29,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device m528x_fec = {
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.name = "fec",
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.id = 0,
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.num_resources = ARRAY_SIZE(m528x_fec_resources),
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.resource = m528x_fec_resources,
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};
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#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
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static struct resource m528x_qspi_resources[] = {
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{
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.start = MCFQSPI_IOBASE,
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.end = MCFQSPI_IOBASE + MCFQSPI_IOSIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MCFINT_VECBASE + MCFINT_QSPI,
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.end = MCFINT_VECBASE + MCFINT_QSPI,
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.flags = IORESOURCE_IRQ,
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},
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};
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#define MCFQSPI_CS0 147
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#define MCFQSPI_CS1 148
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#define MCFQSPI_CS2 149
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#define MCFQSPI_CS3 150
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static int m528x_cs_setup(struct mcfqspi_cs_control *cs_control)
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{
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int status;
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status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
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if (status) {
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pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
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goto fail0;
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}
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status = gpio_direction_output(MCFQSPI_CS0, 1);
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if (status) {
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pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
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goto fail1;
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}
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status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
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if (status) {
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pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
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goto fail1;
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}
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status = gpio_direction_output(MCFQSPI_CS1, 1);
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if (status) {
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pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
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goto fail2;
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}
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status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
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if (status) {
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pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
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goto fail2;
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}
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status = gpio_direction_output(MCFQSPI_CS2, 1);
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if (status) {
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pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
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goto fail3;
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}
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status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
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if (status) {
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pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
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goto fail3;
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}
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status = gpio_direction_output(MCFQSPI_CS3, 1);
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if (status) {
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pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
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goto fail4;
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}
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return 0;
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fail4:
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gpio_free(MCFQSPI_CS3);
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fail3:
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gpio_free(MCFQSPI_CS2);
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fail2:
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gpio_free(MCFQSPI_CS1);
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fail1:
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gpio_free(MCFQSPI_CS0);
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fail0:
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return status;
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}
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static void m528x_cs_teardown(struct mcfqspi_cs_control *cs_control)
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{
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gpio_free(MCFQSPI_CS3);
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gpio_free(MCFQSPI_CS2);
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gpio_free(MCFQSPI_CS1);
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gpio_free(MCFQSPI_CS0);
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}
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static void m528x_cs_select(struct mcfqspi_cs_control *cs_control,
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u8 chip_select, bool cs_high)
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{
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gpio_set_value(MCFQSPI_CS0 + chip_select, cs_high);
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}
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static void m528x_cs_deselect(struct mcfqspi_cs_control *cs_control,
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u8 chip_select, bool cs_high)
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{
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gpio_set_value(MCFQSPI_CS0 + chip_select, !cs_high);
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}
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static struct mcfqspi_cs_control m528x_cs_control = {
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.setup = m528x_cs_setup,
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.teardown = m528x_cs_teardown,
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.select = m528x_cs_select,
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.deselect = m528x_cs_deselect,
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};
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static struct mcfqspi_platform_data m528x_qspi_data = {
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.bus_num = 0,
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.num_chipselect = 4,
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.cs_control = &m528x_cs_control,
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};
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static struct platform_device m528x_qspi = {
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.name = "mcfqspi",
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.id = 0,
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.num_resources = ARRAY_SIZE(m528x_qspi_resources),
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.resource = m528x_qspi_resources,
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.dev.platform_data = &m528x_qspi_data,
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};
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static void __init m528x_qspi_init(void)
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{
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/* setup Port QS for QSPI with gpio CS control */
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__raw_writeb(0x07, MCFGPIO_PQSPAR);
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}
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#endif /* defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE) */
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static struct platform_device *m528x_devices[] __initdata = {
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&m528x_uart,
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&m528x_fec,
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#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
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&m528x_qspi,
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#endif
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};
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/***************************************************************************/
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static void __init m528x_uart_init_line(int line, int irq)
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{
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u8 port;
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if ((line < 0) || (line > 2))
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return;
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/* make sure PUAPAR is set for UART0 and UART1 */
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if (line < 2) {
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port = readb(MCF5282_GPIO_PUAPAR);
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port |= (0x03 << (line * 2));
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writeb(port, MCF5282_GPIO_PUAPAR);
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}
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}
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static void __init m528x_uarts_init(void)
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{
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const int nrlines = ARRAY_SIZE(m528x_uart_platform);
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int line;
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for (line = 0; (line < nrlines); line++)
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m528x_uart_init_line(line, m528x_uart_platform[line].irq);
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}
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/***************************************************************************/
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static void __init m528x_fec_init(void)
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{
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u16 v16;
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/* Set multi-function pins to ethernet mode for fec0 */
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v16 = readw(MCF_IPSBAR + 0x100056);
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writew(v16 | 0xf00, MCF_IPSBAR + 0x100056);
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writeb(0xc0, MCF_IPSBAR + 0x100058);
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}
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/***************************************************************************/
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static void m528x_cpu_reset(void)
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{
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local_irq_disable();
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__raw_writeb(MCF_RCR_SWRESET, MCF_IPSBAR + MCF_RCR);
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}
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/***************************************************************************/
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#ifdef CONFIG_WILDFIRE
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void wildfire_halt(void)
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{
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writeb(0, 0x30000007);
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writeb(0x2, 0x30000007);
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}
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#endif
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#ifdef CONFIG_WILDFIREMOD
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void wildfiremod_halt(void)
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{
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printk(KERN_INFO "WildFireMod hibernating...\n");
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/* Set portE.5 to Digital IO */
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MCF5282_GPIO_PEPAR &= ~(1 << (5 * 2));
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/* Make portE.5 an output */
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MCF5282_GPIO_DDRE |= (1 << 5);
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/* Now toggle portE.5 from low to high */
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MCF5282_GPIO_PORTE &= ~(1 << 5);
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MCF5282_GPIO_PORTE |= (1 << 5);
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printk(KERN_EMERG "Failed to hibernate. Halting!\n");
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}
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#endif
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void __init config_BSP(char *commandp, int size)
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{
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#ifdef CONFIG_WILDFIRE
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mach_halt = wildfire_halt;
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#endif
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#ifdef CONFIG_WILDFIREMOD
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mach_halt = wildfiremod_halt;
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#endif
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}
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/***************************************************************************/
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static int __init init_BSP(void)
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{
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mach_reset = m528x_cpu_reset;
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m528x_uarts_init();
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m528x_fec_init();
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#if defined(CONFIG_SPI_COLDFIRE_QSPI) || defined(CONFIG_SPI_COLDFIRE_QSPI_MODULE)
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m528x_qspi_init();
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#endif
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platform_add_devices(m528x_devices, ARRAY_SIZE(m528x_devices));
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return 0;
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}
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arch_initcall(init_BSP);
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/***************************************************************************/
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