2012-09-24 02:09:33 -06:00
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/*
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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*
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2012-10-02 03:22:10 -06:00
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* Configuration settings for the Freescale i.MX6Q SabreAuto board.
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2012-09-24 02:09:33 -06:00
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*
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2013-07-08 01:37:19 -06:00
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* SPDX-License-Identifier: GPL-2.0+
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2012-09-24 02:09:33 -06:00
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*/
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#ifndef __MX6QSABREAUTO_CONFIG_H
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#define __MX6QSABREAUTO_CONFIG_H
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#define CONFIG_MACH_TYPE 3529
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#define CONFIG_MXC_UART_BASE UART4_BASE
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2012-09-26 05:37:01 -06:00
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#define CONFIG_CONSOLE_DEV "ttymxc3"
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2012-10-02 03:22:10 -06:00
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#define CONFIG_MMCROOT "/dev/mmcblk0p2"
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2012-09-24 02:09:33 -06:00
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#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)
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2013-01-21 16:11:21 -07:00
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/* USB Configs */
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#define CONFIG_CMD_USB
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#define CONFIG_USB_EHCI
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#define CONFIG_USB_EHCI_MX6
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#define CONFIG_USB_STORAGE
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#define CONFIG_USB_HOST_ETHER
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#define CONFIG_USB_ETHER_ASIX
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2013-10-10 16:27:59 -06:00
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
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2013-01-21 16:11:21 -07:00
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#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
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#define CONFIG_MXC_USB_FLAGS 0
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2014-10-30 04:53:49 -06:00
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#define CONFIG_PCA953X
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#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
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2013-06-04 01:00:15 -06:00
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#include "mx6sabre_common.h"
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2012-09-26 05:37:01 -06:00
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2014-11-14 06:27:23 -07:00
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#undef CONFIG_SYS_NO_FLASH
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#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
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#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024)
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
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#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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2012-12-30 07:14:59 -07:00
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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#if defined(CONFIG_ENV_IS_IN_MMC)
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#endif
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2013-05-13 12:01:12 -06:00
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/* I2C Configs */
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#define CONFIG_CMD_I2C
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2013-09-21 10:13:36 -06:00
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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2015-09-21 14:43:38 -06:00
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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2015-03-20 11:20:40 -06:00
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#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
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2013-05-13 12:01:12 -06:00
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#define CONFIG_SYS_I2C_SPEED 100000
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2014-11-11 23:02:05 -07:00
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/* NAND flash command */
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_NAND_TRIMFFS
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/* NAND stuff */
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#define CONFIG_NAND_MXS
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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/* DMA stuff, needed for GPMI/MXS NAND support */
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#define CONFIG_APBH_DMA
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#define CONFIG_APBH_DMA_BURST
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#define CONFIG_APBH_DMA_BURST8
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2014-11-06 01:29:02 -07:00
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/* PMIC */
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#define CONFIG_POWER
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#define CONFIG_POWER_I2C
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#define CONFIG_POWER_PFUZE100
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#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
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2012-09-24 02:09:33 -06:00
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#endif /* __MX6QSABREAUTO_CONFIG_H */
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