arm/km: add support for portl2 board
This adds support for the keymile Kirkwood BEC portl2 board. This board relies on the km_arm (km_kirkwood) BEC. The egiga driver is configured for a 100M full-duplex, A/N off connnection to the backplane. This board has always ethernet present, because it is connected to the marvell switch similar to mgcoge3un. The reset_phy functionality is also the same to mgcoge3un. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Heiko Schocher <hs@denx.de>utp
Valentin Longchamp
Albert ARIBAUD
parent
83b40c3146
commit
01fa4e8cde
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@ -734,6 +734,7 @@ Sergey Lapin <slapin@ossfans.org>
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Valentin Longchamp <valentin.longchamp@keymile.com>
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km_kirkwood ARM926EJS (Kirkwood SoC)
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portl2 ARM926EJS (Kirkwood SoC)
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Nishanth Menon <nm@ti.com>
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1
MAKEALL
1
MAKEALL
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@ -364,6 +364,7 @@ LIST_ARM9=" \
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openrd_base \
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openrd_client \
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openrd_ultimate \
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portl2 \
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rd6281a \
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sbc2410x \
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scb9328 \
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@ -130,10 +130,12 @@ int startup_allowed(void)
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return 1;
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return 0;
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}
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#endif
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#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2))
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/*
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* mgcoge3un has always ethernet present. Its connected to the 6061 switch
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* and provides ICNev and piggy4 connections.
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* These two boards have always ethernet present. Its connected to the mv
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* switch.
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*/
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int ethernet_present(void)
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{
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@ -335,7 +337,7 @@ void dram_init_banksize(void)
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}
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}
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#if defined(CONFIG_MGCOGE3UN)
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#if (defined(CONFIG_MGCOGE3UN)|defined(CONFIG_PORTL2))
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#define PHY_LED_SEL 0x18
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#define PHY_LED0_LINK (0x5)
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@ -118,6 +118,7 @@ davinci_sonata arm arm926ejs sonata davinci
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km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_DISABLE_PCI
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km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood
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mgcoge3un arm arm926ejs km_arm keymile kirkwood
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portl2 arm arm926ejs km_arm keymile kirkwood
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guruplug arm arm926ejs - Marvell kirkwood
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mv88f6281gtw_ge arm arm926ejs - Marvell kirkwood
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openrd_base arm arm926ejs openrd Marvell kirkwood openrd:BOARD_IS_OPENRD_BASE
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@ -0,0 +1,81 @@
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/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Prafulla Wadaskar <prafulla@marvell.com>
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*
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* (C) Copyright 2009
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2010-2011
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* Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com.
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* Valentin Longchamp, Keymile AG Bern, valentin.longchamp@keymile.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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/* for linking errors see
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* http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */
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#ifndef _CONFIG_PORTL2_H
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#define _CONFIG_PORTL2_H
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/* include common defines/options for all arm based Keymile boards */
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#include "km/km_arm.h"
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/*
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* Version number information
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*/
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#define CONFIG_IDENT_STRING "\nKeymile Port-L2"
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#define CONFIG_HOSTNAME portl2
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#define CONFIG_PORTL2
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#define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/
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#define KM_ENV_BUS "pca9544a:70:a" /* I2C2 (Mux-Port 2)*/
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/*
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* portl2 has a fixed link to the XMPP backplane
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* with 100MB full duplex and autoneg off, for this
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* reason we have to change the default settings
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*/
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#define PORT_SERIAL_CONTROL_VALUE ( \
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MVGBE_FORCE_LINK_PASS | \
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MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
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MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
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MVGBE_ADV_NO_FLOW_CTRL | \
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MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
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MVGBE_FORCE_BP_MODE_NO_JAM | \
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(1 << 9) /* Reserved bit has to be 1 */ | \
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MVGBE_DO_NOT_FORCE_LINK_FAIL | \
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MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
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MVGBE_DTE_ADV_0 | \
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MVGBE_MIIPHY_MAC_MODE | \
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MVGBE_AUTO_NEG_NO_CHANGE | \
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MVGBE_MAX_RX_PACKET_1552BYTE | \
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MVGBE_CLR_EXT_LOOPBACK | \
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MVGBE_SET_FULL_DUPLEX_MODE | \
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MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
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MVGBE_SET_GMII_SPEED_TO_10_100 |\
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MVGBE_SET_MII_SPEED_TO_100)
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/*
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* portl2 does use the PCIe Port0
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*/
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#define CONFIG_KIRKWOOD_PCIE_INIT
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#endif /* _CONFIG_PORTL2_H */
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