MLK-16034-02: enable GPMI NAND driver for i.MX8
enable the GPMI NAND driver for i.MX8, the major changes - register defination for i.mx8 - Makefile change for misc.c - DMA structure must be 32bit address Signed-off-by: Han Xu <han.xu@nxp.com> (cherry picked from commit 474c4270108551647c7064a23abdc2e11d7f37ab)zero-sugar
parent
d297f33f47
commit
029cce25cc
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@ -6,6 +6,7 @@
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*
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* Based on code from LTIB:
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* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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@ -54,7 +55,7 @@ enum {
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MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
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MXS_MAX_DMA_CHANNELS,
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};
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#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
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#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M))
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enum {
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MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
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MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
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@ -96,13 +97,13 @@ enum {
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#define MXS_DMA_DESC_BYTES_OFFSET 16
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struct mxs_dma_cmd {
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unsigned long next;
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unsigned long data;
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uint32_t next;
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uint32_t data;
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union {
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dma_addr_t address;
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unsigned long alternate;
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uint32_t address;
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uint32_t alternate;
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};
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unsigned long pio_words[DMA_PIO_WORDS];
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uint32_t pio_words[DMA_PIO_WORDS];
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};
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/*
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@ -118,7 +119,7 @@ struct mxs_dma_cmd {
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struct mxs_dma_desc {
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struct mxs_dma_cmd cmd;
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unsigned int flags;
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dma_addr_t address;
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uint32_t address;
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void *buffer;
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struct list_head node;
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} __aligned(MXS_DMA_ALIGNMENT);
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@ -6,6 +6,7 @@
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*
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* Based on code from LTIB:
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* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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@ -96,7 +97,7 @@ struct mxs_apbh_regs {
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mxs_reg_32(hw_apbh_version)
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};
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#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
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#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M))
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struct mxs_apbh_regs {
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mxs_reg_32(hw_apbh_ctrl0)
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mxs_reg_32(hw_apbh_ctrl1)
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@ -275,7 +276,7 @@ struct mxs_apbh_regs {
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#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800
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#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000
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#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000
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#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
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#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M))
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#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
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#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001
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#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002
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@ -391,7 +392,7 @@ struct mxs_apbh_regs {
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#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000
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#endif
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#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
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#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M))
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#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
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#endif
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@ -6,6 +6,7 @@
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*
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* Based on code from LTIB:
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* Copyright 2008-2010, 2016 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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@ -127,7 +128,7 @@ struct mxs_bch_regs {
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#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24
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#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16)
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#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16
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#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
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#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M))
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#define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11)
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#define BCH_FLASHLAYOUT0_ECC0_OFFSET 11
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#else
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@ -158,7 +159,7 @@ struct mxs_bch_regs {
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#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16)
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#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16
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#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
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#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M))
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#define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11)
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#define BCH_FLASHLAYOUT1_ECCN_OFFSET 11
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#else
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@ -58,6 +58,7 @@ ifeq ($(SOC),$(filter $(SOC),imx8))
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obj-$(CONFIG_HAVE_SC_FIRMWARE) += sci/
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obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
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obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
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obj-y += misc.o
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endif
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ifneq ($(CONFIG_SPL_BUILD),y)
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obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
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@ -6,6 +6,7 @@
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*
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* Based on code from LTIB:
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* Copyright (C) 2010-2016 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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@ -88,7 +89,7 @@ void mxs_dma_flush_desc(struct mxs_dma_desc *desc)
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uint32_t addr;
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uint32_t size;
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addr = (uint32_t)desc;
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addr = (uintptr_t)desc;
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size = roundup(sizeof(struct mxs_dma_desc), MXS_DMA_ALIGNMENT);
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flush_dcache_range(addr, addr + size);
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@ -215,8 +216,8 @@ static int mxs_dma_reset(int channel)
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#if defined(CONFIG_MX23)
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uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set);
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uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET;
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#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
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uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_channel_ctrl_set);
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#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M))
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uint32_t setreg = (uintptr_t)(&apbh_regs->hw_apbh_channel_ctrl_set);
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uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET;
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#endif
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@ -224,7 +225,7 @@ static int mxs_dma_reset(int channel)
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if (ret)
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return ret;
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writel(1 << (channel + offset), setreg);
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writel(1 << (channel + offset), (uintptr_t)setreg);
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return 0;
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}
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@ -31,7 +31,7 @@
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#define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
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#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
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#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
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#if (defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M))
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#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
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#else
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#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
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@ -88,21 +88,21 @@ static int galois_field = 13;
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#ifndef CONFIG_SYS_DCACHE_OFF
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static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
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{
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uint32_t addr = (uint32_t)info->data_buf;
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uint32_t addr = (uintptr_t)info->data_buf;
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flush_dcache_range(addr, addr + info->data_buf_size);
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}
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static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
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{
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uint32_t addr = (uint32_t)info->data_buf;
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uint32_t addr = (uintptr_t)info->data_buf;
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invalidate_dcache_range(addr, addr + info->data_buf_size);
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}
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static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
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{
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uint32_t addr = (uint32_t)info->cmd_buf;
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uint32_t addr = (uintptr_t)info->cmd_buf;
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flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
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}
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int max_ecc_strength_supported;
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/* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
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if (is_mx6sx() || is_mx7() || is_imx8m())
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if (is_mx6sx() || is_mx7() || is_imx8() || is_imx8m())
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max_ecc_strength_supported = 62;
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else
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max_ecc_strength_supported = 40;
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@ -805,7 +805,7 @@ static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
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if (status[i] == 0xff) {
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if (is_mx6dqp() || is_mx7() ||
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is_mx6ul() || is_imx8m())
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is_mx6ul() || is_imx8() || is_imx8m())
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if (readl(&bch_regs->hw_bch_debug1))
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flag = 1;
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continue;
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struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
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uint32_t tmp;
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/* calculate ecc_strength, bbm_chunk, eec_for meta, if necessary */
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mxs_nand_get_ecc_strength(mtd);
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/* Set erase threshold to ecc strength for mx6ul, mx6qp and mx7 */
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if (is_mx6dqp() || is_mx7() ||
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is_mx6ul() || is_imx8m())
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is_mx6ul() || is_imx8() || is_imx8m())
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writel(BCH_MODE_ERASE_THRESHOLD(ecc_strength),
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&bch_regs->hw_bch_mode);
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