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mmc: dw_mmc: support the DDR mode 

Support the DDR mode at dw-mmc controller

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
utp
Jaehoon Chung 2014-05-16 13:59:55 +09:00 committed by Minkyu Kang
parent d22e3d46a9
commit 045bdcd0b2
2 changed files with 13 additions and 2 deletions
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12
drivers/mmc/dw_mmc.c
View File

@ -284,8 +284,8 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
static void dwmci_set_ios(struct mmc *mmc)
{
struct dwmci_host *host = mmc->priv;
u32 ctype;
struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
u32 ctype, regs;
debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock);
@ -304,6 +304,14 @@ static void dwmci_set_ios(struct mmc *mmc)
dwmci_writel(host, DWMCI_CTYPE, ctype);
regs = dwmci_readl(host, DWMCI_UHS_REG);
if (mmc->card_caps & MMC_MODE_DDR_52MHz)
regs |= DWMCI_DDR_MODE;
else
regs &= DWMCI_DDR_MODE;
dwmci_writel(host, DWMCI_UHS_REG, regs);
if (host->clksel)
host->clksel(host);
}

3
include/dwmmc.h
View File

@ -123,6 +123,9 @@
#define DWMCI_BMOD_IDMAC_FB (1 << 1)
#define DWMCI_BMOD_IDMAC_EN (1 << 7)
/* UHS register */
#define DWMCI_DDR_MODE (1 << 16)
/* quirks */
#define DWMCI_QUIRK_DISABLE_SMU (1 << 0)