Wolfgang Denk
parent
3b71755249
commit
04e5ae7931
54
README
54
README
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@ -1177,7 +1177,7 @@ The following options need to be configured:
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or CONFIG_VIDEO_SED13806_16BPP
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CONFIG_FSL_DIU_FB
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Enable the Freescale DIU video driver. Reference boards for
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Enable the Freescale DIU video driver. Reference boards for
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SOCs that have a DIU should define this macro to enable DIU
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support, and should also define these other macros:
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@ -2289,44 +2289,44 @@ FIT uImage format:
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kernel. Needed for UBI support.
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- SPL framework
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CONFIG_SPL
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Enable building of SPL globally.
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CONFIG_SPL
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Enable building of SPL globally.
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CONFIG_SPL_TEXT_BASE
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TEXT_BASE for linking the SPL binary.
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CONFIG_SPL_TEXT_BASE
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TEXT_BASE for linking the SPL binary.
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CONFIG_SPL_LDSCRIPT
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LDSCRIPT for linking the SPL binary.
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CONFIG_SPL_LDSCRIPT
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LDSCRIPT for linking the SPL binary.
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CONFIG_SPL_LIBCOMMON_SUPPORT
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Support for common/libcommon.o in SPL binary
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CONFIG_SPL_LIBCOMMON_SUPPORT
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Support for common/libcommon.o in SPL binary
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CONFIG_SPL_LIBDISK_SUPPORT
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Support for disk/libdisk.o in SPL binary
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CONFIG_SPL_LIBDISK_SUPPORT
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Support for disk/libdisk.o in SPL binary
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CONFIG_SPL_I2C_SUPPORT
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Support for drivers/i2c/libi2c.o in SPL binary
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CONFIG_SPL_I2C_SUPPORT
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Support for drivers/i2c/libi2c.o in SPL binary
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CONFIG_SPL_GPIO_SUPPORT
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Support for drivers/gpio/libgpio.o in SPL binary
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CONFIG_SPL_GPIO_SUPPORT
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Support for drivers/gpio/libgpio.o in SPL binary
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CONFIG_SPL_MMC_SUPPORT
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Support for drivers/mmc/libmmc.o in SPL binary
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CONFIG_SPL_MMC_SUPPORT
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Support for drivers/mmc/libmmc.o in SPL binary
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CONFIG_SPL_SERIAL_SUPPORT
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Support for drivers/serial/libserial.o in SPL binary
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CONFIG_SPL_SERIAL_SUPPORT
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Support for drivers/serial/libserial.o in SPL binary
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CONFIG_SPL_SPI_FLASH_SUPPORT
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Support for drivers/mtd/spi/libspi_flash.o in SPL binary
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CONFIG_SPL_SPI_FLASH_SUPPORT
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Support for drivers/mtd/spi/libspi_flash.o in SPL binary
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CONFIG_SPL_SPI_SUPPORT
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Support for drivers/spi/libspi.o in SPL binary
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CONFIG_SPL_SPI_SUPPORT
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Support for drivers/spi/libspi.o in SPL binary
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CONFIG_SPL_FAT_SUPPORT
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Support for fs/fat/libfat.o in SPL binary
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CONFIG_SPL_FAT_SUPPORT
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Support for fs/fat/libfat.o in SPL binary
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CONFIG_SPL_LIBGENERIC_SUPPORT
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Support for lib/libgeneric.o in SPL binary
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CONFIG_SPL_LIBGENERIC_SUPPORT
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Support for lib/libgeneric.o in SPL binary
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Modem Support:
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--------------
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@ -75,11 +75,9 @@ void at91_serial2_hw_init(void)
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writel(1 << ATMEL_ID_USART2, &pmc->pcer);
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}
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void at91_seriald_hw_init(void)
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{
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at91_set_a_periph(AT91_PIO_PORTA, 30, PUP); /* DRXD */
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at91_set_a_periph(AT91_PIO_PORTA, 31, 1); /* DTXD */
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/* writing SYS to PCER has no effect on AT91RM9200 */
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}
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@ -104,7 +104,6 @@ static u32 at91_pll_rate(u32 freq, u32 reg)
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return freq;
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}
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int at91_clock_init(unsigned long main_clock)
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{
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unsigned freq, mckr;
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@ -157,4 +156,3 @@ int at91_clock_init(unsigned long main_clock)
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return 0;
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}
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@ -40,4 +40,3 @@ int arch_cpu_init(void)
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{
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return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
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}
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@ -34,7 +34,7 @@ endif
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COBJS-$(CONFIG_SPL_BUILD) += foo.o
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#ifdef CONFIG_SPL_BUILD
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foo();
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foo();
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#endif
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@ -39,4 +39,3 @@ The method for updating
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3. add new structures for SoC access
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4. Convert arch, driver and boards file to new SoC
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5. remove legacy code, if all boards and drives are ready
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@ -101,22 +101,22 @@ This steps are done automagically if you do a "make all"
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Structure of this binary (Example for the cam_enc_4xx board with a NAND
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page size = 0x800):
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offset : 0x00000 | 0x800 | 0x3800
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content: UBL | nand_spl | u-boot code
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Header | code |
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offset : 0x00000 | 0x800 | 0x3800
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content: UBL | nand_spl | u-boot code
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Header | code |
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The NAND layout looks for example like this:
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(Example for the cam_enc_4xx board with a NAND page size = 0x800, block
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size = 0x20000 and CONFIG_SYS_NROF_UBL_HEADER 5):
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offset : 0x80000 | 0xa0000 | 0xa3000
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content: UBL | nand_spl | u-boot code
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Header | code |
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^ ^
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^ 0xa0000 = CONFIG_SYS_NROF_UBL_HEADER * 0x20000
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^
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0x80000 = Block 4 * 0x20000
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offset : 0x80000 | 0xa0000 | 0xa3000
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content: UBL | nand_spl | u-boot code
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Header | code |
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^ ^
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^ 0xa0000 = CONFIG_SYS_NROF_UBL_HEADER * 0x20000
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^
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0x80000 = Block 4 * 0x20000
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If the cpu starts in NAND boot mode, it checks the UBL descriptor
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starting with block 1 (page 0). When a valid UBL signature is found,
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@ -132,7 +132,7 @@ read and processed.
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Once the user-specified start-up conditions are set, the RBL copies the
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nand_spl into ARM internal RAM, starting at address 0x0000: 0020.
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^^^^
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^^^^
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The nand_spl code itself now does necessary intializations, and at least,
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copies the u-boot code from NAND into RAM, and jumps to it ...
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@ -116,7 +116,7 @@ Bus 002 Device 010: ID 0b95:7720 ASIX Electronics Corp. AX88772
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If you look at drivers/usb/eth/asix.c you will see this line within the
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supported device list, so we know this adapter is supported.
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{ 0x0b95, 0x7720 }, /* Trendnet TU2-ET100 V3.0R */
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{ 0x0b95, 0x7720 }, /* Trendnet TU2-ET100 V3.0R */
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If your adapter is not listed there is a still a chance that it will
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work. Try looking up the manufacturer of the chip inside your adapter.
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@ -144,8 +144,8 @@ To enable USB Host Ethernet in U-Boot, your platform must of course
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support USB with CONFIG_CMD_USB enabled and working. You will need to
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add some config settings to your board header file:
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#define CONFIG_USB_HOST_ETHER /* Enable USB Ethernet adapters */
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#define CONFIG_USB_ETHER_ASIX /* Asix, or whatever driver(s) you want */
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#define CONFIG_USB_HOST_ETHER /* Enable USB Ethernet adapters */
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#define CONFIG_USB_ETHER_ASIX /* Asix, or whatever driver(s) you want */
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As with built-in networking, you will also want to enable some network
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commands, for example:
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@ -168,9 +168,9 @@ You can also set the default IP address of your board and the server
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as well as the default file to load when a 'bootp' command is issued.
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All of these can be obtained from the bootp server if not set.
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#define CONFIG_IPADDR 10.0.0.2 (replace with your value)
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#define CONFIG_SERVERIP 10.0.0.1 (replace with your value)
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#define CONFIG_BOOTFILE uImage
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#define CONFIG_IPADDR 10.0.0.2 (replace with your value)
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#define CONFIG_SERVERIP 10.0.0.1 (replace with your value)
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#define CONFIG_BOOTFILE uImage
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The 'usb start' command should identify the adapter something like this:
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@ -200,9 +200,9 @@ TFTP from server 172.22.72.144; our IP address is 172.22.73.81
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Filename '/tftpboot/uImage-sjg-seaboard-261347'.
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Load address: 0x40c000
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Loading: #################################################################
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#################################################################
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#################################################################
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################################################
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#################################################################
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#################################################################
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################################################
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done
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Bytes transferred = 3557464 (364858 hex)
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CrOS>
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@ -27,13 +27,11 @@
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#include <asm/arch/hardware.h>
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#include <asm/arch/davinci_misc.h>
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static struct gpio_registry {
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int is_registered;
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char name[GPIO_NAME_SIZE];
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} gpio_registry[MAX_NUM_GPIOS];
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#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
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static const struct pinmux_config gpio_pinmux[] = {
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@ -183,8 +181,6 @@ static const struct pinmux_config gpio_pinmux[] = {
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{ pinmux(18), 8, 2 },
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};
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int gpio_request(int gp, const char *label)
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{
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if (gp >= MAX_NUM_GPIOS)
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@ -202,13 +198,11 @@ int gpio_request(int gp, const char *label)
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return 0;
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}
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void gpio_free(int gp)
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{
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gpio_registry[gp].is_registered = 0;
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}
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void gpio_toggle_value(int gp)
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{
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struct davinci_gpio *bank;
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@ -217,7 +211,6 @@ void gpio_toggle_value(int gp)
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gpio_set_value(gp, !gpio_get_value(gp));
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}
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int gpio_direction_input(int gp)
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{
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struct davinci_gpio *bank;
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@ -227,7 +220,6 @@ int gpio_direction_input(int gp)
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return 0;
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}
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int gpio_direction_output(int gp, int value)
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{
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struct davinci_gpio *bank;
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@ -238,7 +230,6 @@ int gpio_direction_output(int gp, int value)
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return 0;
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}
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int gpio_get_value(int gp)
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{
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struct davinci_gpio *bank;
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@ -249,7 +240,6 @@ int gpio_get_value(int gp)
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return ip ? 1 : 0;
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}
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void gpio_set_value(int gp, int value)
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{
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struct davinci_gpio *bank;
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@ -262,7 +252,6 @@ void gpio_set_value(int gp, int value)
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bank->clr_data = 1U << GPIO_BIT(gp);
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}
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void gpio_info(void)
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{
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int gp, dir, val;
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@ -127,8 +127,6 @@
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MDIO_DEVS_DTEXS | \
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MDIO_DEVS_AN)
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/* Control register 2. */
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#define MDIO_PMA_CTRL2_TYPE 0x000f /* PMA/PMD type selection */
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#define MDIO_PMA_CTRL2_10GBCX4 0x0000 /* 10GBASE-CX4 type */
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