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x86: Create a common header for Intel register access 

There are several blocks of registers that are accessed from all over the
code on Intel CPUs. These don't currently have their own driver and it is
not clear whether having a driver makes sense.

An example is the Memory Controller Hub (MCH). We map it to a known location
on some Intel chips (mostly those without FSP - Firmware Support Package).

Add a new header file for these registers, and move MCH into it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
utp
Simon Glass 2016-03-11 22:06:55 -07:00 committed by Bin Meng
parent 9e66506d33
commit 06d336cca2
6 changed files with 22 additions and 6 deletions
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1
arch/x86/cpu/ivybridge/cpu.c
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@ -17,6 +17,7 @@
#include <fdtdec.h>
#include <pch.h>
#include <asm/cpu.h>
#include <asm/intel_regs.h>
#include <asm/io.h>
#include <asm/lapic.h>
#include <asm/microcode.h>

1
arch/x86/cpu/ivybridge/gma.c
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@ -12,6 +12,7 @@
#include <errno.h>
#include <fdtdec.h>
#include <pci_rom.h>
#include <asm/intel_regs.h>
#include <asm/io.h>
#include <asm/mtrr.h>
#include <asm/pci.h>

5
arch/x86/cpu/ivybridge/northbridge.c
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@ -12,6 +12,7 @@
#include <asm/msr.h>
#include <asm/acpi.h>
#include <asm/cpu.h>
#include <asm/intel_regs.h>
#include <asm/io.h>
#include <asm/pci.h>
#include <asm/processor.h>
@ -167,8 +168,8 @@ static void sandybridge_setup_northbridge_bars(struct udevice *dev)
debug("Setting up static registers\n");
dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1);
dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
dm_pci_write_config32(dev, MCHBAR, DEFAULT_MCHBAR | 1);
dm_pci_write_config32(dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32);
dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1);
dm_pci_write_config32(dev, MCHBAR + 4, (0LL + MCH_BASE_ADDRESS) >> 32);
/* 64MB - busses 0-63 */
dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5);
dm_pci_write_config32(dev, PCIEXBAR + 4,

3
arch/x86/cpu/ivybridge/sdram.c
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@ -23,6 +23,7 @@
#include <asm/processor.h>
#include <asm/gpio.h>
#include <asm/global_data.h>
#include <asm/intel_regs.h>
#include <asm/mrccache.h>
#include <asm/mtrr.h>
#include <asm/pci.h>
@ -682,7 +683,7 @@ int dram_init(void)
{
struct pei_data pei_data __aligned(8) = {
.pei_version = PEI_VERSION,
.mchbar = DEFAULT_MCHBAR,
.mchbar = MCH_BASE_ADDRESS,
.dmibar = DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_PCIE_ECAM_BASE,

3
arch/x86/include/asm/arch-ivybridge/sandybridge.h
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@ -38,7 +38,6 @@
#define IED_SIZE 0x400000
/* Northbridge BARs */
#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
#define DEFAULT_RCBABASE 0xfed1c000
@ -97,8 +96,6 @@
/*
* MCHBAR
*/
#define MCHBAR_REG(reg) (DEFAULT_MCHBAR + (reg))
#define SSKPD 0x5d14 /* 16bit (scratchpad) */
#define BIOS_RESET_CPL 0x5da8 /* 8bit */

15
arch/x86/include/asm/intel_regs.h 100644
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@ -0,0 +1,15 @@
/*
* Copyright (c) 2016 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ASM_INTEL_REGS_H
#define __ASM_INTEL_REGS_H
/* Access the memory-controller hub */
#define MCH_BASE_ADDRESS 0xfed10000
#define MCH_BASE_SIZE 0x8000
#define MCHBAR_REG(reg) (MCH_BASE_ADDRESS + (reg))
#endif