powerpc: ppc4xx: remove sbc405 support
This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>utp
Masahiro Yamada
Tom Rini
parent
242836a893
commit
0e03059396
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@ -8,9 +8,6 @@ choice
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prompt "Target select"
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optional
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config TARGET_SBC405
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bool "Support sbc405"
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config TARGET_T3CORP
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bool "Support t3corp"
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@ -174,7 +171,6 @@ source "board/gdsys/intip/Kconfig"
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source "board/mosaixtech/icon/Kconfig"
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source "board/mpl/mip405/Kconfig"
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source "board/mpl/pip405/Kconfig"
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source "board/sbc405/Kconfig"
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source "board/t3corp/Kconfig"
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source "board/xes/xpedite1000/Kconfig"
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source "board/xilinx/ml507/Kconfig"
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@ -1,9 +0,0 @@
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if TARGET_SBC405
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config SYS_BOARD
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default "sbc405"
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config SYS_CONFIG_NAME
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default "sbc405"
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endif
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@ -1,6 +0,0 @@
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SBC405 BOARD
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#M: -
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S: Maintained
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F: board/sbc405/
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F: include/configs/sbc405.h
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F: configs/sbc405_defconfig
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@ -1,8 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = sbc405.o strataflash.o
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@ -1,91 +0,0 @@
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/*
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* (C) Copyright 2001
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <command.h>
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#include <malloc.h>
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#include <spd_sdram.h>
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int board_early_init_f (void)
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{
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive
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* IRQ 16 405GP internally generated; active low; level sensitive
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* IRQ 17-24 RESERVED
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* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
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* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
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* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
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* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
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* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
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* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
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* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
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*/
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mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtdcr(UIC0ER, 0x00000000); /* disable all ints */
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mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
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mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
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mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
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mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
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mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
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/*
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* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
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*/
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mtebc (EBC0_CFG, 0xa8400000);
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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int misc_init_f (void)
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{
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return 0; /* dummy implementation */
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}
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int misc_init_r (void)
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{
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return (0);
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}
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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char str[64];
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int i = getenv_f("serial#", str, sizeof(str));
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puts ("Board: ");
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if (i == -1) {
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puts ("### No HW ID - assuming sbc405");
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} else {
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puts(str);
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}
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putc ('\n');
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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int testdram (void)
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{
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/* TODO: XXX XXX XXX */
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printf ("test: 64 MB - ok\n");
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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@ -1,774 +0,0 @@
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/*
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* (C) Copyright 2002
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* Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/processor.h>
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#undef DEBUG_FLASH
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/*
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* This file implements a Common Flash Interface (CFI) driver for ppcboot.
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* The width of the port and the width of the chips are determined at initialization.
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* These widths are used to calculate the address for access CFI data structures.
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* It has been tested on an Intel Strataflash implementation.
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*
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* References
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* JEDEC Standard JESD68 - Common Flash Interface (CFI)
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* JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
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* Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
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* Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
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*
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* TODO
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* Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
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* Add support for other command sets Use the PRI and ALT to determine command set
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* Verify erase and program timeouts.
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*/
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#define FLASH_CMD_CFI 0x98
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#define FLASH_CMD_READ_ID 0x90
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#define FLASH_CMD_RESET 0xff
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#define FLASH_CMD_BLOCK_ERASE 0x20
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#define FLASH_CMD_ERASE_CONFIRM 0xD0
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#define FLASH_CMD_WRITE 0x40
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#define FLASH_CMD_PROTECT 0x60
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#define FLASH_CMD_PROTECT_SET 0x01
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#define FLASH_CMD_PROTECT_CLEAR 0xD0
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#define FLASH_CMD_CLEAR_STATUS 0x50
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#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
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#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
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#define FLASH_STATUS_DONE 0x80
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#define FLASH_STATUS_ESS 0x40
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#define FLASH_STATUS_ECLBS 0x20
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#define FLASH_STATUS_PSLBS 0x10
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#define FLASH_STATUS_VPENS 0x08
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#define FLASH_STATUS_PSS 0x04
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#define FLASH_STATUS_DPS 0x02
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#define FLASH_STATUS_R 0x01
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#define FLASH_STATUS_PROTECT 0x01
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#define FLASH_OFFSET_CFI 0x55
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#define FLASH_OFFSET_CFI_RESP 0x10
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#define FLASH_OFFSET_WTOUT 0x1F
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#define FLASH_OFFSET_WBTOUT 0x20
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#define FLASH_OFFSET_ETOUT 0x21
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#define FLASH_OFFSET_CETOUT 0x22
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#define FLASH_OFFSET_WMAX_TOUT 0x23
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#define FLASH_OFFSET_WBMAX_TOUT 0x24
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#define FLASH_OFFSET_EMAX_TOUT 0x25
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#define FLASH_OFFSET_CEMAX_TOUT 0x26
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#define FLASH_OFFSET_SIZE 0x27
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#define FLASH_OFFSET_INTERFACE 0x28
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#define FLASH_OFFSET_BUFFER_SIZE 0x2A
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#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
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#define FLASH_OFFSET_ERASE_REGIONS 0x2D
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#define FLASH_OFFSET_PROTECT 0x02
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#define FLASH_OFFSET_USER_PROTECTION 0x85
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#define FLASH_OFFSET_INTEL_PROTECTION 0x81
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#define FLASH_MAN_CFI 0x01000000
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typedef union {
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unsigned char c;
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unsigned short w;
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unsigned long l;
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} cfiword_t;
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typedef union {
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unsigned char * cp;
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unsigned short *wp;
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unsigned long *lp;
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} cfiptr_t;
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#define NUM_ERASE_REGIONS 4
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
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/*-----------------------------------------------------------------------
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* Functions
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*/
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static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
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static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
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static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
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static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
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static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
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static int flash_detect_cfi(flash_info_t * info);
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static ulong flash_get_size (ulong base, int banknum);
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static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
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static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
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#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
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#endif
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/*-----------------------------------------------------------------------
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* create an address based on the offset and the port width
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*/
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inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
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{
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return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
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}
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/*-----------------------------------------------------------------------
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* read a character at a port width address
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*/
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inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
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{
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uchar *cp;
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cp = flash_make_addr(info, 0, offset);
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return (cp[info->portwidth - 1]);
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}
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/*-----------------------------------------------------------------------
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* read a short word by swapping for ppc format.
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*/
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ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset)
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{
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uchar * addr;
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addr = flash_make_addr(info, sect, offset);
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return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
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}
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/*-----------------------------------------------------------------------
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* read a long word by picking the least significant byte of each maiximum
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* port size word. Swap for ppc format.
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*/
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ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
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{
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uchar * addr;
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addr = flash_make_addr(info, sect, offset);
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return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
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(addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
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}
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/*-----------------------------------------------------------------------
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*/
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unsigned long flash_init (void)
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{
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unsigned long size;
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int i;
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unsigned long address;
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/* The flash is positioned back to back, with the demultiplexing of the chip
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* based on the A24 address line.
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*
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*/
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address = CONFIG_SYS_FLASH_BASE;
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size = 0;
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/* Init: no FLASHes known */
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for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
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flash_info[i].flash_id = FLASH_UNKNOWN;
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size += flash_info[i].size = flash_get_size(address, i);
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address += CONFIG_SYS_FLASH_INCREMENT;
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if (flash_info[0].flash_id == FLASH_UNKNOWN) {
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printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
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flash_info[0].size, flash_info[i].size<<20);
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}
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}
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#if 0 /* test-only */
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/* Monitor protection ON by default */
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#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
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for(i=0; flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1; i++)
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(void)flash_real_protect(&flash_info[0], i, 1);
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#endif
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#else
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/* monitor protection ON by default */
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flash_protect (FLAG_PROTECT_SET,
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- CONFIG_SYS_MONITOR_LEN,
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- 1, &flash_info[1]);
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#endif
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return (size);
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}
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/*-----------------------------------------------------------------------
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*/
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int flash_erase (flash_info_t *info, int s_first, int s_last)
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{
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int rcode = 0;
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int prot;
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int sect;
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if( info->flash_id != FLASH_MAN_CFI) {
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printf ("Can't erase unknown flash type - aborted\n");
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return 1;
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}
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if ((s_first < 0) || (s_first > s_last)) {
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printf ("- no sectors to erase\n");
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return 1;
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}
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prot = 0;
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for (sect=s_first; sect<=s_last; ++sect) {
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if (info->protect[sect]) {
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prot++;
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}
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}
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if (prot) {
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printf ("- Warning: %d protected sectors will not be erased!\n",
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prot);
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} else {
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printf ("\n");
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}
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for (sect = s_first; sect<=s_last; sect++) {
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if (info->protect[sect] == 0) { /* not protected */
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flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
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flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
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flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
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if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
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rcode = 1;
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} else
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printf(".");
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}
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}
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printf (" done\n");
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return rcode;
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info (flash_info_t *info)
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{
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int i;
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if (info->flash_id != FLASH_MAN_CFI) {
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printf ("missing or unknown FLASH type\n");
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return;
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}
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printf("CFI conformant FLASH (%d x %d)",
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(info->portwidth << 3 ), (info->chipwidth << 3 ));
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printf (" Size: %ld MB in %d Sectors\n",
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info->size >> 20, info->sector_count);
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printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
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info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
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printf (" Sector Start Addresses:");
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for (i=0; i<info->sector_count; ++i) {
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#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
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int k;
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int size;
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int erased;
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volatile unsigned long *flash;
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/*
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* Check if whole sector is erased
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*/
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if (i != (info->sector_count-1))
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size = info->start[i+1] - info->start[i];
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else
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size = info->start[0] + info->size - info->start[i];
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erased = 1;
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flash = (volatile unsigned long *)info->start[i];
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size = size >> 2; /* divide by 4 for longword access */
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for (k=0; k<size; k++)
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{
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if (*flash++ != 0xffffffff)
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{
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erased = 0;
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break;
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}
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}
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if ((i % 5) == 0)
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printf ("\n ");
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/* print empty and read-only info */
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printf (" %08lX%s%s",
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info->start[i],
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erased ? " E" : " ",
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info->protect[i] ? "RO " : " ");
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#else
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if ((i % 5) == 0)
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printf ("\n ");
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printf (" %08lX%s",
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info->start[i],
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info->protect[i] ? " (RO)" : " ");
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#endif
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}
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printf ("\n");
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return;
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}
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/*-----------------------------------------------------------------------
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* Copy memory to flash, returns:
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* 0 - OK
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* 1 - write timeout
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* 2 - Flash not erased
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*/
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int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
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{
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ulong wp;
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ulong cp;
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int aln;
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cfiword_t cword;
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int i, rc;
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/* get lower aligned address */
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wp = (addr & ~(info->portwidth - 1));
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/* handle unaligned start */
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if((aln = addr - wp) != 0) {
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cword.l = 0;
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cp = wp;
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for(i=0;i<aln; ++i, ++cp)
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flash_add_byte(info, &cword, (*(uchar *)cp));
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for(; (i< info->portwidth) && (cnt > 0) ; i++) {
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flash_add_byte(info, &cword, *src++);
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cnt--;
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cp++;
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}
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for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
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flash_add_byte(info, &cword, (*(uchar *)cp));
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if((rc = flash_write_cfiword(info, wp, cword)) != 0)
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return rc;
|
||||
wp = cp;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
||||
while(cnt >= info->portwidth) {
|
||||
i = info->buffer_size > cnt? cnt: info->buffer_size;
|
||||
if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
|
||||
return rc;
|
||||
wp += i;
|
||||
src += i;
|
||||
cnt -=i;
|
||||
}
|
||||
#else
|
||||
/* handle the aligned part */
|
||||
while(cnt >= info->portwidth) {
|
||||
cword.l = 0;
|
||||
for(i = 0; i < info->portwidth; i++) {
|
||||
flash_add_byte(info, &cword, *src++);
|
||||
}
|
||||
if((rc = flash_write_cfiword(info, wp, cword)) != 0)
|
||||
return rc;
|
||||
wp += info->portwidth;
|
||||
cnt -= info->portwidth;
|
||||
}
|
||||
#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
|
||||
if (cnt == 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
cword.l = 0;
|
||||
for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
|
||||
flash_add_byte(info, &cword, *src++);
|
||||
--cnt;
|
||||
}
|
||||
for (; i<info->portwidth; ++i, ++cp) {
|
||||
flash_add_byte(info, & cword, (*(uchar *)cp));
|
||||
}
|
||||
|
||||
return flash_write_cfiword(info, wp, cword);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
int flash_real_protect(flash_info_t *info, long sector, int prot)
|
||||
{
|
||||
int retcode = 0;
|
||||
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
|
||||
if(prot)
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
|
||||
else
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
|
||||
|
||||
if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
|
||||
prot?"protect":"unprotect")) == 0) {
|
||||
|
||||
info->protect[sector] = prot;
|
||||
/* Intel's unprotect unprotects all locking */
|
||||
if(prot == 0) {
|
||||
int i;
|
||||
for(i = 0 ; i<info->sector_count; i++) {
|
||||
if(info->protect[i])
|
||||
flash_real_protect(info, i, 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return retcode;
|
||||
}
|
||||
/*-----------------------------------------------------------------------
|
||||
* wait for XSR.7 to be set. Time out with an error if it does not.
|
||||
* This routine does not set the flash to read-array mode.
|
||||
*/
|
||||
static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
|
||||
{
|
||||
ulong start;
|
||||
|
||||
/* Wait for command completion */
|
||||
start = get_timer (0);
|
||||
while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
|
||||
if (get_timer(start) > info->erase_blk_tout) {
|
||||
printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
|
||||
return ERR_TIMOUT;
|
||||
}
|
||||
}
|
||||
return ERR_OK;
|
||||
}
|
||||
/*-----------------------------------------------------------------------
|
||||
* Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
|
||||
* This routine sets the flash to read-array mode.
|
||||
*/
|
||||
static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
|
||||
{
|
||||
int retcode;
|
||||
retcode = flash_status_check(info, sector, tout, prompt);
|
||||
if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
|
||||
retcode = ERR_INVAL;
|
||||
printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
|
||||
if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
|
||||
printf("Command Sequence Error.\n");
|
||||
} else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
|
||||
printf("Block Erase Error.\n");
|
||||
retcode = ERR_NOT_ERASED;
|
||||
} else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
|
||||
printf("Locking Error\n");
|
||||
}
|
||||
if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
|
||||
printf("Block locked.\n");
|
||||
retcode = ERR_PROTECTED;
|
||||
}
|
||||
if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
|
||||
printf("Vpp Low Error.\n");
|
||||
}
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
|
||||
return retcode;
|
||||
}
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
|
||||
{
|
||||
switch(info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
cword->c = c;
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
cword->w = (cword->w << 8) | c;
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
cword->l = (cword->l << 8) | c;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* make a proper sized command based on the port and chip widths
|
||||
*/
|
||||
static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
|
||||
{
|
||||
int i;
|
||||
uchar *cp = (uchar *)cmdbuf;
|
||||
for(i=0; i< info->portwidth; i++)
|
||||
*cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
|
||||
}
|
||||
|
||||
/*
|
||||
* Write a proper sized command to the correct address
|
||||
*/
|
||||
static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
|
||||
{
|
||||
|
||||
volatile cfiptr_t addr;
|
||||
cfiword_t cword;
|
||||
addr.cp = flash_make_addr(info, sect, offset);
|
||||
flash_make_cmd(info, cmd, &cword);
|
||||
switch(info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
*addr.cp = cword.c;
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
*addr.wp = cword.w;
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
*addr.lp = cword.l;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
|
||||
{
|
||||
cfiptr_t cptr;
|
||||
cfiword_t cword;
|
||||
int retval;
|
||||
cptr.cp = flash_make_addr(info, sect, offset);
|
||||
flash_make_cmd(info, cmd, &cword);
|
||||
switch(info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
retval = (cptr.cp[0] == cword.c);
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
retval = (cptr.wp[0] == cword.w);
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
retval = (cptr.lp[0] == cword.l);
|
||||
break;
|
||||
default:
|
||||
retval = 0;
|
||||
break;
|
||||
}
|
||||
return retval;
|
||||
}
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
|
||||
{
|
||||
cfiptr_t cptr;
|
||||
cfiword_t cword;
|
||||
int retval;
|
||||
cptr.cp = flash_make_addr(info, sect, offset);
|
||||
flash_make_cmd(info, cmd, &cword);
|
||||
switch(info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
retval = ((cptr.cp[0] & cword.c) == cword.c);
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
retval = ((cptr.wp[0] & cword.w) == cword.w);
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
retval = ((cptr.lp[0] & cword.l) == cword.l);
|
||||
break;
|
||||
default:
|
||||
retval = 0;
|
||||
break;
|
||||
}
|
||||
return retval;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* detect if flash is compatible with the Common Flash Interface (CFI)
|
||||
* http://www.jedec.org/download/search/jesd68.pdf
|
||||
*
|
||||
*/
|
||||
static int flash_detect_cfi(flash_info_t * info)
|
||||
{
|
||||
|
||||
for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
|
||||
info->portwidth <<= 1) {
|
||||
for(info->chipwidth =FLASH_CFI_BY8;
|
||||
info->chipwidth <= info->portwidth;
|
||||
info->chipwidth <<= 1) {
|
||||
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
|
||||
flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
|
||||
if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
|
||||
flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
|
||||
flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
/*
|
||||
* The following code cannot be run from FLASH!
|
||||
*
|
||||
*/
|
||||
static ulong flash_get_size (ulong base, int banknum)
|
||||
{
|
||||
flash_info_t * info = &flash_info[banknum];
|
||||
int i, j;
|
||||
int sect_cnt;
|
||||
unsigned long sector;
|
||||
unsigned long tmp;
|
||||
int size_ratio;
|
||||
uchar num_erase_regions;
|
||||
int erase_region_size;
|
||||
int erase_region_count;
|
||||
|
||||
info->start[0] = base;
|
||||
|
||||
if(flash_detect_cfi(info)){
|
||||
#ifdef DEBUG_FLASH
|
||||
printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
|
||||
#endif
|
||||
size_ratio = info->portwidth / info->chipwidth;
|
||||
num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
|
||||
#ifdef DEBUG_FLASH
|
||||
printf("found %d erase regions\n", num_erase_regions);
|
||||
#endif
|
||||
sect_cnt = 0;
|
||||
sector = base;
|
||||
for(i = 0 ; i < num_erase_regions; i++) {
|
||||
if(i > NUM_ERASE_REGIONS) {
|
||||
printf("%d erase regions found, only %d used\n",
|
||||
num_erase_regions, NUM_ERASE_REGIONS);
|
||||
break;
|
||||
}
|
||||
tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
|
||||
erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
|
||||
tmp >>= 16;
|
||||
erase_region_count = (tmp & 0xffff) +1;
|
||||
for(j = 0; j< erase_region_count; j++) {
|
||||
info->start[sect_cnt] = sector;
|
||||
sector += (erase_region_size * size_ratio);
|
||||
info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
|
||||
sect_cnt++;
|
||||
}
|
||||
}
|
||||
|
||||
info->sector_count = sect_cnt;
|
||||
/* multiply the size by the number of chips */
|
||||
info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
|
||||
info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
|
||||
tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
|
||||
info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
|
||||
tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
|
||||
info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
|
||||
tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
|
||||
info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
|
||||
info->flash_id = FLASH_MAN_CFI;
|
||||
}
|
||||
|
||||
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
|
||||
return(info->size);
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
|
||||
{
|
||||
|
||||
cfiptr_t cptr;
|
||||
int flag;
|
||||
|
||||
cptr.cp = (uchar *)dest;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
switch(info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
flag = ((cptr.cp[0] & cword.c) == cword.c);
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
flag = ((cptr.wp[0] & cword.w) == cword.w);
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
flag = ((cptr.lp[0] & cword.l) == cword.l);
|
||||
break;
|
||||
default:
|
||||
return 2;
|
||||
}
|
||||
if(!flag)
|
||||
return 2;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
|
||||
flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
|
||||
|
||||
switch(info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
cptr.cp[0] = cword.c;
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
cptr.wp[0] = cword.w;
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
cptr.lp[0] = cword.l;
|
||||
break;
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if(flag)
|
||||
enable_interrupts();
|
||||
|
||||
return flash_full_status_check(info, 0, info->write_tout, "write");
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
||||
|
||||
/* loop through the sectors from the highest address
|
||||
* when the passed address is greater or equal to the sector address
|
||||
* we have a match
|
||||
*/
|
||||
static int find_sector(flash_info_t *info, ulong addr)
|
||||
{
|
||||
int sector;
|
||||
for(sector = info->sector_count - 1; sector >= 0; sector--) {
|
||||
if(addr >= info->start[sector])
|
||||
break;
|
||||
}
|
||||
return sector;
|
||||
}
|
||||
|
||||
static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
|
||||
{
|
||||
|
||||
int sector;
|
||||
int cnt;
|
||||
int retcode;
|
||||
volatile cfiptr_t src;
|
||||
volatile cfiptr_t dst;
|
||||
|
||||
src.cp = cp;
|
||||
dst.cp = (uchar *)dest;
|
||||
sector = find_sector(info, dest);
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
|
||||
if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
|
||||
"write to buffer")) == ERR_OK) {
|
||||
switch(info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
cnt = len;
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
cnt = len >> 1;
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
cnt = len >> 2;
|
||||
break;
|
||||
default:
|
||||
return ERR_INVAL;
|
||||
break;
|
||||
}
|
||||
flash_write_cmd(info, sector, 0, (uchar)cnt-1);
|
||||
while(cnt-- > 0) {
|
||||
switch(info->portwidth) {
|
||||
case FLASH_CFI_8BIT:
|
||||
*dst.cp++ = *src.cp++;
|
||||
break;
|
||||
case FLASH_CFI_16BIT:
|
||||
*dst.wp++ = *src.wp++;
|
||||
break;
|
||||
case FLASH_CFI_32BIT:
|
||||
*dst.lp++ = *src.lp++;
|
||||
break;
|
||||
default:
|
||||
return ERR_INVAL;
|
||||
break;
|
||||
}
|
||||
}
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
|
||||
retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
|
||||
"buffer write");
|
||||
}
|
||||
flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
|
||||
return retcode;
|
||||
}
|
||||
#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
CONFIG_PPC=y
|
||||
CONFIG_4xx=y
|
||||
CONFIG_TARGET_SBC405=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
|
|
@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
|
|||
|
||||
Board Arch CPU Commit Removed Last known maintainer/contact
|
||||
=================================================================================================
|
||||
sbc405 powerpc ppc4xx - -
|
||||
pcs440ep powerpc ppc4xx - - Stefan Roese <sr@denx.de>
|
||||
p3p440 powerpc ppc4xx - - Stefan Roese <sr@denx.de>
|
||||
lwmon5 powerpc ppc4xx - - Stefan Roese <sr@denx.de>
|
||||
|
|
|
|||
|
|
@ -1,252 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
|
||||
#define CONFIG_SBC405 1 /* ...on a WR SBC405 board */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
|
||||
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
|
||||
|
||||
#define CONFIG_BAUDRATE 9600
|
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot for the sbc405;echo;echo Type \"? or help\" to get on-line help;echo"
|
||||
|
||||
#define CONFIG_RAMBOOT \
|
||||
"setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
|
||||
"bootm ffc00000 ffca0000"
|
||||
#define CONFIG_NFSBOOT \
|
||||
"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
|
||||
"bootm ffc00000"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
#define CONFIG_BOOTCOMMAND "version;echo;tftpboot ${loadaddr} ${loadfile};bootvx" /* autoboot command */
|
||||
|
||||
|
||||
#define CONFIG_PPC4xx_EMAC
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_PHY_ADDR 0 /* PHY address */
|
||||
#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"bootargs=emac(0,0)host:/T221ppc/target/config/sbc405/vxWorks.st " \
|
||||
"e=192.168.193.102:ffffffe0 h=192.168.193.100 u=target pw=hello " \
|
||||
"f=0x08 tn=sbc405 o=emac \0" \
|
||||
"env_startaddr=FF000000\0" \
|
||||
"env_endaddr=FF03FFFF\0" \
|
||||
"loadfile=vxWorks.st\0" \
|
||||
"loadaddr=0x01000000\0" \
|
||||
"net_load=tftpboot ${loadaddr} ${loadfile}\0" \
|
||||
"uboot_startaddr=FFFC0000\0" \
|
||||
"uboot_endaddr=FFFFFFFF\0" \
|
||||
"update=tftp ${loadaddr} u-boot.bin;" \
|
||||
"protect off ${uboot_startaddr} ${uboot_endaddr};" \
|
||||
"era ${uboot_startaddr} ${uboot_endaddr};" \
|
||||
"cp.b ${loadaddr} ${uboot_startaddr} ${filesize};" \
|
||||
"protect on ${uboot_startaddr} ${uboot_endaddr}\0" \
|
||||
"zapenv=protect off ${env_startaddr} ${env_endaddr};" \
|
||||
"era ${env_startaddr} ${env_endaddr};" \
|
||||
"protect on ${env_startaddr} ${env_endaddr}\0"
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#define CONFIG_CMD_BSP
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_SDRAM
|
||||
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
|
||||
|
||||
#define CONFIG_IPADDR 192.168.193.102
|
||||
#define CONFIG_NETMASK 255.255.255.224
|
||||
#define CONFIG_SERVERIP 192.168.193.119
|
||||
#define CONFIG_GATEWAYIP 192.168.193.97
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
|
||||
#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
|
||||
|
||||
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
|
||||
#define CONFIG_SYS_BASE_BAUD 691200
|
||||
|
||||
/* The following table includes the supported baudrates */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
|
||||
57600, 115200, 230400, 460800, 921600 }
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
||||
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */
|
||||
|
||||
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
|
||||
|
||||
#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
|
||||
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_PPC4XX
|
||||
#define CONFIG_SYS_I2C_PPC4XX_CH0
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
|
||||
#define PCI_HOST_FORCE 1 /* configure as pci host */
|
||||
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
|
||||
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
|
||||
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
/* resource configuration */
|
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
|
||||
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0408 /* PCI Device ID: PMC-405 */
|
||||
#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
|
||||
#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
|
||||
#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
|
||||
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
|
||||
#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
|
||||
#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
|
||||
#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_MONITOR_BASE 0xFFFC0000
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFF000000
|
||||
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
|
||||
#define CONFIG_SYS_FLASH_INCREMENT 0x01000000
|
||||
#undef CONFIG_SYS_FLASH_PROTECTION /* don't use hardware protection */
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment Variable setup
|
||||
*/
|
||||
#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* starting right at the beginning */
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
|
||||
#define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
|
||||
#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup
|
||||
*/
|
||||
#define FLASH0_BA CONFIG_SYS_FLASH_BASE /* FLASH 0 Base Address */
|
||||
|
||||
/* Memory Bank 0 (Flash Bank 0) initialization */
|
||||
#define CONFIG_SYS_EBC_PB0AP 0x92015480
|
||||
#define CONFIG_SYS_EBC_PB0CR FLASH0_BA | 0x9C000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=32bit*/
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in data cache)
|
||||
*/
|
||||
|
||||
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
|
||||
#define CONFIG_SYS_TEMP_STACK_OCM 1
|
||||
|
||||
/* On Chip Memory location */
|
||||
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
|
||||
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for Serial Presence Detect EEPROM address
|
||||
* (to get SDRAM settings)
|
||||
*/
|
||||
#define SPD_EEPROM_ADDRESS 0x50
|
||||
#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue