tegra: Add EMC support for optimal memory timings
Add support for setting up the memory controller parameters. Boards can set up an appropriate table in the device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>utp
Jimmy Zhang
Albert ARIBAUD
parent
1d5dba604c
commit
0e35ad053f
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@ -34,6 +34,7 @@ LIB = $(obj)lib$(SOC).o
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SOBJS := lowlevel_init.o
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COBJS-y := ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
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COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
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COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
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COBJS := $(COBJS-y)
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@ -0,0 +1,286 @@
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/*
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* Copyright (c) 2011 The Chromium OS Authors.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <fdtdec.h>
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#include <asm/io.h>
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#include <asm/arch/ap20.h>
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#include <asm/arch/apb_misc.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/emc.h>
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#include <asm/arch/tegra2.h>
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/*
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* The EMC registers have shadow registers. When the EMC clock is updated
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* in the clock controller, the shadow registers are copied to the active
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* registers, allowing glitchless memory bus frequency changes.
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* This function updates the shadow registers for a new clock frequency,
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* and relies on the clock lock on the emc clock to avoid races between
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* multiple frequency changes
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*/
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/*
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* This table defines the ordering of the registers provided to
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* tegra_set_mmc()
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* TODO: Convert to fdt version once available
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*/
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static const unsigned long emc_reg_addr[TEGRA_EMC_NUM_REGS] = {
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0x2c, /* RC */
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0x30, /* RFC */
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0x34, /* RAS */
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0x38, /* RP */
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0x3c, /* R2W */
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0x40, /* W2R */
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0x44, /* R2P */
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0x48, /* W2P */
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0x4c, /* RD_RCD */
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0x50, /* WR_RCD */
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0x54, /* RRD */
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0x58, /* REXT */
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0x5c, /* WDV */
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0x60, /* QUSE */
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0x64, /* QRST */
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0x68, /* QSAFE */
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0x6c, /* RDV */
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0x70, /* REFRESH */
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0x74, /* BURST_REFRESH_NUM */
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0x78, /* PDEX2WR */
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0x7c, /* PDEX2RD */
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0x80, /* PCHG2PDEN */
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0x84, /* ACT2PDEN */
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0x88, /* AR2PDEN */
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0x8c, /* RW2PDEN */
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0x90, /* TXSR */
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0x94, /* TCKE */
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0x98, /* TFAW */
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0x9c, /* TRPAB */
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0xa0, /* TCLKSTABLE */
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0xa4, /* TCLKSTOP */
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0xa8, /* TREFBW */
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0xac, /* QUSE_EXTRA */
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0x114, /* FBIO_CFG6 */
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0xb0, /* ODT_WRITE */
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0xb4, /* ODT_READ */
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0x104, /* FBIO_CFG5 */
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0x2bc, /* CFG_DIG_DLL */
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0x2c0, /* DLL_XFORM_DQS */
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0x2c4, /* DLL_XFORM_QUSE */
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0x2e0, /* ZCAL_REF_CNT */
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0x2e4, /* ZCAL_WAIT_CNT */
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0x2a8, /* AUTO_CAL_INTERVAL */
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0x2d0, /* CFG_CLKTRIM_0 */
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0x2d4, /* CFG_CLKTRIM_1 */
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0x2d8, /* CFG_CLKTRIM_2 */
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};
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struct emc_ctlr *emc_get_controller(const void *blob)
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{
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fdt_addr_t addr;
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int node;
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node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_EMC);
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if (node > 0) {
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addr = fdtdec_get_addr(blob, node, "reg");
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if (addr != FDT_ADDR_T_NONE)
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return (struct emc_ctlr *)addr;
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}
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return NULL;
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}
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/* Error codes we use */
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enum {
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ERR_NO_EMC_NODE = -10,
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ERR_NO_EMC_REG,
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ERR_NO_FREQ,
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ERR_FREQ_NOT_FOUND,
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ERR_BAD_REGS,
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ERR_NO_RAM_CODE,
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ERR_RAM_CODE_NOT_FOUND,
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};
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/**
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* Find EMC tables for the given ram code.
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*
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* The tegra EMC binding has two options, one using the ram code and one not.
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* We detect which is in use by looking for the nvidia,use-ram-code property.
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* If this is not present, then the EMC tables are directly below 'node',
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* otherwise we select the correct emc-tables subnode based on the 'ram_code'
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* value.
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*
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* @param blob Device tree blob
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* @param node EMC node (nvidia,tegra20-emc compatible string)
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* @param ram_code RAM code to select (0-3, or -1 if unknown)
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* @return 0 if ok, otherwise a -ve ERR_ code (see enum above)
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*/
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static int find_emc_tables(const void *blob, int node, int ram_code)
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{
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int need_ram_code;
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int depth;
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int offset;
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/* If we are using RAM codes, scan through the tables for our code */
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need_ram_code = fdtdec_get_bool(blob, node, "nvidia,use-ram-code");
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if (!need_ram_code)
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return node;
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if (ram_code == -1) {
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debug("%s: RAM code required but not supplied\n", __func__);
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return ERR_NO_RAM_CODE;
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}
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offset = node;
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depth = 0;
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do {
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/*
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* Sadly there is no compatible string so we cannot use
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* fdtdec_next_compatible_subnode().
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*/
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offset = fdt_next_node(blob, offset, &depth);
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if (depth <= 0)
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break;
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/* Make sure this is a direct subnode */
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if (depth != 1)
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continue;
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if (strcmp("emc-tables", fdt_get_name(blob, offset, NULL)))
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continue;
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if (fdtdec_get_int(blob, offset, "nvidia,ram-code", -1)
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== ram_code)
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return offset;
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} while (1);
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debug("%s: Could not find tables for RAM code %d\n", __func__,
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ram_code);
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return ERR_RAM_CODE_NOT_FOUND;
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}
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/**
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* Decode the EMC node of the device tree, returning a pointer to the emc
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* controller and the table to be used for the given rate.
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*
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* @param blob Device tree blob
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* @param rate Clock speed of memory controller in Hz (=2x memory bus rate)
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* @param emcp Returns address of EMC controller registers
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* @param tablep Returns pointer to table to program into EMC. There are
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* TEGRA_EMC_NUM_REGS entries, destined for offsets as per the
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* emc_reg_addr array.
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* @return 0 if ok, otherwise a -ve error code which will allow someone to
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* figure out roughly what went wrong by looking at this code.
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*/
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static int decode_emc(const void *blob, unsigned rate, struct emc_ctlr **emcp,
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const u32 **tablep)
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{
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struct apb_misc_pp_ctlr *pp =
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(struct apb_misc_pp_ctlr *)NV_PA_APB_MISC_BASE;
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int ram_code;
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int depth;
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int node;
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ram_code = (readl(&pp->strapping_opt_a) & RAM_CODE_MASK)
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>> RAM_CODE_SHIFT;
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/*
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* The EMC clock rate is twice the bus rate, and the bus rate is
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* measured in kHz
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*/
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rate = rate / 2 / 1000;
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node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_EMC);
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if (node < 0) {
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debug("%s: No EMC node found in FDT\n", __func__);
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return ERR_NO_EMC_NODE;
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}
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*emcp = (struct emc_ctlr *)fdtdec_get_addr(blob, node, "reg");
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if (*emcp == (struct emc_ctlr *)FDT_ADDR_T_NONE) {
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debug("%s: No EMC node reg property\n", __func__);
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return ERR_NO_EMC_REG;
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}
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/* Work out the parent node which contains our EMC tables */
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node = find_emc_tables(blob, node, ram_code & 3);
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if (node < 0)
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return node;
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depth = 0;
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for (;;) {
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int node_rate;
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node = fdtdec_next_compatible_subnode(blob, node,
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COMPAT_NVIDIA_TEGRA20_EMC_TABLE, &depth);
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if (node < 0)
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break;
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node_rate = fdtdec_get_int(blob, node, "clock-frequency", -1);
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if (node_rate == -1) {
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debug("%s: Missing clock-frequency\n", __func__);
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return ERR_NO_FREQ; /* we expect this property */
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}
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if (node_rate == rate)
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break;
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}
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if (node < 0) {
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debug("%s: No node found for clock frequency %d\n", __func__,
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rate);
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return ERR_FREQ_NOT_FOUND;
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}
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*tablep = fdtdec_locate_array(blob, node, "nvidia,emc-registers",
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TEGRA_EMC_NUM_REGS);
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if (!*tablep) {
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debug("%s: node '%s' array missing / wrong size\n", __func__,
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fdt_get_name(blob, node, NULL));
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return ERR_BAD_REGS;
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}
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/* All seems well */
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return 0;
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}
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int tegra_set_emc(const void *blob, unsigned rate)
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{
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struct emc_ctlr *emc;
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const u32 *table;
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int err, i;
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err = decode_emc(blob, rate, &emc, &table);
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if (err) {
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debug("Warning: no valid EMC (%d), memory timings unset\n",
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err);
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return err;
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}
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debug("%s: Table found, setting EMC values as follows:\n", __func__);
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for (i = 0; i < TEGRA_EMC_NUM_REGS; i++) {
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u32 value = fdt32_to_cpu(table[i]);
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u32 addr = (uintptr_t)emc + emc_reg_addr[i];
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debug(" %#x: %#x\n", addr, value);
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writel(value, addr);
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}
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/* trigger emc with new settings */
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clock_adjust_periph_pll_div(PERIPH_ID_EMC, CLOCK_ID_MEMORY,
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clock_get_rate(CLOCK_ID_MEMORY), NULL);
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debug("EMC clock set to %lu\n",
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clock_get_periph_rate(PERIPH_ID_EMC, CLOCK_ID_MEMORY));
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return 0;
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}
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@ -0,0 +1,113 @@
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/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _ARCH_EMC_H_
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#define _ARCH_EMC_H_
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#include <asm/types.h>
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#define TEGRA_EMC_NUM_REGS 46
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/* EMC Registers */
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struct emc_ctlr {
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u32 cfg; /* 0x00: EMC_CFG */
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u32 reserved0[3]; /* 0x04 ~ 0x0C */
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u32 adr_cfg; /* 0x10: EMC_ADR_CFG */
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u32 adr_cfg1; /* 0x14: EMC_ADR_CFG_1 */
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u32 reserved1[2]; /* 0x18 ~ 0x18 */
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u32 refresh_ctrl; /* 0x20: EMC_REFCTRL */
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u32 pin; /* 0x24: EMC_PIN */
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u32 timing_ctrl; /* 0x28: EMC_TIMING_CONTROL */
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u32 rc; /* 0x2C: EMC_RC */
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u32 rfc; /* 0x30: EMC_RFC */
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u32 ras; /* 0x34: EMC_RAS */
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u32 rp; /* 0x38: EMC_RP */
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u32 r2w; /* 0x3C: EMC_R2W */
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u32 w2r; /* 0x40: EMC_W2R */
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u32 r2p; /* 0x44: EMC_R2P */
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u32 w2p; /* 0x48: EMC_W2P */
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u32 rd_rcd; /* 0x4C: EMC_RD_RCD */
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u32 wd_rcd; /* 0x50: EMC_WD_RCD */
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u32 rrd; /* 0x54: EMC_RRD */
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u32 rext; /* 0x58: EMC_REXT */
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u32 wdv; /* 0x5C: EMC_WDV */
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u32 quse; /* 0x60: EMC_QUSE */
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u32 qrst; /* 0x64: EMC_QRST */
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u32 qsafe; /* 0x68: EMC_QSAFE */
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u32 rdv; /* 0x6C: EMC_RDV */
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u32 refresh; /* 0x70: EMC_REFRESH */
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u32 burst_refresh_num; /* 0x74: EMC_BURST_REFRESH_NUM */
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u32 pdex2wr; /* 0x78: EMC_PDEX2WR */
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u32 pdex2rd; /* 0x7c: EMC_PDEX2RD */
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u32 pchg2pden; /* 0x80: EMC_PCHG2PDEN */
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u32 act2pden; /* 0x84: EMC_ACT2PDEN */
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u32 ar2pden; /* 0x88: EMC_AR2PDEN */
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u32 rw2pden; /* 0x8C: EMC_RW2PDEN */
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u32 txsr; /* 0x90: EMC_TXSR */
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u32 tcke; /* 0x94: EMC_TCKE */
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u32 tfaw; /* 0x98: EMC_TFAW */
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u32 trpab; /* 0x9C: EMC_TRPAB */
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u32 tclkstable; /* 0xA0: EMC_TCLKSTABLE */
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u32 tclkstop; /* 0xA4: EMC_TCLKSTOP */
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u32 trefbw; /* 0xA8: EMC_TREFBW */
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u32 quse_extra; /* 0xAC: EMC_QUSE_EXTRA */
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u32 odt_write; /* 0xB0: EMC_ODT_WRITE */
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u32 odt_read; /* 0xB4: EMC_ODT_READ */
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u32 reserved2[5]; /* 0xB8 ~ 0xC8 */
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u32 mrs; /* 0xCC: EMC_MRS */
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u32 emrs; /* 0xD0: EMC_EMRS */
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u32 ref; /* 0xD4: EMC_REF */
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u32 pre; /* 0xD8: EMC_PRE */
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u32 nop; /* 0xDC: EMC_NOP */
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u32 self_ref; /* 0xE0: EMC_SELF_REF */
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u32 dpd; /* 0xE4: EMC_DPD */
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u32 mrw; /* 0xE8: EMC_MRW */
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u32 mrr; /* 0xEC: EMC_MRR */
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u32 reserved3; /* 0xF0: */
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u32 fbio_cfg1; /* 0xF4: EMC_FBIO_CFG1 */
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u32 fbio_dqsib_dly; /* 0xF8: EMC_FBIO_DQSIB_DLY */
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u32 fbio_dqsib_dly_msb; /* 0xFC: EMC_FBIO_DQSIB_DLY_MSG */
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u32 fbio_spare; /* 0x100: SBIO_SPARE */
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/* There are more registers ... */
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};
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/**
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* Set up the EMC for the given rate. The timing parameters are retrieved
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* from the device tree "nvidia,tegra20-emc" node and its
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* "nvidia,tegra20-emc-table" sub-nodes.
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*
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* @param blob Device tree blob
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* @param rate Clock speed of memory controller in Hz (=2x memory bus rate)
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* @return 0 if ok, else -ve error code (look in emc.c to decode it)
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*/
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int tegra_set_emc(const void *blob, unsigned rate);
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/**
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* Get a pointer to the EMC controller from the device tree.
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*
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* @param blob Device tree blob
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* @return pointer to EMC controller
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*/
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struct emc_ctlr *emc_get_controller(const void *blob);
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#endif
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@ -60,6 +60,8 @@ enum fdt_compat_id {
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COMPAT_NVIDIA_TEGRA20_USB, /* Tegra2 USB port */
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COMPAT_NVIDIA_TEGRA20_I2C, /* Tegra2 i2c */
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COMPAT_NVIDIA_TEGRA20_DVC, /* Tegra2 dvc (really just i2c) */
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COMPAT_NVIDIA_TEGRA20_EMC, /* Tegra2 memory controller */
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COMPAT_NVIDIA_TEGRA20_EMC_TABLE, /* Tegra2 memory timing table */
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COMPAT_COUNT,
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};
|
||||
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@ -40,6 +40,8 @@ static const char * const compat_names[COMPAT_COUNT] = {
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COMPAT(NVIDIA_TEGRA20_USB, "nvidia,tegra20-ehci"),
|
||||
COMPAT(NVIDIA_TEGRA20_I2C, "nvidia,tegra20-i2c"),
|
||||
COMPAT(NVIDIA_TEGRA20_DVC, "nvidia,tegra20-i2c-dvc"),
|
||||
COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),
|
||||
COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),
|
||||
};
|
||||
|
||||
const char *fdtdec_get_compatible(enum fdt_compat_id id)
|
||||
|
|
|
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Loading…
Reference in New Issue