Blackfin: default to L1 bank A when L1 bank B does not exist
Some parts lack Bank B in L1 data, so have the linker script fall back to Bank A when that happens. This way we can still leverage L1 data. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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@ -40,9 +40,13 @@
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* This is here in the first place so we can quickly test building
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* for different CPU's which may lack non-cache L1 data.
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*/
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#ifndef L1_DATA_A_SRAM
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# define L1_DATA_A_SRAM 0
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# define L1_DATA_A_SRAM_SIZE 0
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#endif
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#ifndef L1_DATA_B_SRAM
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# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE
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# define L1_DATA_B_SRAM_SIZE 0
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# define L1_DATA_B_SRAM L1_DATA_A_SRAM
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# define L1_DATA_B_SRAM_SIZE L1_DATA_A_SRAM_SIZE
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#endif
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/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
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@ -138,7 +142,7 @@ SECTIONS
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} >l1_data AT>ram_data
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__data_l1_lma = LOADADDR(.data_l1);
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__data_l1_len = SIZEOF(.data_l1);
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ASSERT (__data_l1_len <= L1_DATA_B_SRAM_SIZE, "L1 data B overflow!")
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ASSERT (__data_l1_len <= L1_DATA_B_SRAM_SIZE, "L1 data overflow!")
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.bss :
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{
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