ARM: AM57xx: Update EMIF registers
There are certain EMIF timing failures seen on the some x15 boards. Updating the EMIF settings to get rid of these timing failures. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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@ -64,22 +64,22 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
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static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
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.sdram_config_init = 0x61851b32,
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.sdram_config = 0x61851b32,
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.sdram_config2 = 0x00000000,
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.sdram_config2 = 0x08000000,
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.ref_ctrl = 0x000040F1,
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.ref_ctrl_final = 0x00001035,
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.sdram_tim1 = 0xceef266b,
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.sdram_tim2 = 0x328f7fda,
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.sdram_tim3 = 0x027f88a8,
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.sdram_tim1 = 0xcccf36ab,
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.sdram_tim2 = 0x308f7fda,
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.sdram_tim3 = 0x409f88a8,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x0007190b,
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.zq_config = 0x5007190b,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1_init = 0x0024400b,
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.emif_ddr_phy_ctlr_1 = 0x0e24400b,
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.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
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.emif_ddr_ext_phy_ctrl_2 = 0x00740074,
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.emif_ddr_ext_phy_ctrl_3 = 0x00780078,
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.emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
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.emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
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.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
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.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
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.emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
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.emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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@ -89,39 +89,35 @@ static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
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/* Ext phy ctrl regs 1-35 */
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static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
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0x10040100,
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0x00740074,
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0x00780078,
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0x007c007c,
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0x007b007b,
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0x00800080,
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0x00360036,
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0x00910091,
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0x00950095,
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0x009B009B,
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0x009E009E,
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0x00980098,
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0x00340034,
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0x00360036,
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0x00350035,
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0x00350035,
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0x01ff01ff,
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0x01ff01ff,
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0x01ff01ff,
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0x01ff01ff,
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0x01ff01ff,
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0x00430043,
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0x003e003e,
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0x004a004a,
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0x00470047,
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0x00400040,
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0x00340034,
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0x00310031,
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0x00340034,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x00480048,
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0x004A004A,
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0x00520052,
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0x00550055,
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0x00500050,
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0x00000000,
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0x00600020,
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0x40011080,
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0x08102040,
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0x00400040,
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0x00400040,
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0x00400040,
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0x00400040,
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0x00400040,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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@ -132,22 +128,22 @@ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
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static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
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.sdram_config_init = 0x61851b32,
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.sdram_config = 0x61851b32,
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.sdram_config2 = 0x00000000,
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.sdram_config2 = 0x08000000,
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.ref_ctrl = 0x000040F1,
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.ref_ctrl_final = 0x00001035,
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.sdram_tim1 = 0xceef266b,
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.sdram_tim2 = 0x328f7fda,
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.sdram_tim3 = 0x027f88a8,
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.sdram_tim1 = 0xcccf36ab,
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.sdram_tim2 = 0x308f7fda,
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.sdram_tim3 = 0x409f88a8,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x0007190b,
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.zq_config = 0x5007190b,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1_init = 0x0024400b,
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.emif_ddr_phy_ctlr_1 = 0x0e24400b,
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.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
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.emif_ddr_ext_phy_ctrl_2 = 0x00820082,
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.emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
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.emif_ddr_ext_phy_ctrl_4 = 0x00800080,
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.emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
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.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
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.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
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.emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
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.emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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@ -156,37 +152,35 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
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static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
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0x10040100,
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0x00820082,
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0x008b008b,
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0x00800080,
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0x007e007e,
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0x00800080,
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0x00370037,
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0x00390039,
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0x00360036,
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0x00370037,
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0x00910091,
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0x00950095,
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0x009B009B,
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0x009E009E,
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0x00980098,
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0x00340034,
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0x00350035,
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0x01ff01ff,
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0x01ff01ff,
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0x01ff01ff,
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0x01ff01ff,
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0x01ff01ff,
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0x00540054,
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0x00540054,
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0x004e004e,
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0x004c004c,
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0x00400040,
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0x00340034,
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0x00310031,
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0x00340034,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x007F007F,
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0x00480048,
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0x004A004A,
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0x00520052,
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0x00550055,
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0x00500050,
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0x00000000,
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0x00600020,
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0x40011080,
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0x08102040,
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0x00400040,
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0x00400040,
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0x00400040,
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0x00400040,
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0x00400040,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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0x0,
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