From 1836036c3241431e37135d45cdd8f1a28a6b09b3 Mon Sep 17 00:00:00 2001 From: Steinar Bakkemo Date: Mon, 3 Jun 2019 13:34:39 +0200 Subject: [PATCH] Remove not required config from devicetree Add CLKO2 pin mux (-> SD1_WP pad) --- arch/arm/dts/zero-sugar.dts | 208 ++---------------------------------- 1 file changed, 8 insertions(+), 200 deletions(-) diff --git a/arch/arm/dts/zero-sugar.dts b/arch/arm/dts/zero-sugar.dts index 50375e279d..ebd9e45c38 100644 --- a/arch/arm/dts/zero-sugar.dts +++ b/arch/arm/dts/zero-sugar.dts @@ -77,67 +77,11 @@ /*arm-supply = <&sw1a_reg>;*/ }; -/* -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>; - pinctrl-assert-gpios = <&gpio_spi 5 GPIO_ACTIVE_HIGH>; - assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>, - <&clks IMX7D_ENET_AXI_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>, - <&clks IMX7D_ENET_AXI_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>; - phy-mode = "rgmii"; - phy-handle = <ðphy0>; - fsl,magic-packet; - status = "disabled"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <0>; - }; - - ethphy1: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; - }; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_epdc0_en>; - pinctrl-assert-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; - assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>, - <&clks IMX7D_ENET_AXI_ROOT_SRC>, - <&clks IMX7D_ENET2_TIME_ROOT_SRC>, - <&clks IMX7D_ENET2_TIME_ROOT_CLK>, - <&clks IMX7D_ENET_AXI_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, - <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>; - phy-mode = "rgmii"; - phy-handle = <ðphy1>; - fsl,magic-packet; - status = "disabled"; -}; -*/ - &i2c1 { clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; status = "okay"; @@ -147,7 +91,6 @@ clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_gpio>; scl-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; status = "okay"; @@ -157,7 +100,6 @@ clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_gpio>; scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; status = "okay"; @@ -167,7 +109,6 @@ clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_gpio>; scl-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>; status = "okay"; @@ -210,17 +151,12 @@ status = "okay"; }; + &iomuxc_lpsr { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_2 &pinctrl_usbotg2_pwr_2>; + pinctrl-0 = <&pinctrl_usbotg2_pwr_2>; imx7d-sdb { - pinctrl_hog_2: hoggrp-2 { - fsl,pins = < - MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14 - >; - }; - pinctrl_usbotg2_pwr_2: usbotg2-2 { fsl,pins = < MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x14 @@ -232,12 +168,6 @@ MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74 >; }; - - pinctrl_enet2_epdc0_en: enet2_epdc0_grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x80000000 - >; - }; }; }; @@ -263,25 +193,11 @@ status = "okay"; }; -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; - cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - wakeup-source; - vmmc-supply = <®_sd1_vmmc>; - enable-sdio-wakeup; - keep-power-in-suspend; - status = "okay"; -}; - &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + pinctrl-0 = <&pinctrl_wifi &pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_wifi &pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_wifi &pinctrl_usdhc2_200mhz>; enable-sdio-wakeup; keep-power-in-suspend; non-removable; @@ -311,49 +227,12 @@ &iomuxc { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog_1>; + pinctrl-0 = <&pinctrl_wifi>; imx7d-sdb { - - pinctrl_hog_1: hoggrp-1 { + pinctrl_wifi: wifigrp { fsl,pins = < - MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x59 /* headphone detect */ - >; - }; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 - MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 - MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 - MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 - MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 - MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 - MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 - MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 - MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 - MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 - MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 - MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 - MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 - MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 - >; - }; - - pinctrl_enet2: enet2grp { - fsl,pins = < - MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 - MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 - MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 - MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 - MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 - MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 - MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 - MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 - MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 - MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 - MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 - MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 + MX7D_PAD_SD1_WP__CCM_CLKO2 0x00000014 >; }; @@ -364,13 +243,6 @@ >; }; - pinctrl_i2c1_gpio: i2c1grp_gpio { - fsl,pins = < - MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x7f - MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x7f - >; - }; - pinctrl_i2c2: i2c2grp { fsl,pins = < MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f @@ -378,13 +250,6 @@ >; }; - pinctrl_i2c2_gpio: i2c2grp_gpio { - fsl,pins = < - MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x7f - MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x7f - >; - }; - pinctrl_i2c3: i2c3grp { fsl,pins = < MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f @@ -392,13 +257,6 @@ >; }; - pinctrl_i2c3_gpio: i2c3grp_gpio { - fsl,pins = < - MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x7f - MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x7f - >; - }; - pinctrl_i2c4: i2c4grp { fsl,pins = < MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f @@ -406,13 +264,6 @@ >; }; - pinctrl_i2c4_gpio: i2c4grp_gpio { - fsl,pins = < - MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x7f - MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x7f - >; - }; - pinctrl_lcdif: lcdifgrp { fsl,pins = < MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 @@ -454,55 +305,12 @@ >; }; - pinctrl_usdhc1_gpio: usdhc1_gpiogrp { - fsl,pins = < - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ - MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ - >; - }; - pinctrl_usbotg2_pwr_1: usbotg2-1 { fsl,pins = < MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 >; }; - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x59 - MX7D_PAD_SD1_CLK__SD1_CLK 0x19 - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5a - MX7D_PAD_SD1_CLK__SD1_CLK 0x1a - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { - fsl,pins = < - MX7D_PAD_SD1_CMD__SD1_CMD 0x5b - MX7D_PAD_SD1_CLK__SD1_CLK 0x1b - MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b - MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b - MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b - MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b - >; - }; - pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX7D_PAD_SD2_CMD__SD2_CMD 0x59