Merge git://www.denx.de/git/u-boot into merge
This commit is contained in:
commit
19909edb97
|
@ -438,6 +438,20 @@ Changes for U-Boot 1.1.5:
|
|||
|
||||
* Call serial_initialize() before first debug() is used.
|
||||
|
||||
* Code cleanup
|
||||
|
||||
* Various USB related patches
|
||||
- Add support for mpc8xx USB device.
|
||||
- Add support for Common Device Class - Abstract Control Model USB console.
|
||||
- Add support for flow control in USB slave devices.
|
||||
- Add support for switching between gserial and cdc_acm using environment.
|
||||
- Minor changes to usbdcore_omap1510.c usbdcore_omap1510.h
|
||||
- Update usbcore slightly to ease host enumeration.
|
||||
- Fix non-portable endian problems in usbdcore and usbdcore_ep0.
|
||||
- Add AdderUSB_config as a defconfig to enable usage of the USB console
|
||||
by default with the Adder87x U-Boot port.
|
||||
Patch by Bryan O'Donoghue <bodonoghue@codehermit.ie>, 29 May 2006
|
||||
|
||||
* Cleanup trab board for GCC-4.x
|
||||
|
||||
* VoiceBlue update: use new MTD flash partitioning methods, use more
|
||||
|
|
9
CREDITS
9
CREDITS
|
@ -160,6 +160,11 @@ N: Thomas Frieden
|
|||
E: ThomasF@hyperion-entertainment.com
|
||||
D: Support for AmigaOne
|
||||
|
||||
N: Niklaus Giger
|
||||
E: niklaus.giger@netstal.com
|
||||
D: Support for HCU(x) boards
|
||||
W: www.netstal.com
|
||||
|
||||
N: Paul Gortmaker
|
||||
E: paul.gortmaker@windriver.com
|
||||
D: Support for WRS SBC8347/8349 boards
|
||||
|
@ -252,6 +257,10 @@ E: Raghu.Krishnaprasad@fci.com
|
|||
D: Support for Adder-II MPC852T evaluation board
|
||||
W: http://www.forcecomputers.com
|
||||
|
||||
N: Sergey Kubushyn
|
||||
E: ksi@koi8.net
|
||||
D: Support for various TI DaVinci based boards.
|
||||
|
||||
N: Bernhard Kuhn
|
||||
E: bkuhn@metrowerks.com
|
||||
D Support for Coldfire CPU; Support for Motorola M5272C3 and M5282EVB boards
|
||||
|
|
17
MAINTAINERS
17
MAINTAINERS
|
@ -160,6 +160,11 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com>
|
|||
WUH405 PPC405EP
|
||||
CMS700 PPC405EP
|
||||
|
||||
Niklaus Giger <niklaus.giger@netstal.com>
|
||||
|
||||
HCU4 PPC405GPr
|
||||
HCU5 PPC440EPx
|
||||
|
||||
Frank Gottschling <fgottschling@eltec.de>
|
||||
|
||||
MHPC MPC8xx
|
||||
|
@ -179,6 +184,10 @@ Howard Gray <mvsensor@matrix-vision.de>
|
|||
|
||||
MVS1 MPC823
|
||||
|
||||
Joe Hamman <joe.hamman@embeddedspecialties.com>
|
||||
|
||||
sbc8641d MPC8641D
|
||||
|
||||
Klaus Heydeck <heydeck@kieback-peter.de>
|
||||
|
||||
KUP4K MPC855
|
||||
|
@ -248,6 +257,7 @@ Tolunay Orkun <torkun@nextio.com>
|
|||
John Otken <jotken@softadvances.com>
|
||||
|
||||
luan PPC440SP
|
||||
taihu PPC405EP
|
||||
|
||||
Keith Outwater <Keith_Outwater@mvis.com>
|
||||
|
||||
|
@ -292,6 +302,7 @@ Stefan Roese <sr@denx.de>
|
|||
walnut PPC405GP
|
||||
yellowstone PPC440GR
|
||||
yosemite PPC440EP
|
||||
zeus PPC405EP
|
||||
|
||||
P3M750 PPC750FX/GX/GL
|
||||
|
||||
|
@ -444,6 +455,12 @@ Nishant Kamat <nskamat@ti.com>
|
|||
|
||||
omap1610h2 ARM926EJS
|
||||
|
||||
Sergey Kubushyn <ksi@koi8.net>
|
||||
|
||||
DV-EVM ARM926EJS
|
||||
SONATA ARM926EJS
|
||||
SCHMOOGIE ARM926EJS
|
||||
|
||||
Prakash Kumar <prakash@embedx.com>
|
||||
|
||||
cerf250 xscale
|
||||
|
|
591
MAKEALL
591
MAKEALL
|
@ -26,124 +26,285 @@ LIST=""
|
|||
## MPC5xx Systems
|
||||
#########################################################################
|
||||
|
||||
LIST_5xx=" \
|
||||
cmi_mpc5xx \
|
||||
LIST_5xx=" \
|
||||
cmi_mpc5xx \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## MPC5xxx Systems
|
||||
#########################################################################
|
||||
|
||||
LIST_5xxx=" \
|
||||
BC3450 cm5200 cpci5200 EVAL5200 \
|
||||
fo300 icecube_5100 icecube_5200 lite5200b \
|
||||
mcc200 mecp5200 motionpro o2dnt \
|
||||
pf5200 PM520 TB5200 Total5100 \
|
||||
Total5200 Total5200_Rev2 TQM5200 TQM5200_B \
|
||||
TQM5200S v38b \
|
||||
LIST_5xxx=" \
|
||||
BC3450 \
|
||||
cm5200 \
|
||||
cpci5200 \
|
||||
EVAL5200 \
|
||||
fo300 \
|
||||
icecube_5100 \
|
||||
icecube_5200 \
|
||||
lite5200b \
|
||||
mcc200 \
|
||||
mecp5200 \
|
||||
motionpro \
|
||||
o2dnt \
|
||||
pf5200 \
|
||||
PM520 \
|
||||
TB5200 \
|
||||
Total5100 \
|
||||
Total5200 \
|
||||
Total5200_Rev2 \
|
||||
TQM5200 \
|
||||
TQM5200_B \
|
||||
TQM5200S \
|
||||
v38b \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## MPC512x Systems
|
||||
#########################################################################
|
||||
|
||||
LIST_512x=" \
|
||||
ads5121 \
|
||||
LIST_512x=" \
|
||||
ads5121 \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## MPC8xx Systems
|
||||
#########################################################################
|
||||
LIST_8xx=" \
|
||||
Adder87x GENIETV MBX860T R360MPI \
|
||||
AdderII GTH MHPC RBC823 \
|
||||
ADS860 hermes MPC86xADS rmu \
|
||||
AMX860 IAD210 MPC885ADS RPXClassic \
|
||||
c2mon ICU862_100MHz MVS1 RPXlite \
|
||||
CCM IP860 NETPHONE RPXlite_DW \
|
||||
cogent_mpc8xx IVML24 NETTA RRvision \
|
||||
ELPT860 IVML24_128 NETTA2 SM850 \
|
||||
EP88x IVML24_256 NETTA_ISDN spc1920 \
|
||||
ESTEEM192E IVMS8 NETVIA SPD823TS \
|
||||
ETX094 IVMS8_128 NETVIA_V2 svm_sc8xx \
|
||||
FADS823 IVMS8_256 NX823 SXNI855T \
|
||||
FADS850SAR KUP4K pcu_e TOP860 \
|
||||
FADS860T KUP4X QS823 TQM823L \
|
||||
FLAGADM LANTEC QS850 TQM823L_LCD \
|
||||
FPS850L lwmon QS860T TQM850L \
|
||||
GEN860T MBX quantum TQM855L \
|
||||
GEN860T_SC TQM860L \
|
||||
TQM885D \
|
||||
uc100 \
|
||||
v37 \
|
||||
LIST_8xx=" \
|
||||
Adder87x \
|
||||
AdderII \
|
||||
ADS860 \
|
||||
AMX860 \
|
||||
c2mon \
|
||||
CCM \
|
||||
cogent_mpc8xx \
|
||||
ELPT860 \
|
||||
EP88x \
|
||||
ESTEEM192E \
|
||||
ETX094 \
|
||||
FADS823 \
|
||||
FADS850SAR \
|
||||
FADS860T \
|
||||
FLAGADM \
|
||||
FPS850L \
|
||||
GEN860T \
|
||||
GEN860T_SC \
|
||||
GENIETV \
|
||||
GTH \
|
||||
hermes \
|
||||
IAD210 \
|
||||
ICU862_100MHz \
|
||||
IP860 \
|
||||
IVML24 \
|
||||
IVML24_128 \
|
||||
IVML24_256 \
|
||||
IVMS8 \
|
||||
IVMS8_128 \
|
||||
IVMS8_256 \
|
||||
KUP4K \
|
||||
KUP4X \
|
||||
LANTEC \
|
||||
lwmon \
|
||||
MBX \
|
||||
MBX860T \
|
||||
MHPC \
|
||||
MPC86xADS \
|
||||
MPC885ADS \
|
||||
MVS1 \
|
||||
NETPHONE \
|
||||
NETTA \
|
||||
NETTA2 \
|
||||
NETTA_ISDN \
|
||||
NETVIA \
|
||||
NETVIA_V2 \
|
||||
NX823 \
|
||||
pcu_e \
|
||||
QS823 \
|
||||
QS850 \
|
||||
QS860T \
|
||||
quantum \
|
||||
R360MPI \
|
||||
RBC823 \
|
||||
rmu \
|
||||
RPXClassic \
|
||||
RPXlite \
|
||||
RPXlite_DW \
|
||||
RRvision \
|
||||
SM850 \
|
||||
spc1920 \
|
||||
SPD823TS \
|
||||
svm_sc8xx \
|
||||
SXNI855T \
|
||||
TOP860 \
|
||||
TQM823L \
|
||||
TQM823L_LCD \
|
||||
TQM850L \
|
||||
TQM855L \
|
||||
TQM860L \
|
||||
TQM885D \
|
||||
uc100 \
|
||||
v37 \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## PPC4xx Systems
|
||||
#########################################################################
|
||||
|
||||
LIST_4xx=" \
|
||||
acadia acadia_nand ADCIOP alpr \
|
||||
AP1000 AR405 ASH405 bamboo \
|
||||
bamboo_nand bubinga CANBT CMS700 \
|
||||
CPCI2DP CPCI405 CPCI4052 CPCI405AB \
|
||||
CPCI405DT CPCI440 CPCIISER4 CRAYL1 \
|
||||
csb272 csb472 DASA_SIM DP405 \
|
||||
DU405 ebony ERIC EXBITGEN \
|
||||
G2000 HH405 HUB405 JSE \
|
||||
KAREF katmai luan lwmon5 \
|
||||
METROBOX MIP405 MIP405T ML2 \
|
||||
ml300 ocotea OCRTC ORSG \
|
||||
p3p440 PCI405 pcs440ep PIP405 \
|
||||
PLU405 PMC405 PPChameleonEVB sbc405 \
|
||||
sc3 sequoia sequoia_nand taishan \
|
||||
VOH405 VOM405 W7OLMC W7OLMG \
|
||||
walnut WUH405 XPEDITE1K yellowstone \
|
||||
yosemite yucca \
|
||||
LIST_4xx=" \
|
||||
acadia \
|
||||
acadia_nand \
|
||||
ADCIOP \
|
||||
alpr \
|
||||
AP1000 \
|
||||
AR405 \
|
||||
ASH405 \
|
||||
bamboo \
|
||||
bamboo_nand \
|
||||
bubinga \
|
||||
CANBT \
|
||||
CMS700 \
|
||||
CPCI2DP \
|
||||
CPCI405 \
|
||||
CPCI4052 \
|
||||
CPCI405AB \
|
||||
CPCI405DT \
|
||||
CPCI440 \
|
||||
CPCIISER4 \
|
||||
CRAYL1 \
|
||||
csb272 \
|
||||
csb472 \
|
||||
DASA_SIM \
|
||||
DP405 \
|
||||
DU405 \
|
||||
ebony \
|
||||
ERIC \
|
||||
EXBITGEN \
|
||||
G2000 \
|
||||
hcu4 \
|
||||
hcu5 \
|
||||
HH405 \
|
||||
HUB405 \
|
||||
JSE \
|
||||
KAREF \
|
||||
katmai \
|
||||
luan \
|
||||
lwmon5 \
|
||||
METROBOX \
|
||||
MIP405 \
|
||||
MIP405T \
|
||||
ML2 \
|
||||
ml300 \
|
||||
ocotea \
|
||||
OCRTC \
|
||||
ORSG \
|
||||
p3p440 \
|
||||
PCI405 \
|
||||
pcs440ep \
|
||||
PIP405 \
|
||||
PLU405 \
|
||||
PMC405 \
|
||||
PPChameleonEVB \
|
||||
sbc405 \
|
||||
sc3 \
|
||||
sequoia \
|
||||
sequoia_nand \
|
||||
taihu \
|
||||
taishan \
|
||||
VOH405 \
|
||||
VOM405 \
|
||||
W7OLMC \
|
||||
W7OLMG \
|
||||
walnut \
|
||||
WUH405 \
|
||||
XPEDITE1K \
|
||||
yellowstone \
|
||||
yosemite \
|
||||
yucca \
|
||||
zeus \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## MPC8220 Systems
|
||||
#########################################################################
|
||||
|
||||
LIST_8220=" \
|
||||
Alaska8220 Yukon8220 \
|
||||
LIST_8220=" \
|
||||
Alaska8220 \
|
||||
Yukon8220 \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## MPC824x Systems
|
||||
#########################################################################
|
||||
|
||||
LIST_824x=" \
|
||||
A3000 barco BMW CPC45 \
|
||||
CU824 debris eXalion HIDDEN_DRAGON \
|
||||
MOUSSE MUSENKI MVBLUE \
|
||||
OXC PN62 Sandpoint8240 Sandpoint8245 \
|
||||
sbc8240 SL8245 utx8245 \
|
||||
LIST_824x=" \
|
||||
A3000 \
|
||||
barco \
|
||||
BMW \
|
||||
CPC45 \
|
||||
CU824 \
|
||||
debris \
|
||||
eXalion \
|
||||
HIDDEN_DRAGON \
|
||||
MOUSSE \
|
||||
MUSENKI \
|
||||
MVBLUE \
|
||||
OXC \
|
||||
PN62 \
|
||||
Sandpoint8240 \
|
||||
Sandpoint8245 \
|
||||
sbc8240 \
|
||||
SL8245 \
|
||||
utx8245 \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## MPC8260 Systems (includes 8250, 8255 etc.)
|
||||
#########################################################################
|
||||
|
||||
LIST_8260=" \
|
||||
atc cogent_mpc8260 CPU86 CPU87 \
|
||||
ep8248 ep8260 ep82xxm gw8260 \
|
||||
hymod IPHASE4539 ISPAN MPC8260ADS \
|
||||
MPC8266ADS MPC8272ADS PM826 PM828 \
|
||||
ppmc8260 Rattler8248 RPXsuper rsdproto \
|
||||
sacsng sbc8260 SCM TQM8260_AC \
|
||||
TQM8260_AD TQM8260_AE ZPC1900 \
|
||||
LIST_8260=" \
|
||||
atc \
|
||||
cogent_mpc8260 \
|
||||
CPU86 \
|
||||
CPU87 \
|
||||
ep8248 \
|
||||
ep8260 \
|
||||
ep82xxm \
|
||||
gw8260 \
|
||||
hymod \
|
||||
IPHASE4539 \
|
||||
ISPAN \
|
||||
MPC8260ADS \
|
||||
MPC8266ADS \
|
||||
MPC8272ADS \
|
||||
PM826 \
|
||||
PM828 \
|
||||
ppmc8260 \
|
||||
Rattler8248 \
|
||||
RPXsuper \
|
||||
rsdproto \
|
||||
sacsng \
|
||||
sbc8260 \
|
||||
SCM \
|
||||
TQM8260_AC \
|
||||
TQM8260_AD \
|
||||
TQM8260_AE \
|
||||
ZPC1900 \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## MPC83xx Systems (includes 8349, etc.)
|
||||
#########################################################################
|
||||
|
||||
LIST_83xx=" \
|
||||
MPC8313ERDB_33 MPC8313ERDB_66 MPC832XEMDS MPC8349EMDS \
|
||||
MPC8349ITX MPC8349ITXGP MPC8360EMDS sbc8349 \
|
||||
TQM834x \
|
||||
LIST_83xx=" \
|
||||
MPC8313ERDB_33 \
|
||||
MPC8313ERDB_66 \
|
||||
MPC832XEMDS \
|
||||
MPC8349EMDS \
|
||||
MPC8349ITX \
|
||||
MPC8349ITXGP \
|
||||
MPC8360EMDS \
|
||||
sbc8349 \
|
||||
TQM834x \
|
||||
"
|
||||
|
||||
|
||||
|
@ -151,123 +312,227 @@ LIST_83xx=" \
|
|||
## MPC85xx Systems (includes 8540, 8560 etc.)
|
||||
#########################################################################
|
||||
|
||||
LIST_85xx=" \
|
||||
MPC8540ADS MPC8540EVAL MPC8541CDS MPC8544DS \
|
||||
MPC8548CDS MPC8555CDS MPC8560ADS MPC8568MDS \
|
||||
PM854 PM856 sbc8540 sbc8560 \
|
||||
stxgp3 stxssa TQM8540 TQM8541 \
|
||||
TQM8555 TQM8560 \
|
||||
LIST_85xx=" \
|
||||
MPC8540ADS \
|
||||
MPC8540EVAL \
|
||||
MPC8541CDS \
|
||||
MPC8544DS \
|
||||
MPC8548CDS \
|
||||
MPC8555CDS \
|
||||
MPC8560ADS \
|
||||
MPC8568MDS \
|
||||
PM854 \
|
||||
PM856 \
|
||||
sbc8540 \
|
||||
sbc8560 \
|
||||
stxgp3 \
|
||||
stxssa \
|
||||
TQM8540 \
|
||||
TQM8541 \
|
||||
TQM8555 \
|
||||
TQM8560 \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## MPC86xx Systems
|
||||
#########################################################################
|
||||
|
||||
LIST_86xx=" \
|
||||
MPC8641HPCN \
|
||||
LIST_86xx=" \
|
||||
MPC8641HPCN \
|
||||
SBC8641D \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## 74xx/7xx Systems
|
||||
#########################################################################
|
||||
|
||||
LIST_74xx=" \
|
||||
DB64360 DB64460 EVB64260 P3G4 \
|
||||
p3m7448 PCIPPC2 PCIPPC6 ZUMA \
|
||||
mpc7448hpc2
|
||||
LIST_74xx=" \
|
||||
DB64360 \
|
||||
DB64460 \
|
||||
EVB64260 \
|
||||
mpc7448hpc2 \
|
||||
P3G4 \
|
||||
p3m7448 \
|
||||
PCIPPC2 \
|
||||
PCIPPC6 \
|
||||
ZUMA \
|
||||
"
|
||||
|
||||
LIST_7xx=" \
|
||||
BAB7xx CPCI750 ELPPC p3m750 \
|
||||
ppmc7xx \
|
||||
LIST_7xx=" \
|
||||
BAB7xx \
|
||||
CPCI750 \
|
||||
ELPPC \
|
||||
p3m750 \
|
||||
ppmc7xx \
|
||||
"
|
||||
|
||||
LIST_ppc="${LIST_5xx} ${LIST_5xxx} \
|
||||
${LIST_8xx} \
|
||||
${LIST_8220} ${LIST_824x} ${LIST_8260} \
|
||||
${LIST_83xx} \
|
||||
${LIST_85xx} \
|
||||
${LIST_86xx} \
|
||||
${LIST_4xx} \
|
||||
${LIST_74xx} ${LIST_7xx}"
|
||||
LIST_ppc=" \
|
||||
${LIST_5xx} \
|
||||
${LIST_5xxx} \
|
||||
${LIST_8xx} \
|
||||
${LIST_8220} \
|
||||
${LIST_824x} \
|
||||
${LIST_8260} \
|
||||
${LIST_83xx} \
|
||||
${LIST_85xx} \
|
||||
${LIST_86xx} \
|
||||
${LIST_4xx} \
|
||||
${LIST_74xx} \
|
||||
${LIST_7xx} \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## StrongARM Systems
|
||||
#########################################################################
|
||||
|
||||
LIST_SA="assabet dnp1110 gcplus lart shannon"
|
||||
LIST_SA=" \
|
||||
assabet \
|
||||
dnp1110 \
|
||||
gcplus \
|
||||
lart \
|
||||
shannon \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## ARM7 Systems
|
||||
#########################################################################
|
||||
|
||||
LIST_ARM7=" \
|
||||
armadillo B2 ep7312 evb4510 \
|
||||
impa7 integratorap ap7 ap720t \
|
||||
lpc2292sodimm modnet50 SMN42 \
|
||||
LIST_ARM7=" \
|
||||
ap7 \
|
||||
ap720t \
|
||||
armadillo \
|
||||
B2 \
|
||||
ep7312 \
|
||||
evb4510 \
|
||||
impa7 \
|
||||
integratorap \
|
||||
lpc2292sodimm \
|
||||
modnet50 \
|
||||
SMN42 \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## ARM9 Systems
|
||||
#########################################################################
|
||||
|
||||
LIST_ARM9=" \
|
||||
at91rm9200dk cmc_pu2 \
|
||||
ap920t ap922_XA10 ap926ejs ap946es \
|
||||
ap966 cp920t cp922_XA10 cp926ejs \
|
||||
cp946es cp966 lpd7a400 mp2usb \
|
||||
mx1ads mx1fs2 netstar omap1510inn \
|
||||
omap1610h2 omap1610inn omap730p2 sbc2410x \
|
||||
scb9328 smdk2400 smdk2410 trab \
|
||||
VCMA9 versatile versatileab versatilepb \
|
||||
voiceblue \
|
||||
LIST_ARM9=" \
|
||||
at91rm9200dk \
|
||||
cmc_pu2 \
|
||||
ap920t \
|
||||
ap922_XA10 \
|
||||
ap926ejs \
|
||||
ap946es \
|
||||
ap966 \
|
||||
cp920t \
|
||||
cp922_XA10 \
|
||||
cp926ejs \
|
||||
cp946es \
|
||||
cp966 \
|
||||
lpd7a400 \
|
||||
mp2usb \
|
||||
mx1ads \
|
||||
mx1fs2 \
|
||||
netstar \
|
||||
omap1510inn \
|
||||
omap1610h2 \
|
||||
omap1610inn \
|
||||
omap730p2 \
|
||||
sbc2410x \
|
||||
scb9328 \
|
||||
smdk2400 \
|
||||
smdk2410 \
|
||||
trab \
|
||||
VCMA9 \
|
||||
versatile \
|
||||
versatileab \
|
||||
versatilepb \
|
||||
voiceblue \
|
||||
davinci_dvevm \
|
||||
davinci_schmoogie \
|
||||
davinci_sonata \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## ARM10 Systems
|
||||
#########################################################################
|
||||
LIST_ARM10=" \
|
||||
integratorcp cp1026 \
|
||||
LIST_ARM10=" \
|
||||
integratorcp \
|
||||
cp1026 \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## ARM11 Systems
|
||||
#########################################################################
|
||||
LIST_ARM11=" \
|
||||
cp1136 omap2420h4 \
|
||||
LIST_ARM11=" \
|
||||
cp1136 \
|
||||
omap2420h4 \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## Xscale Systems
|
||||
#########################################################################
|
||||
|
||||
LIST_pxa=" \
|
||||
adsvix cerf250 cradle csb226 \
|
||||
delta innokom lubbock pleb2 \
|
||||
pxa255_idp wepep250 xaeniax xm250 \
|
||||
xsengine zylonite \
|
||||
LIST_pxa=" \
|
||||
adsvix \
|
||||
cerf250 \
|
||||
cradle \
|
||||
csb226 \
|
||||
delta \
|
||||
innokom \
|
||||
lubbock \
|
||||
pleb2 \
|
||||
pxa255_idp \
|
||||
wepep250 \
|
||||
xaeniax \
|
||||
xm250 \
|
||||
xsengine \
|
||||
zylonite \
|
||||
"
|
||||
|
||||
LIST_ixp="ixdp425 ixdpg425 pdnb3 scpu"
|
||||
LIST_ixp=" \
|
||||
ixdp425 \
|
||||
ixdpg425 \
|
||||
pdnb3 \
|
||||
scpu \
|
||||
"
|
||||
|
||||
|
||||
LIST_arm=" \
|
||||
${LIST_SA} \
|
||||
${LIST_ARM7} ${LIST_ARM9} ${LIST_ARM10} ${LIST_ARM11} \
|
||||
${LIST_pxa} ${LIST_ixp} \
|
||||
LIST_arm=" \
|
||||
${LIST_SA} \
|
||||
${LIST_ARM7} \
|
||||
${LIST_ARM9} \
|
||||
${LIST_ARM10} \
|
||||
${LIST_ARM11} \
|
||||
${LIST_pxa} \
|
||||
${LIST_ixp} \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## MIPS Systems (default = big endian)
|
||||
#########################################################################
|
||||
|
||||
LIST_mips4kc="incaip"
|
||||
LIST_mips4kc=" \
|
||||
incaip \
|
||||
"
|
||||
|
||||
LIST_mips5kc="purple"
|
||||
LIST_mips5kc=" \
|
||||
purple \
|
||||
"
|
||||
|
||||
LIST_au1xx0="dbau1000 dbau1100 dbau1500 dbau1550 dbau1550_el gth2"
|
||||
LIST_au1xx0=" \
|
||||
dbau1000 \
|
||||
dbau1100 \
|
||||
dbau1500 \
|
||||
dbau1550 \
|
||||
dbau1550_el \
|
||||
gth2 \
|
||||
"
|
||||
|
||||
LIST_mips="${LIST_mips4kc} ${LIST_mips5kc} ${LIST_au1xx0}"
|
||||
LIST_mips=" \
|
||||
${LIST_mips4kc} \
|
||||
${LIST_mips5kc} \
|
||||
${LIST_au1xx0} \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## MIPS Systems (little endian)
|
||||
|
@ -277,36 +542,55 @@ LIST_mips4kc_el=""
|
|||
|
||||
LIST_mips5kc_el=""
|
||||
|
||||
LIST_au1xx0_el="dbau1550_el"
|
||||
LIST_au1xx0_el=" \
|
||||
dbau1550_el \
|
||||
"
|
||||
|
||||
LIST_mips_el="${LIST_mips4kc_el} ${LIST_mips5kc_el} ${LIST_au1xx0_el}"
|
||||
LIST_mips_el=" \
|
||||
${LIST_mips4kc_el} \
|
||||
${LIST_mips5kc_el} \
|
||||
${LIST_au1xx0_el} \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## i386 Systems
|
||||
#########################################################################
|
||||
|
||||
LIST_I486="sc520_cdp sc520_spunk sc520_spunk_rel"
|
||||
LIST_I486=" \
|
||||
sc520_cdp \
|
||||
sc520_spunk \
|
||||
sc520_spunk_rel \
|
||||
"
|
||||
|
||||
LIST_x86="${LIST_I486}"
|
||||
LIST_x86=" \
|
||||
${LIST_I486} \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## NIOS Systems
|
||||
#########################################################################
|
||||
|
||||
LIST_nios=" \
|
||||
ADNPESC1 ADNPESC1_base_32 \
|
||||
ADNPESC1_DNPEVA2_base_32 \
|
||||
DK1C20 DK1C20_standard_32 \
|
||||
DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20 \
|
||||
LIST_nios=" \
|
||||
ADNPESC1 \
|
||||
ADNPESC1_base_32 \
|
||||
ADNPESC1_DNPEVA2_base_32\
|
||||
DK1C20 \
|
||||
DK1C20_standard_32 \
|
||||
DK1S10 \
|
||||
DK1S10_standard_32 \
|
||||
DK1S10_mtx_ldk_20 \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## Nios-II Systems
|
||||
#########################################################################
|
||||
|
||||
LIST_nios2=" \
|
||||
EP1C20 EP1S10 EP1S40 \
|
||||
PCI5441 PK1C20 \
|
||||
LIST_nios2=" \
|
||||
EP1C20 \
|
||||
EP1S10 \
|
||||
EP1S40 \
|
||||
PCI5441 \
|
||||
PK1C20 \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
|
@ -314,31 +598,44 @@ LIST_nios2=" \
|
|||
#########################################################################
|
||||
|
||||
LIST_microblaze=" \
|
||||
suzaku ml401 xupv2p
|
||||
suzaku \
|
||||
ml401 \
|
||||
xupv2p \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## ColdFire Systems
|
||||
#########################################################################
|
||||
|
||||
LIST_coldfire=" \
|
||||
cobra5272 EB+MCF-EV123 EB+MCF-EV123_internal \
|
||||
idmr M5271EVB M5272C3 M5282EVB \
|
||||
TASREG r5200 M5271EVB \
|
||||
LIST_coldfire=" \
|
||||
cobra5272 \
|
||||
EB+MCF-EV123 \
|
||||
EB+MCF-EV123_internal \
|
||||
idmr \
|
||||
M5271EVB \
|
||||
M5272C3 \
|
||||
M5282EVB \
|
||||
TASREG \
|
||||
r5200 \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## AVR32 Systems
|
||||
#########################################################################
|
||||
|
||||
LIST_avr32="atstk1002"
|
||||
LIST_avr32=" \
|
||||
atstk1002 \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
## Blackfin Systems
|
||||
#########################################################################
|
||||
|
||||
LIST_blackfin=" \
|
||||
bf533-ezkit bf533-stamp bf537-stamp bf561-ezkit \
|
||||
LIST_blackfin=" \
|
||||
bf533-ezkit \
|
||||
bf533-stamp \
|
||||
bf537-stamp \
|
||||
bf561-ezkit \
|
||||
"
|
||||
|
||||
#-----------------------------------------------------------------------
|
||||
|
|
78
Makefile
78
Makefile
|
@ -34,6 +34,7 @@ HOSTARCH := $(shell uname -m | \
|
|||
-e s/arm.*/arm/ \
|
||||
-e s/sa110/arm/ \
|
||||
-e s/powerpc/ppc/ \
|
||||
-e s/ppc64/ppc/ \
|
||||
-e s/macppc/ppc/)
|
||||
|
||||
HOSTOS := $(shell uname -s | tr '[:upper:]' '[:lower:]' | \
|
||||
|
@ -122,7 +123,7 @@ ifeq ($(HOSTARCH),$(ARCH))
|
|||
CROSS_COMPILE =
|
||||
else
|
||||
ifeq ($(ARCH),ppc)
|
||||
CROSS_COMPILE = powerpc-linux-
|
||||
CROSS_COMPILE = ppc_8xx-
|
||||
endif
|
||||
ifeq ($(ARCH),arm)
|
||||
CROSS_COMPILE = arm-linux-
|
||||
|
@ -213,6 +214,9 @@ LIBS += drivers/net/libnetdrv.a
|
|||
ifeq ($(CPU),mpc83xx)
|
||||
LIBS += drivers/qe/qe.a
|
||||
endif
|
||||
ifeq ($(CPU),mpc85xx)
|
||||
LIBS += drivers/qe/qe.a
|
||||
endif
|
||||
LIBS += drivers/sk98lin/libsk98lin.a
|
||||
LIBS += post/libpost.a post/drivers/libpostdrivers.a
|
||||
LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \
|
||||
|
@ -659,6 +663,9 @@ AdderII_config \
|
|||
@echo "#define CONFIG_MPC852T" > $(obj)include/config.h)
|
||||
@$(MKCONFIG) -a Adder ppc mpc8xx adder
|
||||
|
||||
AdderUSB_config: unconfig
|
||||
@./mkconfig -a AdderUSB ppc mpc8xx adder
|
||||
|
||||
ADS860_config \
|
||||
FADS823_config \
|
||||
FADS850SAR_config \
|
||||
|
@ -1137,6 +1144,12 @@ EXBITGEN_config: unconfig
|
|||
G2000_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx g2000
|
||||
|
||||
hcu4_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu4 netstal
|
||||
|
||||
hcu5_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx hcu5 netstal
|
||||
|
||||
HH405_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx hh405 esd
|
||||
|
||||
|
@ -1256,6 +1269,9 @@ rainier_nand_config: unconfig
|
|||
sc3_config:unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx sc3
|
||||
|
||||
taihu_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx taihu amcc
|
||||
|
||||
taishan_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx taishan amcc
|
||||
|
||||
|
@ -1293,6 +1309,9 @@ yellowstone_config: unconfig
|
|||
yucca_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx yucca amcc
|
||||
|
||||
zeus_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx zeus
|
||||
|
||||
#########################################################################
|
||||
## MPC8220 Systems
|
||||
#########################################################################
|
||||
|
@ -1664,15 +1683,18 @@ MPC8313ERDB_66_config: unconfig
|
|||
@mkdir -p $(obj)include
|
||||
@echo "" >$(obj)include/config.h ; \
|
||||
if [ "$(findstring _33_,$@)" ] ; then \
|
||||
echo "...33M ..." ; \
|
||||
echo -n "...33M ..." ; \
|
||||
echo "#define CFG_33MHZ" >>$(obj)include/config.h ; \
|
||||
fi ; \
|
||||
if [ "$(findstring _66_,$@)" ] ; then \
|
||||
echo "...66M..." ; \
|
||||
echo -n "...66M..." ; \
|
||||
echo "#define CFG_66MHZ" >>$(obj)include/config.h ; \
|
||||
fi ;
|
||||
@$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb
|
||||
|
||||
MPC8323ERDB_config: unconfig
|
||||
@$(MKCONFIG) -a MPC8323ERDB ppc mpc83xx mpc8323erdb freescale
|
||||
|
||||
MPC832XEMDS_config \
|
||||
MPC832XEMDS_HOST_33_config \
|
||||
MPC832XEMDS_HOST_66_config \
|
||||
|
@ -1680,7 +1702,7 @@ MPC832XEMDS_SLAVE_config: unconfig
|
|||
@mkdir -p $(obj)include
|
||||
@echo "" >$(obj)include/config.h ; \
|
||||
if [ "$(findstring _HOST_,$@)" ] ; then \
|
||||
echo "... PCI HOST " ; \
|
||||
echo -n "... PCI HOST " ; \
|
||||
echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
|
||||
fi ; \
|
||||
if [ "$(findstring _SLAVE_,$@)" ] ; then \
|
||||
|
@ -1689,11 +1711,11 @@ MPC832XEMDS_SLAVE_config: unconfig
|
|||
echo "#define CONFIG_PCISLAVE" >>$(obj)include/config.h ; \
|
||||
fi ; \
|
||||
if [ "$(findstring _33_,$@)" ] ; then \
|
||||
echo "...33M ..." ; \
|
||||
echo -n "...33M ..." ; \
|
||||
echo "#define PCI_33M" >>$(obj)include/config.h ; \
|
||||
fi ; \
|
||||
if [ "$(findstring _66_,$@)" ] ; then \
|
||||
echo "...66M..." ; \
|
||||
echo -n "...66M..." ; \
|
||||
echo "#define PCI_66M" >>$(obj)include/config.h ; \
|
||||
fi ;
|
||||
@$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds
|
||||
|
@ -1722,7 +1744,7 @@ MPC8360EMDS_SLAVE_config: unconfig
|
|||
@mkdir -p $(obj)include
|
||||
@echo "" >$(obj)include/config.h ; \
|
||||
if [ "$(findstring _HOST_,$@)" ] ; then \
|
||||
echo "... PCI HOST " ; \
|
||||
echo -n "... PCI HOST " ; \
|
||||
echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \
|
||||
fi ; \
|
||||
if [ "$(findstring _SLAVE_,$@)" ] ; then \
|
||||
|
@ -1731,11 +1753,11 @@ MPC8360EMDS_SLAVE_config: unconfig
|
|||
echo "#define CONFIG_PCISLAVE" >>$(obj)include/config.h ; \
|
||||
fi ; \
|
||||
if [ "$(findstring _33_,$@)" ] ; then \
|
||||
echo "...33M ..." ; \
|
||||
echo -n "...33M ..." ; \
|
||||
echo "#define PCI_33M" >>$(obj)include/config.h ; \
|
||||
fi ; \
|
||||
if [ "$(findstring _66_,$@)" ] ; then \
|
||||
echo "...66M..." ; \
|
||||
echo -n "...66M..." ; \
|
||||
echo "#define PCI_66M" >>$(obj)include/config.h ; \
|
||||
fi ;
|
||||
@$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds
|
||||
|
@ -1778,17 +1800,38 @@ MPC8540EVAL_66_slave_config: unconfig
|
|||
MPC8560ADS_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8560ads
|
||||
|
||||
MPC8541CDS_legacy_config \
|
||||
MPC8541CDS_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8541cds cds
|
||||
@mkdir -p $(obj)include
|
||||
@echo "" >$(obj)include/config.h ; \
|
||||
if [ "$(findstring _legacy_,$@)" ] ; then \
|
||||
echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
|
||||
echo "... legacy" ; \
|
||||
fi
|
||||
@$(MKCONFIG) -a MPC8541CDS ppc mpc85xx mpc8541cds cds
|
||||
|
||||
MPC8544DS_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8544ds freescale
|
||||
|
||||
MPC8548CDS_legacy_config \
|
||||
MPC8548CDS_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8548cds cds
|
||||
@mkdir -p $(obj)include
|
||||
@echo "" >$(obj)include/config.h ; \
|
||||
if [ "$(findstring _legacy_,$@)" ] ; then \
|
||||
echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
|
||||
echo "... legacy" ; \
|
||||
fi
|
||||
@$(MKCONFIG) -a MPC8548CDS ppc mpc85xx mpc8548cds cds
|
||||
|
||||
MPC8555CDS_legacy_config \
|
||||
MPC8555CDS_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8555cds cds
|
||||
@mkdir -p $(obj)include
|
||||
@echo "" >$(obj)include/config.h ; \
|
||||
if [ "$(findstring _legacy_,$@)" ] ; then \
|
||||
echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
|
||||
echo "... legacy" ; \
|
||||
fi
|
||||
@$(MKCONFIG) -a MPC8555CDS ppc mpc85xx mpc8555cds cds
|
||||
|
||||
MPC8568MDS_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds
|
||||
|
@ -1861,6 +1904,8 @@ TQM8560_config: unconfig
|
|||
MPC8641HPCN_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc mpc86xx mpc8641hpcn
|
||||
|
||||
sbc8641d_config: unconfig
|
||||
@./mkconfig $(@:_config=) ppc mpc86xx sbc8641d
|
||||
|
||||
#########################################################################
|
||||
## 74xx/7xx Systems
|
||||
|
@ -2016,6 +2061,15 @@ omap1510inn_config : unconfig
|
|||
omap5912osk_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm926ejs omap5912osk NULL omap
|
||||
|
||||
davinci_dvevm_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm926ejs dv-evm davinci davinci
|
||||
|
||||
davinci_schmoogie_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm926ejs schmoogie davinci davinci
|
||||
|
||||
davinci_sonata_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm926ejs sonata davinci davinci
|
||||
|
||||
omap1610inn_config \
|
||||
omap1610inn_cs0boot_config \
|
||||
omap1610inn_cs3boot_config \
|
||||
|
|
217
README
217
README
|
@ -228,113 +228,9 @@ build a config tool - later.
|
|||
|
||||
The following options need to be configured:
|
||||
|
||||
- CPU Type: Define exactly one of
|
||||
- CPU Type: Define exactly one, e.g. CONFIG_MPC85XX.
|
||||
|
||||
PowerPC based CPUs:
|
||||
-------------------
|
||||
CONFIG_MPC823, CONFIG_MPC850, CONFIG_MPC855, CONFIG_MPC860
|
||||
or CONFIG_MPC5xx
|
||||
or CONFIG_MPC8220
|
||||
or CONFIG_MPC824X, CONFIG_MPC8260
|
||||
or CONFIG_MPC85xx
|
||||
or CONFIG_IOP480
|
||||
or CONFIG_405GP
|
||||
or CONFIG_405EP
|
||||
or CONFIG_440
|
||||
or CONFIG_MPC74xx
|
||||
or CONFIG_750FX
|
||||
|
||||
ARM based CPUs:
|
||||
---------------
|
||||
CONFIG_SA1110
|
||||
CONFIG_ARM7
|
||||
CONFIG_PXA250
|
||||
CONFIG_CPU_MONAHANS
|
||||
|
||||
MicroBlaze based CPUs:
|
||||
----------------------
|
||||
CONFIG_MICROBLAZE
|
||||
|
||||
Nios-2 based CPUs:
|
||||
----------------------
|
||||
CONFIG_NIOS2
|
||||
|
||||
AVR32 based CPUs:
|
||||
----------------------
|
||||
CONFIG_AT32AP
|
||||
|
||||
- Board Type: Define exactly one of
|
||||
|
||||
PowerPC based boards:
|
||||
---------------------
|
||||
|
||||
CONFIG_ADCIOP CONFIG_FPS860L CONFIG_OXC
|
||||
CONFIG_ADS860 CONFIG_GEN860T CONFIG_PCI405
|
||||
CONFIG_AMX860 CONFIG_GENIETV CONFIG_PCIPPC2
|
||||
CONFIG_AP1000 CONFIG_GTH CONFIG_PCIPPC6
|
||||
CONFIG_AR405 CONFIG_gw8260 CONFIG_pcu_e
|
||||
CONFIG_BAB7xx CONFIG_hermes CONFIG_PIP405
|
||||
CONFIG_BC3450 CONFIG_hymod CONFIG_PM826
|
||||
CONFIG_c2mon CONFIG_IAD210 CONFIG_ppmc8260
|
||||
CONFIG_CANBT CONFIG_ICU862 CONFIG_QS823
|
||||
CONFIG_CCM CONFIG_IP860 CONFIG_QS850
|
||||
CONFIG_CMI CONFIG_IPHASE4539 CONFIG_QS860T
|
||||
CONFIG_cogent_mpc8260 CONFIG_IVML24 CONFIG_RBC823
|
||||
CONFIG_cogent_mpc8xx CONFIG_IVML24_128 CONFIG_RPXClassic
|
||||
CONFIG_CPCI405 CONFIG_IVML24_256 CONFIG_RPXlite
|
||||
CONFIG_CPCI4052 CONFIG_IVMS8 CONFIG_RPXsuper
|
||||
CONFIG_CPCIISER4 CONFIG_IVMS8_128 CONFIG_rsdproto
|
||||
CONFIG_CPU86 CONFIG_IVMS8_256 CONFIG_sacsng
|
||||
CONFIG_CRAYL1 CONFIG_JSE CONFIG_Sandpoint8240
|
||||
CONFIG_CSB272 CONFIG_LANTEC CONFIG_Sandpoint8245
|
||||
CONFIG_CU824 CONFIG_LITE5200B CONFIG_sbc8260
|
||||
CONFIG_DASA_SIM CONFIG_lwmon CONFIG_sbc8560
|
||||
CONFIG_DB64360 CONFIG_MBX CONFIG_SM850
|
||||
CONFIG_DB64460 CONFIG_MBX860T CONFIG_SPD823TS
|
||||
CONFIG_DU405 CONFIG_MHPC CONFIG_STXGP3
|
||||
CONFIG_DUET_ADS CONFIG_MIP405 CONFIG_SXNI855T
|
||||
CONFIG_EBONY CONFIG_MOUSSE CONFIG_TQM823L
|
||||
CONFIG_ELPPC CONFIG_MPC8260ADS CONFIG_TQM8260
|
||||
CONFIG_ELPT860 CONFIG_MPC8540ADS CONFIG_TQM850L
|
||||
CONFIG_ep8260 CONFIG_MPC8540EVAL CONFIG_TQM855L
|
||||
CONFIG_ERIC CONFIG_MPC8560ADS CONFIG_TQM860L
|
||||
CONFIG_ESTEEM192E CONFIG_MUSENKI CONFIG_TTTech
|
||||
CONFIG_ETX094 CONFIG_MVS1 CONFIG_UTX8245
|
||||
CONFIG_EVB64260 CONFIG_NETPHONE CONFIG_V37
|
||||
CONFIG_FADS823 CONFIG_NETTA CONFIG_W7OLMC
|
||||
CONFIG_FADS850SAR CONFIG_NETVIA CONFIG_W7OLMG
|
||||
CONFIG_FADS860T CONFIG_NX823 CONFIG_WALNUT
|
||||
CONFIG_FLAGADM CONFIG_OCRTC CONFIG_ZPC1900
|
||||
CONFIG_FPS850L CONFIG_ORSG CONFIG_ZUMA
|
||||
|
||||
ARM based boards:
|
||||
-----------------
|
||||
|
||||
CONFIG_ARMADILLO, CONFIG_AT91RM9200DK, CONFIG_CERF250,
|
||||
CONFIG_CSB637, CONFIG_DELTA, CONFIG_DNP1110,
|
||||
CONFIG_EP7312, CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE,
|
||||
CONFIG_IMPA7, CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610,
|
||||
CONFIG_KB9202, CONFIG_LART, CONFIG_LPD7A400,
|
||||
CONFIG_LUBBOCK, CONFIG_OSK_OMAP5912, CONFIG_OMAP2420H4,
|
||||
CONFIG_PLEB2, CONFIG_SHANNON, CONFIG_P2_OMAP730,
|
||||
CONFIG_SMDK2400, CONFIG_SMDK2410, CONFIG_TRAB,
|
||||
CONFIG_VCMA9
|
||||
|
||||
MicroBlaze based boards:
|
||||
------------------------
|
||||
|
||||
CONFIG_SUZAKU
|
||||
|
||||
Nios-2 based boards:
|
||||
------------------------
|
||||
|
||||
CONFIG_PCI5441 CONFIG_PK1C20
|
||||
CONFIG_EP1C20 CONFIG_EP1S10 CONFIG_EP1S40
|
||||
|
||||
AVR32 based boards:
|
||||
-------------------
|
||||
|
||||
CONFIG_ATSTK1000
|
||||
- Board Type: Define exactly one, e.g. CONFIG_MPC8540ADS.
|
||||
|
||||
- CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined)
|
||||
Define exactly one of
|
||||
|
@ -893,6 +789,71 @@ The following options need to be configured:
|
|||
CONFIG_USB_CONFIG
|
||||
for differential drivers: 0x00001000
|
||||
for single ended drivers: 0x00005000
|
||||
CFG_USB_EVENT_POLL
|
||||
May be defined to allow interrupt polling
|
||||
instead of using asynchronous interrupts
|
||||
|
||||
- USB Device:
|
||||
Define the below if you wish to use the USB console.
|
||||
Once firmware is rebuilt from a serial console issue the
|
||||
command "setenv stdin usbtty; setenv stdout usbtty" and
|
||||
attach your usb cable. The Unix command "dmesg" should print
|
||||
it has found a new device. The environment variable usbtty
|
||||
can be set to gserial or cdc_acm to enable your device to
|
||||
appear to a USB host as a Linux gserial device or a
|
||||
Common Device Class Abstract Control Model serial device.
|
||||
If you select usbtty = gserial you should be able to enumerate
|
||||
a Linux host by
|
||||
# modprobe usbserial vendor=0xVendorID product=0xProductID
|
||||
else if using cdc_acm, simply setting the environment
|
||||
variable usbtty to be cdc_acm should suffice. The following
|
||||
might be defined in YourBoardName.h
|
||||
|
||||
CONFIG_USB_DEVICE
|
||||
Define this to build a UDC device
|
||||
|
||||
CONFIG_USB_TTY
|
||||
Define this to have a tty type of device available to
|
||||
talk to the UDC device
|
||||
|
||||
CFG_CONSOLE_IS_IN_ENV
|
||||
Define this if you want stdin, stdout &/or stderr to
|
||||
be set to usbtty.
|
||||
|
||||
mpc8xx:
|
||||
CFG_USB_EXTC_CLK 0xBLAH
|
||||
Derive USB clock from external clock "blah"
|
||||
- CFG_USB_EXTC_CLK 0x02
|
||||
|
||||
CFG_USB_BRG_CLK 0xBLAH
|
||||
Derive USB clock from brgclk
|
||||
- CFG_USB_BRG_CLK 0x04
|
||||
|
||||
If you have a USB-IF assigned VendorID then you may wish to
|
||||
define your own vendor specific values either in BoardName.h
|
||||
or directly in usbd_vendor_info.h. If you don't define
|
||||
CONFIG_USBD_MANUFACTURER, CONFIG_USBD_PRODUCT_NAME,
|
||||
CONFIG_USBD_VENDORID and CONFIG_USBD_PRODUCTID, then U-Boot
|
||||
should pretend to be a Linux device to it's target host.
|
||||
|
||||
CONFIG_USBD_MANUFACTURER
|
||||
Define this string as the name of your company for
|
||||
- CONFIG_USBD_MANUFACTURER "my company"
|
||||
|
||||
CONFIG_USBD_PRODUCT_NAME
|
||||
Define this string as the name of your product
|
||||
- CONFIG_USBD_PRODUCT_NAME "acme usb device"
|
||||
|
||||
CONFIG_USBD_VENDORID
|
||||
Define this as your assigned Vendor ID from the USB
|
||||
Implementors Forum. This *must* be a genuine Vendor ID
|
||||
to avoid polluting the USB namespace.
|
||||
- CONFIG_USBD_VENDORID 0xFFFF
|
||||
|
||||
CONFIG_USBD_PRODUCTID
|
||||
Define this as the unique Product ID
|
||||
for your device
|
||||
- CONFIG_USBD_PRODUCTID 0xFFFF
|
||||
|
||||
|
||||
- MMC Support:
|
||||
|
@ -1105,6 +1066,16 @@ The following options need to be configured:
|
|||
Defines a default value for theIP address of a TFTP
|
||||
server to contact when using the "tftboot" command.
|
||||
|
||||
- Multicast TFTP Mode:
|
||||
CONFIG_MCAST_TFTP
|
||||
|
||||
Defines whether you want to support multicast TFTP as per
|
||||
rfc-2090; for example to work with atftp. Lets lots of targets
|
||||
tftp down the same boot image concurrently. Note: the ethernet
|
||||
driver in use must provide a function: mcast() to join/leave a
|
||||
multicast group.
|
||||
|
||||
CONFIG_BOOTP_RANDOM_DELAY
|
||||
- BOOTP Recovery Mode:
|
||||
CONFIG_BOOTP_RANDOM_DELAY
|
||||
|
||||
|
@ -1141,6 +1112,9 @@ The following options need to be configured:
|
|||
CONFIG_BOOTP_TIMEOFFSET
|
||||
CONFIG_BOOTP_VENDOREX
|
||||
|
||||
CONFIG_BOOTP_SERVERIP - TFTP server will be the serverip
|
||||
environment variable, not the BOOTP server.
|
||||
|
||||
CONFIG_BOOTP_DNS2 - If a DHCP client requests the DNS
|
||||
serverip from a DHCP server, it is possible that more
|
||||
than one DNS serverip is offered to the client.
|
||||
|
@ -1153,7 +1127,7 @@ The following options need to be configured:
|
|||
CONFIG_BOOTP_SEND_HOSTNAME - Some DHCP servers are capable
|
||||
to do a dynamic update of a DNS server. To do this, they
|
||||
need the hostname of the DHCP requester.
|
||||
If CONFIG_BOOP_SEND_HOSTNAME is defined, the content
|
||||
If CONFIG_BOOTP_SEND_HOSTNAME is defined, the content
|
||||
of the "hostname" environment variable is passed as
|
||||
option 12 to the DHCP server.
|
||||
|
||||
|
@ -2426,34 +2400,7 @@ is done by typing:
|
|||
make NAME_config
|
||||
|
||||
where "NAME_config" is the name of one of the existing
|
||||
configurations; the following names are supported:
|
||||
|
||||
ADCIOP_config FPS860L_config omap730p2_config
|
||||
ADS860_config GEN860T_config pcu_e_config
|
||||
Alaska8220_config
|
||||
AR405_config GENIETV_config PIP405_config
|
||||
at91rm9200dk_config GTH_config QS823_config
|
||||
CANBT_config hermes_config QS850_config
|
||||
cmi_mpc5xx_config hymod_config QS860T_config
|
||||
cogent_common_config IP860_config RPXlite_config
|
||||
cogent_mpc8260_config IVML24_config RPXlite_DW_config
|
||||
cogent_mpc8xx_config IVMS8_config RPXsuper_config
|
||||
CPCI405_config JSE_config rsdproto_config
|
||||
CPCIISER4_config LANTEC_config Sandpoint8240_config
|
||||
csb272_config lwmon_config sbc8260_config
|
||||
CU824_config MBX860T_config sbc8560_33_config
|
||||
DUET_ADS_config MBX_config sbc8560_66_config
|
||||
EBONY_config mpc7448hpc2_config SM850_config
|
||||
ELPT860_config MPC8260ADS_config SPD823TS_config
|
||||
ESTEEM192E_config MPC8540ADS_config stxgp3_config
|
||||
ETX094_config MPC8540EVAL_config SXNI855T_config
|
||||
FADS823_config NMPC8560ADS_config TQM823L_config
|
||||
FADS850SAR_config NETVIA_config TQM850L_config
|
||||
FADS860T_config omap1510inn_config TQM855L_config
|
||||
FPS850L_config omap1610h2_config TQM860L_config
|
||||
omap1610inn_config walnut_config
|
||||
omap5912osk_config Yukon8220_config
|
||||
omap2420h4_config ZPC1900_config
|
||||
configurations; see the main Makefile for supported names.
|
||||
|
||||
Note: for some board special configuration names may exist; check if
|
||||
additional information is available from the board vendor; for
|
||||
|
|
|
@ -85,9 +85,7 @@ long int initdram (int board_type)
|
|||
{
|
||||
u32 msize = 0;
|
||||
|
||||
puts ("Initializing\n");
|
||||
msize = fixed_sdram ();
|
||||
puts (" DDR RAM: ");
|
||||
|
||||
return msize;
|
||||
}
|
||||
|
|
|
@ -32,9 +32,170 @@ void ext_bus_cntlr_init(void);
|
|||
void configure_ppc440ep_pins(void);
|
||||
int is_nand_selected(void);
|
||||
|
||||
unsigned char cfg_simulate_spd_eeprom[128];
|
||||
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
|
||||
/*************************************************************************
|
||||
*
|
||||
* Bamboo has one bank onboard sdram (plus DIMM)
|
||||
*
|
||||
* Fixed memory is composed of :
|
||||
* MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
|
||||
* 13 row add bits, 10 column add bits (but 12 row used only).
|
||||
* ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
|
||||
* 12 row add bits, 10 column add bits.
|
||||
* Prepare a subset (only the used ones) of SPD data
|
||||
*
|
||||
* Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
|
||||
* the corresponding bank is divided by 2 due to number of Row addresses
|
||||
* 12 in the ECC module
|
||||
*
|
||||
* Assumes: 64 MB, ECC, non-registered
|
||||
* PLB @ 133 MHz
|
||||
*
|
||||
************************************************************************/
|
||||
const unsigned char cfg_simulate_spd_eeprom[128] = {
|
||||
0x80, /* number of SPD bytes used: 128 */
|
||||
0x08, /* total number bytes in SPD device = 256 */
|
||||
0x07, /* DDR ram */
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
0x0C, /* num Row Addr: 12 */
|
||||
#else
|
||||
0x0D, /* num Row Addr: 13 */
|
||||
#endif
|
||||
0x09, /* numColAddr: 9 */
|
||||
0x01, /* numBanks: 1 */
|
||||
0x20, /* Module data width: 32 bits */
|
||||
0x00, /* Module data width continued: +0 */
|
||||
0x04, /* 2.5 Volt */
|
||||
0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
0x02, /* ECC ON : 02 OFF : 00 */
|
||||
#else
|
||||
0x00, /* ECC ON : 02 OFF : 00 */
|
||||
#endif
|
||||
0x82, /* refresh Rate Type: Normal (15.625us) + Self refresh */
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0x01, /* wcsbc = 1 */
|
||||
0,
|
||||
0,
|
||||
0x0C, /* casBit (2,2.5) */
|
||||
0,
|
||||
0,
|
||||
0x00, /* not registered: 0 registered : 0x02*/
|
||||
0,
|
||||
0xA0, /* SDRAM Cycle Time (cas latency 2) = 10 ns */
|
||||
0,
|
||||
0x00, /* SDRAM Cycle Time (cas latency 1.5) = N.A */
|
||||
0,
|
||||
0x50, /* tRpNs = 20 ns */
|
||||
0,
|
||||
0x50, /* tRcdNs = 20 ns */
|
||||
45, /* tRasNs */
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
0x08, /* bankSizeID: 32MB */
|
||||
#else
|
||||
0x10, /* bankSizeID: 64MB */
|
||||
#endif
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0
|
||||
};
|
||||
#endif
|
||||
|
||||
gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
|
||||
#if 0
|
||||
{ /* GPIO Alternate1 Alternate2 Alternate3 */
|
||||
{
|
||||
|
@ -291,73 +452,12 @@ int checkboard(void)
|
|||
return (0);
|
||||
}
|
||||
|
||||
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
|
||||
/*************************************************************************
|
||||
*
|
||||
* init_spd_array -- Bamboo has one bank onboard sdram (plus DIMM)
|
||||
*
|
||||
* Fixed memory is composed of :
|
||||
* MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
|
||||
* 13 row add bits, 10 column add bits (but 12 row used only).
|
||||
* ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
|
||||
* 12 row add bits, 10 column add bits.
|
||||
* Prepare a subset (only the used ones) of SPD data
|
||||
*
|
||||
* Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
|
||||
* the corresponding bank is divided by 2 due to number of Row addresses
|
||||
* 12 in the ECC module
|
||||
*
|
||||
* Assumes: 64 MB, ECC, non-registered
|
||||
* PLB @ 133 MHz
|
||||
*
|
||||
************************************************************************/
|
||||
static void init_spd_array(void)
|
||||
{
|
||||
cfg_simulate_spd_eeprom[8] = 0x04; /* 2.5 Volt */
|
||||
cfg_simulate_spd_eeprom[2] = 0x07; /* DDR ram */
|
||||
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
cfg_simulate_spd_eeprom[11] = 0x02; /* ECC ON : 02 OFF : 00 */
|
||||
cfg_simulate_spd_eeprom[31] = 0x08; /* bankSizeID: 32MB */
|
||||
cfg_simulate_spd_eeprom[3] = 0x0C; /* num Row Addr: 12 */
|
||||
#else
|
||||
cfg_simulate_spd_eeprom[11] = 0x00; /* ECC ON : 02 OFF : 00 */
|
||||
cfg_simulate_spd_eeprom[31] = 0x10; /* bankSizeID: 64MB */
|
||||
cfg_simulate_spd_eeprom[3] = 0x0D; /* num Row Addr: 13 */
|
||||
#endif
|
||||
|
||||
cfg_simulate_spd_eeprom[4] = 0x09; /* numColAddr: 9 */
|
||||
cfg_simulate_spd_eeprom[5] = 0x01; /* numBanks: 1 */
|
||||
cfg_simulate_spd_eeprom[0] = 0x80; /* number of SPD bytes used: 128 */
|
||||
cfg_simulate_spd_eeprom[1] = 0x08; /* total number bytes in SPD device = 256 */
|
||||
cfg_simulate_spd_eeprom[21] = 0x00; /* not registered: 0 registered : 0x02*/
|
||||
cfg_simulate_spd_eeprom[6] = 0x20; /* Module data width: 32 bits */
|
||||
cfg_simulate_spd_eeprom[7] = 0x00; /* Module data width continued: +0 */
|
||||
cfg_simulate_spd_eeprom[15] = 0x01; /* wcsbc = 1 */
|
||||
cfg_simulate_spd_eeprom[27] = 0x50; /* tRpNs = 20 ns */
|
||||
cfg_simulate_spd_eeprom[29] = 0x50; /* tRcdNs = 20 ns */
|
||||
|
||||
cfg_simulate_spd_eeprom[30] = 45; /* tRasNs */
|
||||
|
||||
cfg_simulate_spd_eeprom[18] = 0x0C; /* casBit (2,2.5) */
|
||||
|
||||
cfg_simulate_spd_eeprom[9] = 0x75; /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
|
||||
cfg_simulate_spd_eeprom[23] = 0xA0; /* SDRAM Cycle Time (cas latency 2) = 10 ns */
|
||||
cfg_simulate_spd_eeprom[25] = 0x00; /* SDRAM Cycle Time (cas latency 1.5) = N.A */
|
||||
cfg_simulate_spd_eeprom[12] = 0x82; /* refresh Rate Type: Normal (15.625us) + Self refresh */
|
||||
}
|
||||
#endif
|
||||
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
|
||||
long dram_size;
|
||||
|
||||
/*
|
||||
* First write simulated values in eeprom array for onboard bank 0
|
||||
*/
|
||||
init_spd_array();
|
||||
|
||||
dram_size = spd_sdram();
|
||||
|
||||
return dram_size;
|
||||
|
@ -371,11 +471,12 @@ int testdram(void)
|
|||
{
|
||||
unsigned long *mem = (unsigned long *)0;
|
||||
const unsigned long kend = (1024 / sizeof(unsigned long));
|
||||
unsigned long k, n;
|
||||
unsigned long k, n, *p32, ctr;
|
||||
const unsigned long bend = CFG_MBYTES_SDRAM * 1024 * 1024;
|
||||
|
||||
mtmsr(0);
|
||||
|
||||
for (k = 0; k < CFG_KBYTES_SDRAM;
|
||||
for (k = 0; k < CFG_MBYTES_SDRAM*1024;
|
||||
++k, mem += (1024 / sizeof(unsigned long))) {
|
||||
if ((k & 1023) == 0) {
|
||||
printf("%3d MB\r", k / 1024);
|
||||
|
@ -399,6 +500,34 @@ int testdram(void)
|
|||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Perform a sequence test to ensure that all
|
||||
* memory locations are uniquely addressable
|
||||
*/
|
||||
ctr = 0;
|
||||
p32 = 0;
|
||||
while ((unsigned long)p32 != bend) {
|
||||
if (0 == ((unsigned long)p32 & ((1<<20)-1)))
|
||||
printf("Writing %3d MB\r", (unsigned long)p32 >> 20);
|
||||
*p32++ = ctr++;
|
||||
}
|
||||
|
||||
ctr = 0;
|
||||
p32 = 0;
|
||||
while ((unsigned long)p32 != bend) {
|
||||
if (0 == ((unsigned long)p32 & ((1<<20)-1)))
|
||||
printf("Verifying %3d MB\r", (unsigned long)p32 >> 20);
|
||||
|
||||
if (*p32 != ctr) {
|
||||
printf("SDRAM test fails at: %08x\n", p32);
|
||||
return 1;
|
||||
}
|
||||
|
||||
ctr++;
|
||||
p32++;
|
||||
}
|
||||
|
||||
printf("SDRAM test passes\n");
|
||||
return 0;
|
||||
}
|
||||
|
@ -1211,7 +1340,7 @@ void uart_selection_in_fpga(uart_config_nb_t uart_config)
|
|||
/*----------------------------------------------------------------------------+
|
||||
| init_default_gpio
|
||||
+----------------------------------------------------------------------------*/
|
||||
void init_default_gpio(void)
|
||||
void init_default_gpio(gpio_param_s (*gpio_tab)[GPIO_MAX])
|
||||
{
|
||||
int i;
|
||||
|
||||
|
@ -1281,7 +1410,7 @@ void init_default_gpio(void)
|
|||
|
|
||||
+----------------------------------------------------------------------------*/
|
||||
|
||||
void update_uart_ios(uart_config_nb_t uart_config)
|
||||
void update_uart_ios(uart_config_nb_t uart_config, gpio_param_s (*gpio_tab)[GPIO_MAX])
|
||||
{
|
||||
switch (uart_config)
|
||||
{
|
||||
|
@ -1409,7 +1538,7 @@ void update_uart_ios(uart_config_nb_t uart_config)
|
|||
/*----------------------------------------------------------------------------+
|
||||
| update_ndfc_ios(void).
|
||||
+----------------------------------------------------------------------------*/
|
||||
void update_ndfc_ios(void)
|
||||
void update_ndfc_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
|
||||
{
|
||||
/* Update GPIO Configuration Table */
|
||||
gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
|
||||
|
@ -1427,7 +1556,7 @@ void update_ndfc_ios(void)
|
|||
/*----------------------------------------------------------------------------+
|
||||
| update_zii_ios(void).
|
||||
+----------------------------------------------------------------------------*/
|
||||
void update_zii_ios(void)
|
||||
void update_zii_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
|
||||
{
|
||||
/* Update GPIO Configuration Table */
|
||||
gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
|
||||
|
@ -1477,7 +1606,7 @@ void update_zii_ios(void)
|
|||
/*----------------------------------------------------------------------------+
|
||||
| update_uic_0_3_irq_ios().
|
||||
+----------------------------------------------------------------------------*/
|
||||
void update_uic_0_3_irq_ios(void)
|
||||
void update_uic_0_3_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
|
||||
{
|
||||
gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
|
||||
gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
|
||||
|
@ -1495,7 +1624,7 @@ void update_uic_0_3_irq_ios(void)
|
|||
/*----------------------------------------------------------------------------+
|
||||
| update_uic_4_9_irq_ios().
|
||||
+----------------------------------------------------------------------------*/
|
||||
void update_uic_4_9_irq_ios(void)
|
||||
void update_uic_4_9_irq_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
|
||||
{
|
||||
gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
|
||||
gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
|
||||
|
@ -1516,7 +1645,7 @@ void update_uic_4_9_irq_ios(void)
|
|||
/*----------------------------------------------------------------------------+
|
||||
| update_dma_a_b_ios().
|
||||
+----------------------------------------------------------------------------*/
|
||||
void update_dma_a_b_ios(void)
|
||||
void update_dma_a_b_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
|
||||
{
|
||||
gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
|
||||
gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
|
||||
|
@ -1537,7 +1666,7 @@ void update_dma_a_b_ios(void)
|
|||
/*----------------------------------------------------------------------------+
|
||||
| update_dma_c_d_ios().
|
||||
+----------------------------------------------------------------------------*/
|
||||
void update_dma_c_d_ios(void)
|
||||
void update_dma_c_d_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
|
||||
{
|
||||
gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
|
||||
gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
|
||||
|
@ -1562,7 +1691,7 @@ void update_dma_c_d_ios(void)
|
|||
/*----------------------------------------------------------------------------+
|
||||
| update_ebc_master_ios().
|
||||
+----------------------------------------------------------------------------*/
|
||||
void update_ebc_master_ios(void)
|
||||
void update_ebc_master_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
|
||||
{
|
||||
gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
|
||||
gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
|
||||
|
@ -1580,7 +1709,7 @@ void update_ebc_master_ios(void)
|
|||
/*----------------------------------------------------------------------------+
|
||||
| update_usb2_device_ios().
|
||||
+----------------------------------------------------------------------------*/
|
||||
void update_usb2_device_ios(void)
|
||||
void update_usb2_device_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
|
||||
{
|
||||
gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
|
||||
gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
|
||||
|
@ -1611,20 +1740,21 @@ void update_usb2_device_ios(void)
|
|||
/*----------------------------------------------------------------------------+
|
||||
| update_pci_patch_ios().
|
||||
+----------------------------------------------------------------------------*/
|
||||
void update_pci_patch_ios(void)
|
||||
void update_pci_patch_ios(gpio_param_s (*gpio_tab)[GPIO_MAX])
|
||||
{
|
||||
gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
|
||||
gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------+
|
||||
| set_chip_gpio_configuration(unsigned char gpio_core)
|
||||
| set_chip_gpio_configuration(unsigned char gpio_core,
|
||||
| gpio_param_s (*gpio_tab)[GPIO_MAX])
|
||||
| Put the core impacted by clock modification and sharing in reset.
|
||||
| Config the select registers to resolve the sharing depending of the config.
|
||||
| Configure the GPIO registers.
|
||||
|
|
||||
+----------------------------------------------------------------------------*/
|
||||
void set_chip_gpio_configuration(unsigned char gpio_core)
|
||||
void set_chip_gpio_configuration(unsigned char gpio_core, gpio_param_s (*gpio_tab)[GPIO_MAX])
|
||||
{
|
||||
unsigned char i=0, j=0, reg_offset = 0;
|
||||
unsigned long gpio_reg, gpio_core_add;
|
||||
|
@ -1778,11 +1908,12 @@ void configure_ppc440ep_pins(void)
|
|||
CORE_NOT_SELECTED /* PCI_PATCH */
|
||||
};
|
||||
|
||||
gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
|
||||
|
||||
/* Table Default Initialisation + FPGA Access */
|
||||
init_default_gpio();
|
||||
set_chip_gpio_configuration(GPIO0);
|
||||
set_chip_gpio_configuration(GPIO1);
|
||||
init_default_gpio(gpio_tab);
|
||||
set_chip_gpio_configuration(GPIO0, gpio_tab);
|
||||
set_chip_gpio_configuration(GPIO1, gpio_tab);
|
||||
|
||||
/* Update Table */
|
||||
force_bup_core_selection(ppc440ep_core_selection, &config_val);
|
||||
|
@ -1817,7 +1948,7 @@ void configure_ppc440ep_pins(void)
|
|||
/* UIC 0:3 Selection */
|
||||
if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
|
||||
{
|
||||
update_uic_0_3_irq_ios();
|
||||
update_uic_0_3_irq_ios(gpio_tab);
|
||||
dma_a_b_unselect_in_fpga();
|
||||
}
|
||||
|
||||
|
@ -1825,21 +1956,21 @@ void configure_ppc440ep_pins(void)
|
|||
if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
|
||||
{
|
||||
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
|
||||
update_uic_4_9_irq_ios();
|
||||
update_uic_4_9_irq_ios(gpio_tab);
|
||||
}
|
||||
|
||||
/* DMA AB Selection */
|
||||
if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
|
||||
{
|
||||
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
|
||||
update_dma_a_b_ios();
|
||||
update_dma_a_b_ios(gpio_tab);
|
||||
dma_a_b_selection_in_fpga();
|
||||
}
|
||||
|
||||
/* DMA CD Selection */
|
||||
if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
|
||||
{
|
||||
update_dma_c_d_ios();
|
||||
update_dma_c_d_ios(gpio_tab);
|
||||
dma_c_d_selection_in_fpga();
|
||||
}
|
||||
|
||||
|
@ -1848,14 +1979,14 @@ void configure_ppc440ep_pins(void)
|
|||
{
|
||||
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
|
||||
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
|
||||
update_ebc_master_ios();
|
||||
update_ebc_master_ios(gpio_tab);
|
||||
}
|
||||
|
||||
/* PCI Patch Enable */
|
||||
if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
|
||||
{
|
||||
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
|
||||
update_pci_patch_ios();
|
||||
update_pci_patch_ios(gpio_tab);
|
||||
}
|
||||
|
||||
/* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
|
||||
|
@ -1871,7 +2002,7 @@ void configure_ppc440ep_pins(void)
|
|||
/* USB2.0 Device Selection */
|
||||
if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
|
||||
{
|
||||
update_usb2_device_ios();
|
||||
update_usb2_device_ios(gpio_tab);
|
||||
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
|
||||
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
|
||||
|
||||
|
@ -1904,7 +2035,7 @@ void configure_ppc440ep_pins(void)
|
|||
/* NAND Flash Selection */
|
||||
if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
|
||||
{
|
||||
update_ndfc_ios();
|
||||
update_ndfc_ios(gpio_tab);
|
||||
|
||||
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
|
||||
mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
|
||||
|
@ -1933,7 +2064,7 @@ void configure_ppc440ep_pins(void)
|
|||
/* MII Selection */
|
||||
if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
|
||||
{
|
||||
update_zii_ios();
|
||||
update_zii_ios(gpio_tab);
|
||||
mfsdr(sdr_mfr, sdr0_mfr);
|
||||
sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
|
||||
mtsdr(sdr_mfr, sdr0_mfr);
|
||||
|
@ -1944,7 +2075,7 @@ void configure_ppc440ep_pins(void)
|
|||
/* RMII Selection */
|
||||
if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
|
||||
{
|
||||
update_zii_ios();
|
||||
update_zii_ios(gpio_tab);
|
||||
mfsdr(sdr_mfr, sdr0_mfr);
|
||||
sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
|
||||
mtsdr(sdr_mfr, sdr0_mfr);
|
||||
|
@ -1955,7 +2086,7 @@ void configure_ppc440ep_pins(void)
|
|||
/* SMII Selection */
|
||||
if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
|
||||
{
|
||||
update_zii_ios();
|
||||
update_zii_ios(gpio_tab);
|
||||
mfsdr(sdr_mfr, sdr0_mfr);
|
||||
sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
|
||||
mtsdr(sdr_mfr, sdr0_mfr);
|
||||
|
@ -1992,7 +2123,7 @@ void configure_ppc440ep_pins(void)
|
|||
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
|
||||
break;
|
||||
}
|
||||
update_uart_ios(uart_configuration);
|
||||
update_uart_ios(uart_configuration, gpio_tab);
|
||||
|
||||
/* UART Selection in all cases */
|
||||
uart_selection_in_fpga(uart_configuration);
|
||||
|
@ -2014,8 +2145,8 @@ void configure_ppc440ep_pins(void)
|
|||
|
||||
/* Perform effective access to hardware */
|
||||
mtsdr(sdr_pfc1, sdr0_pfc1);
|
||||
set_chip_gpio_configuration(GPIO0);
|
||||
set_chip_gpio_configuration(GPIO1);
|
||||
set_chip_gpio_configuration(GPIO0, gpio_tab);
|
||||
set_chip_gpio_configuration(GPIO1, gpio_tab);
|
||||
|
||||
/* USB2.0 Device Reset must be done after GPIO setting */
|
||||
if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
|
||||
|
|
|
@ -51,13 +51,12 @@ tlbtab:
|
|||
tlbentry(CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
|
||||
#else
|
||||
tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 0, AC_R|AC_W|AC_X|SA_G)
|
||||
tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
#endif
|
||||
|
||||
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
|
||||
tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
|
||||
|
||||
tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
|
||||
/* PCI base & peripherals */
|
||||
tlbentry(CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I)
|
||||
|
||||
|
|
|
@ -141,8 +141,6 @@ SECTIONS
|
|||
*(COMMON)
|
||||
}
|
||||
|
||||
ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
|
||||
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
|
|
|
@ -20,10 +20,12 @@
|
|||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
long int spd_sdram(void);
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
long int spd_sdram(void);
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
|
@ -34,6 +36,15 @@ int board_early_init_f(void)
|
|||
mtdcr(uictr, 0x00000010); /* set int trigger levels */
|
||||
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
|
||||
|
||||
/*
|
||||
* Configure CPC0_PCI to enable PerWE as output
|
||||
* and enable the internal PCI arbiter if selected
|
||||
*/
|
||||
if (in_8((void *)FPGA_REG1) & FPGA_REG1_PCI_INT_ARB)
|
||||
mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
|
||||
else
|
||||
mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -745,19 +745,27 @@ static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
|
|||
if (info->flash_id & FLASH_BTYPE) {
|
||||
/* set sector offsets for bottom boot block type */
|
||||
info->start[0] = base + 0x00000000;
|
||||
info->start[1] = base + 0x00004000;
|
||||
info->start[2] = base + 0x00006000;
|
||||
info->start[3] = base + 0x00008000;
|
||||
for (i = 4; i < info->sector_count; i++) {
|
||||
info->start[1] = base + 0x00002000;
|
||||
info->start[2] = base + 0x00004000;
|
||||
info->start[3] = base + 0x00006000;
|
||||
info->start[4] = base + 0x00008000;
|
||||
info->start[5] = base + 0x0000a000;
|
||||
info->start[6] = base + 0x0000c000;
|
||||
info->start[7] = base + 0x0000e000;
|
||||
for (i = 8; i < info->sector_count; i++) {
|
||||
info->start[i] =
|
||||
base + (i * 0x00010000) - 0x00030000;
|
||||
base + ((i-7) * 0x00010000);
|
||||
}
|
||||
} else {
|
||||
/* set sector offsets for top boot block type */
|
||||
i = info->sector_count - 1;
|
||||
info->start[i--] = base + info->size - 0x00002000;
|
||||
info->start[i--] = base + info->size - 0x00004000;
|
||||
info->start[i--] = base + info->size - 0x00006000;
|
||||
info->start[i--] = base + info->size - 0x00008000;
|
||||
info->start[i--] = base + info->size - 0x0000a000;
|
||||
info->start[i--] = base + info->size - 0x0000c000;
|
||||
info->start[i--] = base + info->size - 0x0000e000;
|
||||
for (; i >= 0; i--) {
|
||||
info->start[i] = base + i * 0x00010000;
|
||||
}
|
||||
|
|
|
@ -104,6 +104,13 @@ int checkboard(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
|
||||
* board specific values.
|
||||
*/
|
||||
u32 ddr_clktr(u32 default_val) {
|
||||
return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* int testdram()
|
||||
|
|
49
board/amcc/taihu/Makefile
Normal file
49
board/amcc/taihu/Makefile
Normal file
|
@ -0,0 +1,49 @@
|
|||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o flash.o lcd.o update.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
$(LIB): $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
24
board/amcc/taihu/config.mk
Normal file
24
board/amcc/taihu/config.mk
Normal file
|
@ -0,0 +1,24 @@
|
|||
#
|
||||
# (C) Copyright 2000
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
TEXT_BASE = 0xFFFC0000
|
1083
board/amcc/taihu/flash.c
Normal file
1083
board/amcc/taihu/flash.c
Normal file
File diff suppressed because it is too large
Load diff
257
board/amcc/taihu/lcd.c
Normal file
257
board/amcc/taihu/lcd.c
Normal file
|
@ -0,0 +1,257 @@
|
|||
/*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/gpio.h>
|
||||
|
||||
#define LCD_CMD_ADDR 0x50100002
|
||||
#define LCD_DATA_ADDR 0x50100003
|
||||
#define LCD_BLK_CTRL CPLD_REG1_ADDR
|
||||
|
||||
static char *amcc_logo = "AMCC 405EP TAIHU EVALUATION KIT";
|
||||
static int addr_flag = 0x80;
|
||||
|
||||
static void lcd_bl_ctrl(char val)
|
||||
{
|
||||
out_8((u8 *) LCD_BLK_CTRL, in_8((u8 *) LCD_BLK_CTRL) | val);
|
||||
}
|
||||
|
||||
static void lcd_putc(int val)
|
||||
{
|
||||
int i = 100;
|
||||
char addr;
|
||||
|
||||
while (i--) {
|
||||
if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
|
||||
udelay(50);
|
||||
break;
|
||||
}
|
||||
udelay(50);
|
||||
}
|
||||
|
||||
if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
|
||||
printf("LCD is busy\n");
|
||||
return;
|
||||
}
|
||||
|
||||
addr = in_8((u8 *) LCD_CMD_ADDR);
|
||||
udelay(50);
|
||||
if ((addr != 0) && (addr % 0x10 == 0)) {
|
||||
addr_flag ^= 0x40;
|
||||
out_8((u8 *) LCD_CMD_ADDR, addr_flag);
|
||||
}
|
||||
|
||||
udelay(50);
|
||||
out_8((u8 *) LCD_DATA_ADDR, val);
|
||||
udelay(50);
|
||||
}
|
||||
|
||||
static void lcd_puts(char *s)
|
||||
{
|
||||
char *p = s;
|
||||
int i = 100;
|
||||
|
||||
while (i--) {
|
||||
if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
|
||||
udelay(50);
|
||||
break;
|
||||
}
|
||||
udelay(50);
|
||||
}
|
||||
|
||||
if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
|
||||
printf("LCD is busy\n");
|
||||
return;
|
||||
}
|
||||
|
||||
while (*p)
|
||||
lcd_putc(*p++);
|
||||
}
|
||||
|
||||
static void lcd_put_logo(void)
|
||||
{
|
||||
int i = 100;
|
||||
char *p = amcc_logo;
|
||||
|
||||
while (i--) {
|
||||
if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
|
||||
udelay(50);
|
||||
break;
|
||||
}
|
||||
udelay(50);
|
||||
}
|
||||
|
||||
if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
|
||||
printf("LCD is busy\n");
|
||||
return;
|
||||
}
|
||||
|
||||
out_8((u8 *) LCD_CMD_ADDR, 0x80);
|
||||
while (*p)
|
||||
lcd_putc(*p++);
|
||||
}
|
||||
|
||||
int lcd_init(void)
|
||||
{
|
||||
puts("LCD: ");
|
||||
out_8((u8 *) LCD_CMD_ADDR, 0x38); /* set function:8-bit,2-line,5x7 font type */
|
||||
udelay(50);
|
||||
out_8((u8 *) LCD_CMD_ADDR, 0x0f); /* set display on,cursor on,blink on */
|
||||
udelay(50);
|
||||
out_8((u8 *) LCD_CMD_ADDR, 0x01); /* display clear */
|
||||
udelay(2000);
|
||||
out_8((u8 *) LCD_CMD_ADDR, 0x06); /* set entry */
|
||||
udelay(50);
|
||||
lcd_bl_ctrl(0x02); /* set backlight on */
|
||||
lcd_put_logo();
|
||||
puts("ready\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int do_lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
out_8((u8 *) LCD_CMD_ADDR, 0x01);
|
||||
udelay(2000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int do_lcd_puts (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
if (argc < 2) {
|
||||
printf("%s", cmdtp->usage);
|
||||
return 1;
|
||||
}
|
||||
lcd_puts(argv[1]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int do_lcd_putc (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
if (argc < 2) {
|
||||
printf("%s", cmdtp->usage);
|
||||
return 1;
|
||||
}
|
||||
lcd_putc((char)argv[1][0]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int do_lcd_cur (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
ulong count;
|
||||
ulong dir;
|
||||
char cur_addr;
|
||||
|
||||
if (argc < 3) {
|
||||
printf("%s", cmdtp->usage);
|
||||
return 1;
|
||||
}
|
||||
|
||||
count = simple_strtoul(argv[1], NULL, 16);
|
||||
if (count > 31) {
|
||||
printf("unable to shift > 0x20\n");
|
||||
count = 0;
|
||||
}
|
||||
|
||||
dir = simple_strtoul(argv[2], NULL, 16);
|
||||
cur_addr = in_8((u8 *) LCD_CMD_ADDR);
|
||||
udelay(50);
|
||||
|
||||
if (dir == 0x0) {
|
||||
if (addr_flag == 0x80) {
|
||||
if (count >= (cur_addr & 0xf)) {
|
||||
out_8((u8 *) LCD_CMD_ADDR, 0x80);
|
||||
udelay(50);
|
||||
count = 0;
|
||||
}
|
||||
} else {
|
||||
if (count >= ((cur_addr & 0x0f) + 0x0f)) {
|
||||
out_8((u8 *) LCD_CMD_ADDR, 0x80);
|
||||
addr_flag = 0x80;
|
||||
udelay(50);
|
||||
count = 0x0;
|
||||
} else if (count >= ( cur_addr & 0xf)) {
|
||||
count -= cur_addr & 0xf ;
|
||||
out_8((u8 *) LCD_CMD_ADDR, 0x80 | 0xf);
|
||||
addr_flag = 0x80;
|
||||
udelay(50);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
if (addr_flag == 0x80) {
|
||||
if (count >= (0x1f - (cur_addr & 0xf))) {
|
||||
count = 0x0;
|
||||
addr_flag = 0xc0;
|
||||
out_8((u8 *) LCD_CMD_ADDR, 0xc0 | 0xf);
|
||||
udelay(50);
|
||||
} else if ((count + (cur_addr & 0xf ))>= 0x0f) {
|
||||
count = count + (cur_addr & 0xf) - 0x0f;
|
||||
addr_flag = 0xc0;
|
||||
out_8((u8 *) LCD_CMD_ADDR, 0xc0);
|
||||
udelay(50);
|
||||
}
|
||||
} else if ((count + (cur_addr & 0xf )) >= 0x0f) {
|
||||
count = 0x0;
|
||||
out_8((u8 *) LCD_CMD_ADDR, 0xC0 | 0x0F);
|
||||
udelay(50);
|
||||
}
|
||||
}
|
||||
while (count--) {
|
||||
if (dir == 0)
|
||||
out_8((u8 *) LCD_CMD_ADDR, 0x10);
|
||||
else
|
||||
out_8((u8 *) LCD_CMD_ADDR, 0x14);
|
||||
udelay(50);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
lcd_cls, 1, 1, do_lcd_clear,
|
||||
"lcd_cls - lcd clear display\n",
|
||||
NULL
|
||||
);
|
||||
|
||||
U_BOOT_CMD(
|
||||
lcd_puts, 2, 1, do_lcd_puts,
|
||||
"lcd_puts - display string on lcd\n",
|
||||
"<string> - <string> to be displayed\n"
|
||||
);
|
||||
|
||||
U_BOOT_CMD(
|
||||
lcd_putc, 2, 1, do_lcd_putc,
|
||||
"lcd_putc - display char on lcd\n",
|
||||
"<char> - <char> to be displayed\n"
|
||||
);
|
||||
|
||||
U_BOOT_CMD(
|
||||
lcd_cur, 3, 1, do_lcd_cur,
|
||||
"lcd_cur - shift cursor on lcd\n",
|
||||
"<count> <dir> - shift cursor on lcd <count> times, direction is <dir> \n"
|
||||
" <count> - 0..31\n"
|
||||
" <dir> - 0=backward 1=forward\n"
|
||||
);
|
240
board/amcc/taihu/taihu.c
Normal file
240
board/amcc/taihu/taihu.c
Normal file
|
@ -0,0 +1,240 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2005
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* (C) Copyright 2005-2007
|
||||
* Beijing UD Technology Co., Ltd., taihusupport@amcc.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <spi.h>
|
||||
#include <asm/gpio.h>
|
||||
|
||||
extern int lcd_init(void);
|
||||
|
||||
/*
|
||||
* board_early_init_f
|
||||
*/
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
lcd_init();
|
||||
|
||||
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
|
||||
mtdcr(uicer, 0x00000000); /* disable all ints */
|
||||
mtdcr(uiccr, 0x00000000);
|
||||
mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */
|
||||
mtdcr(uictr, 0x00000000); /* set int trigger levels */
|
||||
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
|
||||
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
|
||||
|
||||
mtebc(pb3ap, CFG_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */
|
||||
mtebc(pb3cr, CFG_EBC_PB3CR);
|
||||
|
||||
/*
|
||||
* Configure CPC0_PCI to enable PerWE as output
|
||||
* and enable the internal PCI arbiter
|
||||
*/
|
||||
mtdcr(cpc0_pci, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
int checkboard(void)
|
||||
{
|
||||
char *s = getenv("serial#");
|
||||
|
||||
puts("Board: Taihu - AMCC PPC405EP Evaluation Board");
|
||||
|
||||
if (s != NULL) {
|
||||
puts(", serial# ");
|
||||
puts(s);
|
||||
}
|
||||
putc('\n');
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* long int initdram
|
||||
*
|
||||
************************************************************************/
|
||||
long int initdram(int board)
|
||||
{
|
||||
return CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS; /* 128Mbytes */
|
||||
}
|
||||
|
||||
static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
|
||||
{
|
||||
char stat;
|
||||
int i;
|
||||
|
||||
stat = in_8((u8 *) CPLD_REG0_ADDR);
|
||||
printf("SW2 status: ");
|
||||
for (i=0; i<4; i++) /* 4-position */
|
||||
printf("%d:%s ", i, stat & (0x08 >> i)?"on":"off");
|
||||
printf("\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD (
|
||||
sw2_stat, 1, 1, do_sw_stat,
|
||||
"sw2_stat - show status of switch 2\n",
|
||||
NULL
|
||||
);
|
||||
|
||||
static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
|
||||
{
|
||||
int led_no;
|
||||
|
||||
if (argc != 3) {
|
||||
printf("%s", cmd_tp->usage);
|
||||
return -1;
|
||||
}
|
||||
|
||||
led_no = simple_strtoul(argv[1], NULL, 16);
|
||||
if (led_no != 1 && led_no != 2) {
|
||||
printf("%s", cmd_tp->usage);
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (strcmp(argv[2],"off") == 0x0) {
|
||||
if (led_no == 1)
|
||||
gpio_write_bit(30, 1);
|
||||
else
|
||||
gpio_write_bit(31, 1);
|
||||
} else if (strcmp(argv[2],"on") == 0x0) {
|
||||
if (led_no == 1)
|
||||
gpio_write_bit(30, 0);
|
||||
else
|
||||
gpio_write_bit(31, 0);
|
||||
} else {
|
||||
printf("%s", cmd_tp->usage);
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD (
|
||||
led_ctl, 3, 1, do_led_ctl,
|
||||
"led_ctl - make led 1 or 2 on or off\n",
|
||||
"<led_no> <on/off> - make led <led_no> on/off,\n"
|
||||
"\tled_no is 1 or 2\t"
|
||||
);
|
||||
|
||||
#define SPI_CS_GPIO0 0
|
||||
#define SPI_SCLK_GPIO14 14
|
||||
#define SPI_DIN_GPIO15 15
|
||||
#define SPI_DOUT_GPIO16 16
|
||||
|
||||
void spi_scl(int bit)
|
||||
{
|
||||
gpio_write_bit(SPI_SCLK_GPIO14, bit);
|
||||
}
|
||||
|
||||
void spi_sda(int bit)
|
||||
{
|
||||
gpio_write_bit(SPI_DOUT_GPIO16, bit);
|
||||
}
|
||||
|
||||
unsigned char spi_read(void)
|
||||
{
|
||||
return (unsigned char)gpio_read_out_bit(SPI_DIN_GPIO15);
|
||||
}
|
||||
|
||||
void taihu_spi_chipsel(int cs)
|
||||
{
|
||||
gpio_write_bit(SPI_CS_GPIO0, cs);
|
||||
}
|
||||
|
||||
spi_chipsel_type spi_chipsel[]= {
|
||||
taihu_spi_chipsel
|
||||
};
|
||||
|
||||
int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
static unsigned char int_lines[32] = {
|
||||
29, 30, 27, 28, 29, 30, 25, 27,
|
||||
29, 30, 27, 28, 29, 30, 27, 28,
|
||||
29, 30, 27, 28, 29, 30, 27, 28,
|
||||
29, 30, 27, 28, 29, 30, 27, 28};
|
||||
|
||||
static void taihu_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
|
||||
{
|
||||
unsigned char int_line = int_lines[PCI_DEV(dev) & 31];
|
||||
|
||||
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
|
||||
}
|
||||
|
||||
int pci_pre_init(struct pci_controller *hose)
|
||||
{
|
||||
hose->fixup_irq = taihu_pci_fixup_irq;
|
||||
return 1;
|
||||
}
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#ifdef CFG_DRAM_TEST
|
||||
int testdram(void)
|
||||
{
|
||||
unsigned long *mem = (unsigned long *)0;
|
||||
const unsigned long kend = (1024 / sizeof(unsigned long));
|
||||
unsigned long k, n;
|
||||
unsigned long msr;
|
||||
unsigned long total_kbytes = CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS / 1024;
|
||||
|
||||
msr = mfmsr();
|
||||
mtmsr(msr & ~(MSR_EE));
|
||||
|
||||
for (k = 0; k < total_kbytes ;
|
||||
++k, mem += (1024 / sizeof(unsigned long))) {
|
||||
if ((k & 1023) == 0)
|
||||
printf("%3d MB\r", k / 1024);
|
||||
|
||||
memset(mem, 0xaaaaaaaa, 1024);
|
||||
for (n = 0; n < kend; ++n) {
|
||||
if (mem[n] != 0xaaaaaaaa) {
|
||||
printf("SDRAM test fails at: %08x\n",
|
||||
(uint) & mem[n]);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
memset(mem, 0x55555555, 1024);
|
||||
for (n = 0; n < kend; ++n) {
|
||||
if (mem[n] != 0x55555555) {
|
||||
printf("SDRAM test fails at: %08x\n",
|
||||
(uint) & mem[n]);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
printf("SDRAM test passes\n");
|
||||
mtmsr(msr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CFG_DRAM_TEST */
|
150
board/amcc/taihu/u-boot.lds
Normal file
150
board/amcc/taihu/u-boot.lds
Normal file
|
@ -0,0 +1,150 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
.resetvec 0xFFFFFFFC :
|
||||
{
|
||||
*(.resetvec)
|
||||
} = 0xffff
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
cpu/ppc4xx/kgdb.o (.text)
|
||||
cpu/ppc4xx/traps.o (.text)
|
||||
cpu/ppc4xx/interrupts.o (.text)
|
||||
cpu/ppc4xx/serial.o (.text)
|
||||
cpu/ppc4xx/cpu_init.o (.text)
|
||||
cpu/ppc4xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
/* . = env_offset;*/
|
||||
/* common/environment.o(.text)*/
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
*(.eh_frame)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
132
board/amcc/taihu/update.c
Normal file
132
board/amcc/taihu/update.c
Normal file
|
@ -0,0 +1,132 @@
|
|||
/*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/processor.h>
|
||||
#include <i2c.h>
|
||||
|
||||
#define PCI_M66EN 0x10
|
||||
|
||||
static uchar buf_33[] =
|
||||
{
|
||||
0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/
|
||||
0x80, /* 0x01~0x03:ptm1ms =0x80000001 */
|
||||
0x00,
|
||||
0x00,
|
||||
0x00, /* 0x04~0x06:ptm1la = 0x00000000 */
|
||||
0x00,
|
||||
0x00,
|
||||
0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */
|
||||
0x00,
|
||||
0x00,
|
||||
0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */
|
||||
0x00,
|
||||
0x00,
|
||||
0x10, /* 0x0d~0x0e:vendor id 0x1014*/
|
||||
0x14,
|
||||
0x00, /* 0x0f~0x10:device id 0x0000*/
|
||||
0x00,
|
||||
0x00, /* 0x11:revision 0x00 */
|
||||
0x00, /* 0x12~0x14:class 0x000000 */
|
||||
0x00,
|
||||
0x00,
|
||||
0x10, /* 0x15~0x16:subsystem vendor id */
|
||||
0xe8,
|
||||
0x00, /* 0x17~0x18:subsystem device id */
|
||||
0x00,
|
||||
0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */
|
||||
0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */
|
||||
0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */
|
||||
0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */
|
||||
0xbe, /* 0x1d: tun[24-31]=0xbe */
|
||||
0x00,
|
||||
0x00
|
||||
};
|
||||
|
||||
static uchar buf_66[] =
|
||||
{
|
||||
0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/
|
||||
0x80, /* 0x01~0x03:ptm1ms =0x80000001 */
|
||||
0x00,
|
||||
0x00,
|
||||
0x00, /* 0x04~0x06:ptm1la = 0x00000000 */
|
||||
0x00,
|
||||
0x00,
|
||||
0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */
|
||||
0x00,
|
||||
0x00,
|
||||
0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */
|
||||
0x00,
|
||||
0x00,
|
||||
0x10, /* 0x0d~0x0e:vendor id 0x1014*/
|
||||
0x14,
|
||||
0x00, /* 0x0f~0x10:device id 0x0000*/
|
||||
0x00,
|
||||
0x00, /* 0x11:revision 0x00 */
|
||||
0x00, /* 0x12~0x14:class 0x000000 */
|
||||
0x00,
|
||||
0x00,
|
||||
0x10, /* 0x15~0x16:subsystem vendor id */
|
||||
0xe8,
|
||||
0x00, /* 0x17~0x18:subsystem device id */
|
||||
0x00,
|
||||
0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */
|
||||
0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */
|
||||
0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */
|
||||
0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */
|
||||
0xbe, /* 0x1d: tun[24-31]=0xbe */
|
||||
0x00,
|
||||
0x00
|
||||
};
|
||||
|
||||
static int update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
ulong len = 0x20;
|
||||
uchar chip = CFG_I2C_EEPROM_ADDR;
|
||||
uchar *pbuf;
|
||||
uchar base;
|
||||
int i;
|
||||
|
||||
if ((*(volatile char*)CPLD_REG0_ADDR & PCI_M66EN) != PCI_M66EN) {
|
||||
pbuf = buf_33;
|
||||
base = 0x00;
|
||||
} else {
|
||||
pbuf = buf_66;
|
||||
base = 0x40;
|
||||
}
|
||||
|
||||
for (i = 0; i< len; i++, base++) {
|
||||
if (i2c_write(chip, base, 1, &pbuf[i],1)!= 0) {
|
||||
printf("i2c_write fail\n");
|
||||
return 1;
|
||||
}
|
||||
udelay(11000);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD (
|
||||
update_boot_eeprom, 1, 1, update_boot_eeprom,
|
||||
"update_boot_eeprom - update boot eeprom content\n",
|
||||
NULL
|
||||
);
|
|
@ -562,6 +562,40 @@ int checkboard (void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
|
||||
* board specific values.
|
||||
*/
|
||||
static int ppc440spe_rev_a(void)
|
||||
{
|
||||
if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA))
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 ddr_wrdtr(u32 default_val) {
|
||||
/*
|
||||
* Yucca boards with 440SPe rev. A need a slightly different setup
|
||||
* for the MCIF0_WRDTR register.
|
||||
*/
|
||||
if (ppc440spe_rev_a())
|
||||
return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV);
|
||||
|
||||
return default_val;
|
||||
}
|
||||
|
||||
u32 ddr_clktr(u32 default_val) {
|
||||
/*
|
||||
* Yucca boards with 440SPe rev. A need a slightly different setup
|
||||
* for the MCIF0_CLKTR register.
|
||||
*/
|
||||
if (ppc440spe_rev_a())
|
||||
return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
|
||||
|
||||
return default_val;
|
||||
}
|
||||
|
||||
#if defined(CFG_DRAM_TEST)
|
||||
int testdram (void)
|
||||
{
|
||||
|
|
2
board/at91rm9200dk/Makefile
Normal file → Executable file
2
board/at91rm9200dk/Makefile
Normal file → Executable file
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := at91rm9200dk.o at45.o flash.o
|
||||
COBJS := at91rm9200dk.o flash.o led.o mux.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
|
|
@ -1,621 +0,0 @@
|
|||
/* Driver for ATMEL DataFlash support
|
||||
* Author : Hamid Ikdoumi (Atmel)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#ifdef CONFIG_HAS_DATAFLASH
|
||||
#include <dataflash.h>
|
||||
|
||||
#define AT91C_SPI_CLK 10000000 /* Max Value = 10MHz to be compliant to
|
||||
the Continuous Array Read function */
|
||||
|
||||
/* AC Characteristics */
|
||||
/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
|
||||
#define DATAFLASH_TCSS (0xC << 16)
|
||||
#define DATAFLASH_TCHS (0x1 << 24)
|
||||
|
||||
#define AT91C_TIMEOUT_WRDY 200000
|
||||
#define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0 : NPCS0 %1110 */
|
||||
#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3 : NPCS3 %0111 */
|
||||
|
||||
void AT91F_SpiInit(void) {
|
||||
|
||||
/*-------------------------------------------------------------------*/
|
||||
/* SPI DataFlash Init */
|
||||
/*-------------------------------------------------------------------*/
|
||||
/* Configure PIOs */
|
||||
AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |
|
||||
AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK;
|
||||
AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |
|
||||
AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK;
|
||||
/* Enable CLock */
|
||||
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI;
|
||||
|
||||
/* Reset the SPI */
|
||||
AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;
|
||||
|
||||
/* Configure SPI in Master Mode with No CS selected !!! */
|
||||
AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;
|
||||
|
||||
/* Configure CS0 and CS3 */
|
||||
*(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
|
||||
DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
|
||||
|
||||
*(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
|
||||
DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
|
||||
|
||||
}
|
||||
|
||||
void AT91F_SpiEnable(int cs) {
|
||||
switch(cs) {
|
||||
case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
|
||||
AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
|
||||
AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & AT91C_SPI_PCS);
|
||||
break;
|
||||
case 3: /* Configure SPI CS3 for Serial DataFlash Card */
|
||||
/* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */
|
||||
AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7; /* Set in PIO mode */
|
||||
AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7; /* Configure in output */
|
||||
/* Clear Output */
|
||||
AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7;
|
||||
/* Configure PCS */
|
||||
AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
|
||||
AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
|
||||
break;
|
||||
}
|
||||
|
||||
/* SPI_Enable */
|
||||
AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* \fn AT91F_SpiWrite */
|
||||
/* \brief Set the PDC registers for a transfert */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc )
|
||||
{
|
||||
unsigned int timeout;
|
||||
|
||||
pDesc->state = BUSY;
|
||||
|
||||
AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
|
||||
|
||||
/* Initialize the Transmit and Receive Pointer */
|
||||
AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ;
|
||||
AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ;
|
||||
|
||||
/* Intialize the Transmit and Receive Counters */
|
||||
AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size;
|
||||
AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size;
|
||||
|
||||
if ( pDesc->tx_data_size != 0 ) {
|
||||
/* Initialize the Next Transmit and Next Receive Pointer */
|
||||
AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ;
|
||||
AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ;
|
||||
|
||||
/* Intialize the Next Transmit and Next Receive Counters */
|
||||
AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ;
|
||||
AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ;
|
||||
}
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
reset_timer_masked();
|
||||
timeout = 0;
|
||||
|
||||
AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
|
||||
while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT));
|
||||
AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
|
||||
pDesc->state = IDLE;
|
||||
|
||||
if (timeout >= CFG_SPI_WRITE_TOUT){
|
||||
printf("Error Timeout\n\r");
|
||||
return DATAFLASH_ERROR;
|
||||
}
|
||||
|
||||
return DATAFLASH_OK;
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
/* \fn AT91F_DataFlashSendCommand */
|
||||
/* \brief Generic function to send a command to the dataflash */
|
||||
/*----------------------------------------------------------------------*/
|
||||
AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
|
||||
AT91PS_DataFlash pDataFlash,
|
||||
unsigned char OpCode,
|
||||
unsigned int CmdSize,
|
||||
unsigned int DataflashAddress)
|
||||
{
|
||||
unsigned int adr;
|
||||
|
||||
if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
|
||||
return DATAFLASH_BUSY;
|
||||
|
||||
/* process the address to obtain page address and byte address */
|
||||
adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size));
|
||||
|
||||
/* fill the command buffer */
|
||||
pDataFlash->pDataFlashDesc->command[0] = OpCode;
|
||||
if (pDataFlash->pDevice->pages_number >= 16384) {
|
||||
pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24);
|
||||
pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16);
|
||||
pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8);
|
||||
pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF);
|
||||
} else {
|
||||
pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16);
|
||||
pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8);
|
||||
pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ;
|
||||
pDataFlash->pDataFlashDesc->command[4] = 0;
|
||||
}
|
||||
pDataFlash->pDataFlashDesc->command[5] = 0;
|
||||
pDataFlash->pDataFlashDesc->command[6] = 0;
|
||||
pDataFlash->pDataFlashDesc->command[7] = 0;
|
||||
|
||||
/* Initialize the SpiData structure for the spi write fuction */
|
||||
pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
|
||||
pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize ;
|
||||
pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
|
||||
pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize ;
|
||||
|
||||
/* send the command and read the data */
|
||||
return AT91F_SpiWrite (pDataFlash->pDataFlashDesc);
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
/* \fn AT91F_DataFlashGetStatus */
|
||||
/* \brief Read the status register of the dataflash */
|
||||
/*----------------------------------------------------------------------*/
|
||||
AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc)
|
||||
{
|
||||
AT91S_DataFlashStatus status;
|
||||
|
||||
/* if a transfert is in progress ==> return 0 */
|
||||
if( (pDesc->state) != IDLE)
|
||||
return DATAFLASH_BUSY;
|
||||
|
||||
/* first send the read status command (D7H) */
|
||||
pDesc->command[0] = DB_STATUS;
|
||||
pDesc->command[1] = 0;
|
||||
|
||||
pDesc->DataFlash_state = GET_STATUS;
|
||||
pDesc->tx_data_size = 0 ; /* Transmit the command and receive response */
|
||||
pDesc->tx_cmd_pt = pDesc->command ;
|
||||
pDesc->rx_cmd_pt = pDesc->command ;
|
||||
pDesc->rx_cmd_size = 2 ;
|
||||
pDesc->tx_cmd_size = 2 ;
|
||||
status = AT91F_SpiWrite (pDesc);
|
||||
|
||||
pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
/* \fn AT91F_DataFlashWaitReady */
|
||||
/* \brief wait for dataflash ready (bit7 of the status register == 1) */
|
||||
/*----------------------------------------------------------------------*/
|
||||
AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc pDataFlashDesc, unsigned int timeout)
|
||||
{
|
||||
pDataFlashDesc->DataFlash_state = IDLE;
|
||||
|
||||
do {
|
||||
AT91F_DataFlashGetStatus(pDataFlashDesc);
|
||||
timeout--;
|
||||
} while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0) );
|
||||
|
||||
if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80)
|
||||
return DATAFLASH_ERROR;
|
||||
|
||||
return DATAFLASH_OK;
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* Function Name : AT91F_DataFlashContinuousRead */
|
||||
/* Object : Continuous stream Read */
|
||||
/* Input Parameters : DataFlash Service */
|
||||
/* : <src> = dataflash address */
|
||||
/* : <*dataBuffer> = data buffer pointer */
|
||||
/* : <sizeToRead> = data buffer size */
|
||||
/* Return value : State of the dataflash */
|
||||
/*------------------------------------------------------------------------------*/
|
||||
AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
|
||||
AT91PS_DataFlash pDataFlash,
|
||||
int src,
|
||||
unsigned char *dataBuffer,
|
||||
int sizeToRead )
|
||||
{
|
||||
AT91S_DataFlashStatus status;
|
||||
/* Test the size to read in the device */
|
||||
if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
|
||||
return DATAFLASH_MEMORY_OVERFLOW;
|
||||
|
||||
pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
|
||||
pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead;
|
||||
pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
|
||||
pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead;
|
||||
|
||||
status = AT91F_DataFlashSendCommand (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src);
|
||||
/* Send the command to the dataflash */
|
||||
return(status);
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* Function Name : AT91F_DataFlashPagePgmBuf */
|
||||
/* Object : Main memory page program through buffer 1 or buffer 2 */
|
||||
/* Input Parameters : DataFlash Service */
|
||||
/* : <*src> = Source buffer */
|
||||
/* : <dest> = dataflash destination address */
|
||||
/* : <SizeToWrite> = data buffer size */
|
||||
/* Return value : State of the dataflash */
|
||||
/*------------------------------------------------------------------------------*/
|
||||
AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
|
||||
AT91PS_DataFlash pDataFlash,
|
||||
unsigned char *src,
|
||||
unsigned int dest,
|
||||
unsigned int SizeToWrite)
|
||||
{
|
||||
int cmdsize;
|
||||
pDataFlash->pDataFlashDesc->tx_data_pt = src ;
|
||||
pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ;
|
||||
pDataFlash->pDataFlashDesc->rx_data_pt = src;
|
||||
pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite;
|
||||
|
||||
cmdsize = 4;
|
||||
/* Send the command to the dataflash */
|
||||
if (pDataFlash->pDevice->pages_number >= 16384)
|
||||
cmdsize = 5;
|
||||
return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest));
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* Function Name : AT91F_MainMemoryToBufferTransfert */
|
||||
/* Object : Read a page in the SRAM Buffer 1 or 2 */
|
||||
/* Input Parameters : DataFlash Service */
|
||||
/* : Page concerned */
|
||||
/* : */
|
||||
/* Return value : State of the dataflash */
|
||||
/*------------------------------------------------------------------------------*/
|
||||
AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
|
||||
AT91PS_DataFlash pDataFlash,
|
||||
unsigned char BufferCommand,
|
||||
unsigned int page)
|
||||
{
|
||||
int cmdsize;
|
||||
/* Test if the buffer command is legal */
|
||||
if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF))
|
||||
return DATAFLASH_BAD_COMMAND;
|
||||
|
||||
/* no data to transmit or receive */
|
||||
pDataFlash->pDataFlashDesc->tx_data_size = 0;
|
||||
cmdsize = 4;
|
||||
if (pDataFlash->pDevice->pages_number >= 16384)
|
||||
cmdsize = 5;
|
||||
return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, page*pDataFlash->pDevice->pages_size));
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------- */
|
||||
/* Function Name : AT91F_DataFlashWriteBuffer */
|
||||
/* Object : Write data to the internal sram buffer 1 or 2 */
|
||||
/* Input Parameters : DataFlash Service */
|
||||
/* : <BufferCommand> = command to write buffer1 or buffer2 */
|
||||
/* : <*dataBuffer> = data buffer to write */
|
||||
/* : <bufferAddress> = address in the internal buffer */
|
||||
/* : <SizeToWrite> = data buffer size */
|
||||
/* Return value : State of the dataflash */
|
||||
/*------------------------------------------------------------------------------*/
|
||||
AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
|
||||
AT91PS_DataFlash pDataFlash,
|
||||
unsigned char BufferCommand,
|
||||
unsigned char *dataBuffer,
|
||||
unsigned int bufferAddress,
|
||||
int SizeToWrite )
|
||||
{
|
||||
int cmdsize;
|
||||
/* Test if the buffer command is legal */
|
||||
if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE))
|
||||
return DATAFLASH_BAD_COMMAND;
|
||||
|
||||
/* buffer address must be lower than page size */
|
||||
if (bufferAddress > pDataFlash->pDevice->pages_size)
|
||||
return DATAFLASH_BAD_ADDRESS;
|
||||
|
||||
if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
|
||||
return DATAFLASH_BUSY;
|
||||
|
||||
/* Send first Write Command */
|
||||
pDataFlash->pDataFlashDesc->command[0] = BufferCommand;
|
||||
pDataFlash->pDataFlashDesc->command[1] = 0;
|
||||
if (pDataFlash->pDevice->pages_number >= 16384) {
|
||||
pDataFlash->pDataFlashDesc->command[2] = 0;
|
||||
pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ;
|
||||
pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ;
|
||||
cmdsize = 5;
|
||||
} else {
|
||||
pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ;
|
||||
pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ;
|
||||
pDataFlash->pDataFlashDesc->command[4] = 0;
|
||||
cmdsize = 4;
|
||||
}
|
||||
|
||||
pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
|
||||
pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ;
|
||||
pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
|
||||
pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ;
|
||||
|
||||
pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer ;
|
||||
pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer ;
|
||||
pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite ;
|
||||
pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ;
|
||||
|
||||
return AT91F_SpiWrite(pDataFlash->pDataFlashDesc);
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* Function Name : AT91F_PageErase */
|
||||
/* Object : Erase a page */
|
||||
/* Input Parameters : DataFlash Service */
|
||||
/* : Page concerned */
|
||||
/* : */
|
||||
/* Return value : State of the dataflash */
|
||||
/*------------------------------------------------------------------------------*/
|
||||
AT91S_DataFlashStatus AT91F_PageErase(
|
||||
AT91PS_DataFlash pDataFlash,
|
||||
unsigned int page)
|
||||
{
|
||||
int cmdsize;
|
||||
/* Test if the buffer command is legal */
|
||||
/* no data to transmit or receive */
|
||||
pDataFlash->pDataFlashDesc->tx_data_size = 0;
|
||||
|
||||
cmdsize = 4;
|
||||
if (pDataFlash->pDevice->pages_number >= 16384)
|
||||
cmdsize = 5;
|
||||
return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, page*pDataFlash->pDevice->pages_size));
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* Function Name : AT91F_BlockErase */
|
||||
/* Object : Erase a Block */
|
||||
/* Input Parameters : DataFlash Service */
|
||||
/* : Page concerned */
|
||||
/* : */
|
||||
/* Return value : State of the dataflash */
|
||||
/*------------------------------------------------------------------------------*/
|
||||
AT91S_DataFlashStatus AT91F_BlockErase(
|
||||
AT91PS_DataFlash pDataFlash,
|
||||
unsigned int block)
|
||||
{
|
||||
int cmdsize;
|
||||
/* Test if the buffer command is legal */
|
||||
/* no data to transmit or receive */
|
||||
pDataFlash->pDataFlashDesc->tx_data_size = 0;
|
||||
cmdsize = 4;
|
||||
if (pDataFlash->pDevice->pages_number >= 16384)
|
||||
cmdsize = 5;
|
||||
return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, block*8*pDataFlash->pDevice->pages_size));
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* Function Name : AT91F_WriteBufferToMain */
|
||||
/* Object : Write buffer to the main memory */
|
||||
/* Input Parameters : DataFlash Service */
|
||||
/* : <BufferCommand> = command to send to buffer1 or buffer2 */
|
||||
/* : <dest> = main memory address */
|
||||
/* Return value : State of the dataflash */
|
||||
/*------------------------------------------------------------------------------*/
|
||||
AT91S_DataFlashStatus AT91F_WriteBufferToMain (
|
||||
AT91PS_DataFlash pDataFlash,
|
||||
unsigned char BufferCommand,
|
||||
unsigned int dest )
|
||||
{
|
||||
int cmdsize;
|
||||
/* Test if the buffer command is correct */
|
||||
if ((BufferCommand != DB_BUF1_PAGE_PGM) &&
|
||||
(BufferCommand != DB_BUF1_PAGE_ERASE_PGM) &&
|
||||
(BufferCommand != DB_BUF2_PAGE_PGM) &&
|
||||
(BufferCommand != DB_BUF2_PAGE_ERASE_PGM) )
|
||||
return DATAFLASH_BAD_COMMAND;
|
||||
|
||||
/* no data to transmit or receive */
|
||||
pDataFlash->pDataFlashDesc->tx_data_size = 0;
|
||||
|
||||
cmdsize = 4;
|
||||
if (pDataFlash->pDevice->pages_number >= 16384)
|
||||
cmdsize = 5;
|
||||
/* Send the command to the dataflash */
|
||||
return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest));
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* Function Name : AT91F_PartialPageWrite */
|
||||
/* Object : Erase partielly a page */
|
||||
/* Input Parameters : <page> = page number */
|
||||
/* : <AdrInpage> = adr to begin the fading */
|
||||
/* : <length> = Number of bytes to erase */
|
||||
/*------------------------------------------------------------------------------*/
|
||||
AT91S_DataFlashStatus AT91F_PartialPageWrite (
|
||||
AT91PS_DataFlash pDataFlash,
|
||||
unsigned char *src,
|
||||
unsigned int dest,
|
||||
unsigned int size)
|
||||
{
|
||||
unsigned int page;
|
||||
unsigned int AdrInPage;
|
||||
|
||||
page = dest / (pDataFlash->pDevice->pages_size);
|
||||
AdrInPage = dest % (pDataFlash->pDevice->pages_size);
|
||||
|
||||
/* Read the contents of the page in the Sram Buffer */
|
||||
AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page);
|
||||
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
|
||||
/*Update the SRAM buffer */
|
||||
AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size);
|
||||
|
||||
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
|
||||
|
||||
/* Erase page if a 128 Mbits device */
|
||||
if (pDataFlash->pDevice->pages_number >= 16384) {
|
||||
AT91F_PageErase(pDataFlash, page);
|
||||
/* Rewrite the modified Sram Buffer in the main memory */
|
||||
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
|
||||
}
|
||||
|
||||
/* Rewrite the modified Sram Buffer in the main memory */
|
||||
return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, (page*pDataFlash->pDevice->pages_size)));
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* Function Name : AT91F_DataFlashWrite */
|
||||
/* Object : */
|
||||
/* Input Parameters : <*src> = Source buffer */
|
||||
/* : <dest> = dataflash adress */
|
||||
/* : <size> = data buffer size */
|
||||
/*------------------------------------------------------------------------------*/
|
||||
AT91S_DataFlashStatus AT91F_DataFlashWrite(
|
||||
AT91PS_DataFlash pDataFlash,
|
||||
unsigned char *src,
|
||||
int dest,
|
||||
int size )
|
||||
{
|
||||
unsigned int length;
|
||||
unsigned int page;
|
||||
unsigned int status;
|
||||
|
||||
AT91F_SpiEnable(pDataFlash->pDevice->cs);
|
||||
|
||||
if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
|
||||
return DATAFLASH_MEMORY_OVERFLOW;
|
||||
|
||||
/* If destination does not fit a page start address */
|
||||
if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) {
|
||||
length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size)));
|
||||
|
||||
if (size < length)
|
||||
length = size;
|
||||
|
||||
if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length))
|
||||
return DATAFLASH_ERROR;
|
||||
|
||||
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
|
||||
|
||||
/* Update size, source and destination pointers */
|
||||
size -= length;
|
||||
dest += length;
|
||||
src += length;
|
||||
}
|
||||
|
||||
while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) {
|
||||
/* program dataflash page */
|
||||
page = (unsigned int)dest / (pDataFlash->pDevice->pages_size);
|
||||
|
||||
status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size);
|
||||
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
|
||||
|
||||
status = AT91F_PageErase(pDataFlash, page);
|
||||
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
|
||||
if (!status)
|
||||
return DATAFLASH_ERROR;
|
||||
|
||||
status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest);
|
||||
if(!status)
|
||||
return DATAFLASH_ERROR;
|
||||
|
||||
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
|
||||
|
||||
/* Update size, source and destination pointers */
|
||||
size -= pDataFlash->pDevice->pages_size ;
|
||||
dest += pDataFlash->pDevice->pages_size ;
|
||||
src += pDataFlash->pDevice->pages_size ;
|
||||
}
|
||||
|
||||
/* If still some bytes to read */
|
||||
if ( size > 0 ) {
|
||||
/* program dataflash page */
|
||||
if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) )
|
||||
return DATAFLASH_ERROR;
|
||||
|
||||
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
|
||||
}
|
||||
return DATAFLASH_OK;
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* Function Name : AT91F_DataFlashRead */
|
||||
/* Object : Read a block in dataflash */
|
||||
/* Input Parameters : */
|
||||
/* Return value : */
|
||||
/*------------------------------------------------------------------------------*/
|
||||
int AT91F_DataFlashRead(
|
||||
AT91PS_DataFlash pDataFlash,
|
||||
unsigned long addr,
|
||||
unsigned long size,
|
||||
char *buffer)
|
||||
{
|
||||
unsigned long SizeToRead;
|
||||
|
||||
AT91F_SpiEnable(pDataFlash->pDevice->cs);
|
||||
|
||||
if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
|
||||
return -1;
|
||||
|
||||
while (size) {
|
||||
SizeToRead = (size < 0x8000)? size:0x8000;
|
||||
|
||||
if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
|
||||
return -1;
|
||||
|
||||
if (AT91F_DataFlashContinuousRead (pDataFlash, addr, (uchar *)buffer, SizeToRead) != DATAFLASH_OK)
|
||||
return -1;
|
||||
|
||||
size -= SizeToRead;
|
||||
addr += SizeToRead;
|
||||
buffer += SizeToRead;
|
||||
}
|
||||
|
||||
return DATAFLASH_OK;
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* Function Name : AT91F_DataflashProbe */
|
||||
/* Object : */
|
||||
/* Input Parameters : */
|
||||
/* Return value : Dataflash status register */
|
||||
/*------------------------------------------------------------------------------*/
|
||||
int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc)
|
||||
{
|
||||
AT91F_SpiEnable(cs);
|
||||
AT91F_DataFlashGetStatus(pDesc);
|
||||
return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C);
|
||||
}
|
||||
|
||||
#endif
|
80
board/at91rm9200dk/led.c
Normal file
80
board/at91rm9200dk/led.c
Normal file
|
@ -0,0 +1,80 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* Atmel Nordic AB <www.atmel.com>
|
||||
* Ulf Samuelsson <ulf@atmel.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/AT91RM9200.h>
|
||||
|
||||
#define GREEN_LED AT91C_PIO_PB0
|
||||
#define YELLOW_LED AT91C_PIO_PB1
|
||||
#define RED_LED AT91C_PIO_PB2
|
||||
|
||||
void green_LED_on(void)
|
||||
{
|
||||
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
|
||||
PIOB->PIO_CODR = GREEN_LED;
|
||||
}
|
||||
|
||||
void yellow_LED_on(void)
|
||||
{
|
||||
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
|
||||
PIOB->PIO_CODR = YELLOW_LED;
|
||||
}
|
||||
|
||||
void red_LED_on(void)
|
||||
{
|
||||
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
|
||||
PIOB->PIO_CODR = RED_LED;
|
||||
}
|
||||
|
||||
void green_LED_off(void)
|
||||
{
|
||||
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
|
||||
PIOB->PIO_SODR = GREEN_LED;
|
||||
}
|
||||
|
||||
void yellow_LED_off(void)
|
||||
{
|
||||
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
|
||||
PIOB->PIO_SODR = YELLOW_LED;
|
||||
}
|
||||
|
||||
void red_LED_off(void)
|
||||
{
|
||||
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
|
||||
PIOB->PIO_SODR = RED_LED;
|
||||
}
|
||||
|
||||
|
||||
void LED_init (void)
|
||||
{
|
||||
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
|
||||
AT91PS_PMC PMC = AT91C_BASE_PMC;
|
||||
PMC->PMC_PCER = (1 << AT91C_ID_PIOB); /* Enable PIOB clock */
|
||||
/* Disable peripherals on LEDs */
|
||||
PIOB->PIO_PER = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0;
|
||||
/* Enable pins as outputs */
|
||||
PIOB->PIO_OER = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0;
|
||||
/* Turn all LEDs OFF */
|
||||
PIOB->PIO_SODR = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0;
|
||||
}
|
37
board/at91rm9200dk/mux.c
Normal file
37
board/at91rm9200dk/mux.c
Normal file
|
@ -0,0 +1,37 @@
|
|||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/hardware.h>
|
||||
#include <dataflash.h>
|
||||
|
||||
int AT91F_GetMuxStatus(void) {
|
||||
#ifdef DATAFLASH_MMC_SELECT
|
||||
AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT; /* Set in PIO mode */
|
||||
AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT; /* Configure in output */
|
||||
|
||||
|
||||
if(AT91C_BASE_PIOB->PIO_ODSR & DATAFLASH_MMC_SELECT) {
|
||||
return 1;
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
void AT91F_SelectMMC(void) {
|
||||
#ifdef DATAFLASH_MMC_SELECT
|
||||
AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT; /* Set in PIO mode */
|
||||
AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT; /* Configure in output */
|
||||
/* Set Output */
|
||||
AT91C_BASE_PIOB->PIO_SODR = DATAFLASH_MMC_SELECT;
|
||||
#endif
|
||||
}
|
||||
|
||||
void AT91F_SelectSPI(void) {
|
||||
#ifdef DATAFLASH_MMC_SELECT
|
||||
AT91C_BASE_PIOB->PIO_PER = DATAFLASH_MMC_SELECT; /* Set in PIO mode */
|
||||
AT91C_BASE_PIOB->PIO_OER = DATAFLASH_MMC_SELECT; /* Configure in output */
|
||||
/* Clear Output */
|
||||
AT91C_BASE_PIOB->PIO_CODR = DATAFLASH_MMC_SELECT;
|
||||
#endif
|
||||
}
|
|
@ -28,11 +28,16 @@ void mpc85xx_config_via(struct pci_controller *hose,
|
|||
pci_dev_t dev, struct pci_config_table *tab)
|
||||
{
|
||||
pci_dev_t bridge;
|
||||
unsigned int cmdstat;
|
||||
|
||||
/* Enable USB and IDE functions */
|
||||
pci_hose_write_config_byte(hose, dev, 0x48, 0x08);
|
||||
|
||||
pciauto_config_device(hose, dev);
|
||||
pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
|
||||
cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER;
|
||||
pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
|
||||
pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
|
||||
pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
|
||||
|
||||
/*
|
||||
* Force the backplane P2P bridge to have a window
|
||||
|
@ -40,7 +45,7 @@ void mpc85xx_config_via(struct pci_controller *hose,
|
|||
* This allows legacy I/O (i8259, etc) on the VIA
|
||||
* southbridge to be accessed.
|
||||
*/
|
||||
bridge = PCI_BDF(0,17,0);
|
||||
bridge = PCI_BDF(0,BRIDGE_ID,0);
|
||||
pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
|
||||
pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
|
||||
pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);
|
||||
|
|
|
@ -476,14 +476,17 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta
|
|||
|
||||
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
|
||||
{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
|
||||
{0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
|
||||
{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1,
|
||||
{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
|
||||
{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
|
||||
mpc85xx_config_via_usbide, {0,0,0}},
|
||||
{0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
|
||||
{0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
|
||||
{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5,
|
||||
{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
|
||||
mpc85xx_config_via_usb, {0,0,0}},
|
||||
{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
|
||||
mpc85xx_config_via_usb2, {0,0,0}},
|
||||
{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
|
||||
mpc85xx_config_via_power, {0,0,0}},
|
||||
{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}},
|
||||
{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
|
||||
mpc85xx_config_via_ac97, {0,0,0}},
|
||||
{},
|
||||
};
|
||||
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
#
|
||||
# Copyright 2004 Freescale Semiconductor.
|
||||
# Copyright 2004, 2007 Freescale Semiconductor.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
|
@ -23,7 +23,9 @@
|
|||
#
|
||||
# mpc8548cds board
|
||||
#
|
||||
ifndef TEXT_BASE
|
||||
TEXT_BASE = 0xfff80000
|
||||
endif
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_E500=1
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2004 Freescale Semiconductor.
|
||||
* Copyright 2004, 2007 Freescale Semiconductor.
|
||||
* Copyright 2002,2003, Motorola Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
|
@ -28,6 +28,12 @@
|
|||
#include <config.h>
|
||||
#include <mpc85xx.h>
|
||||
|
||||
#define LAWAR_TRGT_PCI1 0x00000000
|
||||
#define LAWAR_TRGT_PCI2 0x00100000
|
||||
#define LAWAR_TRGT_PCIE 0x00200000
|
||||
#define LAWAR_TRGT_RIO 0x00c00000
|
||||
#define LAWAR_TRGT_LBC 0x00400000
|
||||
#define LAWAR_TRGT_DDR 0x00f00000
|
||||
|
||||
/*
|
||||
* TLB0 and TLB1 Entries
|
||||
|
@ -47,8 +53,8 @@
|
|||
*/
|
||||
|
||||
#define entry_start \
|
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
|
||||
#define entry_end \
|
||||
0: mflr r0 ; \
|
||||
|
@ -84,8 +90,8 @@ tlb1_entry:
|
|||
#endif
|
||||
|
||||
/*
|
||||
* TLB0 16K Cacheable, non-guarded
|
||||
* 0xd001_0000 16K Temporary Global data for initialization
|
||||
* TLB0 16K Cacheable, guarded
|
||||
* Temporary Global data for initialization
|
||||
*
|
||||
* Use four 4K TLB0 entries. These entries must be cacheable
|
||||
* as they provide the bootstrap memory before the memory
|
||||
|
@ -97,28 +103,28 @@ tlb1_entry:
|
|||
.long TLB1_MAS0(0, 0, 0)
|
||||
.long TLB1_MAS1(1, 0, 0, 0, 0)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
|
||||
0,0,0,0,0,0,0,0)
|
||||
0,0,0,0,0,0,1,0)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
|
||||
0,0,0,0,0,1,0,1,0,1)
|
||||
|
||||
.long TLB1_MAS0(0, 0, 0)
|
||||
.long TLB1_MAS1(1, 0, 0, 0, 0)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
|
||||
0,0,0,0,0,0,0,0)
|
||||
0,0,0,0,0,0,1,0)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
|
||||
0,0,0,0,0,1,0,1,0,1)
|
||||
|
||||
.long TLB1_MAS0(0, 0, 0)
|
||||
.long TLB1_MAS1(1, 0, 0, 0, 0)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
|
||||
0,0,0,0,0,0,0,0)
|
||||
0,0,0,0,0,0,1,0)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
|
||||
0,0,0,0,0,1,0,1,0,1)
|
||||
|
||||
.long TLB1_MAS0(0, 0, 0)
|
||||
.long TLB1_MAS1(1, 0, 0, 0, 0)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
|
||||
0,0,0,0,0,0,0,0)
|
||||
0,0,0,0,0,0,1,0)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
|
||||
0,0,0,0,0,1,0,1,0,1)
|
||||
|
||||
|
@ -130,51 +136,44 @@ tlb1_entry:
|
|||
*/
|
||||
.long TLB1_MAS0(1, 0, 0)
|
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1)
|
||||
|
||||
/*
|
||||
* TLB 1: 256M Non-cacheable, guarded
|
||||
* 0x80000000 256M PCI1 MEM
|
||||
* TLB 1: 1G Non-cacheable, guarded
|
||||
* 0x80000000 1G PCI1/PCIE 8,9,a,b
|
||||
*/
|
||||
.long TLB1_MAS0(1, 1, 0)
|
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
|
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS), 0,0,0,0,1,0,1,0)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS), 0,0,0,0,0,1,0,1,0,1)
|
||||
|
||||
#ifdef CFG_RIO_MEM_PHYS
|
||||
/*
|
||||
* TLB 2: 256M Non-cacheable, guarded
|
||||
* 0x90000000 256M PCI2 MEM
|
||||
*/
|
||||
.long TLB1_MAS0(1, 2, 0)
|
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE),
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS),
|
||||
0,0,0,0,1,0,1,0)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE),
|
||||
0,0,0,0,0,1,0,1,0,1)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS), 0,0,0,0,0,1,0,1,0,1)
|
||||
|
||||
/*
|
||||
* TLB 3: 1GB Non-cacheable, guarded
|
||||
* 0xa0000000 256M PEX MEM First half
|
||||
* 0xb0000000 256M PEX MEM Second half
|
||||
* 0xc0000000 256M Rapid IO MEM First half
|
||||
* 0xd0000000 256M Rapid IO MEM Second half
|
||||
* TLB 3: 256M Non-cacheable, guarded
|
||||
*/
|
||||
.long TLB1_MAS0(1, 3, 0)
|
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
|
||||
|
||||
/*
|
||||
* TLB 4: Reserved for future usage
|
||||
*/
|
||||
|
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS + 0x10000000),
|
||||
0,0,0,0,1,0,1,0)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS + 0x10000000),
|
||||
0,0,0,0,0,1,0,1,0,1)
|
||||
#endif
|
||||
/*
|
||||
* TLB 5: 64M Non-cacheable, guarded
|
||||
* 0xe000_0000 1M CCSRBAR
|
||||
* 0xe200_0000 8M PCI1 IO
|
||||
* 0xe280_0000 8M PCI2 IO
|
||||
* 0xe300_0000 16M PEX IO
|
||||
* 0xe200_0000 1M PCI1 IO
|
||||
* 0xe210_0000 1M PCI2 IO
|
||||
* 0xe300_0000 1M PCIe IO
|
||||
*/
|
||||
.long TLB1_MAS0(1, 5, 0)
|
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
|
||||
|
@ -187,17 +186,18 @@ tlb1_entry:
|
|||
*/
|
||||
.long TLB1_MAS0(1, 6, 0)
|
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
|
||||
|
||||
/*
|
||||
* TLB 7: 1M Non-cacheable, guarded
|
||||
* 0xf8000000 1M CADMUS registers
|
||||
* TLB 7: 64M Non-cacheable, guarded
|
||||
* 0xf8000000 64M CADMUS registers, relocated L2SRAM
|
||||
*/
|
||||
.long TLB1_MAS0(1, 7, 0)
|
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
|
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
|
||||
|
||||
2:
|
||||
entry_end
|
||||
|
||||
|
@ -205,14 +205,13 @@ tlb1_entry:
|
|||
* LAW(Local Access Window) configuration:
|
||||
*
|
||||
* 0x0000_0000 0x7fff_ffff DDR 2G
|
||||
* 0x8000_0000 0x8fff_ffff PCI1 MEM 256M
|
||||
* 0x9000_0000 0x9fff_ffff PCI2 MEM 256M
|
||||
* 0xa000_0000 0xbfff_ffff PEX MEM 512M
|
||||
* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
|
||||
* 0xa000_0000 0xbfff_ffff PCIe MEM 512M
|
||||
* 0xc000_0000 0xdfff_ffff RapidIO 512M
|
||||
* 0xe000_0000 0xe000_ffff CCSR 1M
|
||||
* 0xe200_0000 0xe27f_ffff PCI1 IO 8M
|
||||
* 0xe280_0000 0xe2ff_ffff PCI2 IO 8M
|
||||
* 0xe300_0000 0xe3ff_ffff PEX IO 16M
|
||||
* 0xe200_0000 0xe10f_ffff PCI1 IO 1M
|
||||
* 0xe280_0000 0xe20f_ffff PCI2 IO 1M
|
||||
* 0xe300_0000 0xe30f_ffff PCIe IO 1M
|
||||
* 0xf000_0000 0xf3ff_ffff SDRAM 64M
|
||||
* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
|
||||
* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
|
||||
|
@ -222,47 +221,50 @@ tlb1_entry:
|
|||
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
|
||||
* If flash is 8M at default position (last 8M), no LAW needed.
|
||||
*
|
||||
* The defines below are 1-off of the actual LAWAR0 usage.
|
||||
* So LAWAR3 define uses the LAWAR4 register in the ECM.
|
||||
* LAW 0 is reserved for boot mapping
|
||||
*/
|
||||
|
||||
#define LAWBAR0 0
|
||||
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
|
||||
|
||||
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
|
||||
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
|
||||
|
||||
#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
|
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
|
||||
|
||||
#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
|
||||
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
|
||||
|
||||
#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
|
||||
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_8M))
|
||||
|
||||
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
|
||||
#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
|
||||
#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
|
||||
|
||||
#define LAWBAR6 ((CFG_PEX_MEM_BASE>>12) & 0xfffff)
|
||||
#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M))
|
||||
|
||||
#define LAWBAR7 ((CFG_PEX_IO_PHYS>>12) & 0xfffff)
|
||||
#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M))
|
||||
|
||||
#define LAWBAR8 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
|
||||
#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
|
||||
|
||||
.section .bootpg, "ax"
|
||||
.globl law_entry
|
||||
|
||||
law_entry:
|
||||
entry_start
|
||||
|
||||
.long (4f-3f)/8
|
||||
3:
|
||||
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
|
||||
.long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5,LAWBAR6,LAWAR6,LAWBAR7,LAWAR7
|
||||
.long LAWBAR8,LAWAR8
|
||||
.long 0
|
||||
.long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
|
||||
|
||||
#ifdef CFG_PCI1_MEM_PHYS
|
||||
.long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
|
||||
.long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
|
||||
|
||||
.long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
|
||||
.long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
|
||||
#endif
|
||||
|
||||
#ifdef CFG_PCI2_MEM_PHYS
|
||||
.long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff
|
||||
.long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
|
||||
|
||||
.long (CFG_PCI2_IO_PHYS>>12) & 0xfffff
|
||||
.long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
|
||||
#endif
|
||||
|
||||
#ifdef CFG_PCIE1_MEM_PHYS
|
||||
.long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
|
||||
.long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M)
|
||||
|
||||
.long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
|
||||
.long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M)
|
||||
#endif
|
||||
|
||||
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
|
||||
.long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
|
||||
.long LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
|
||||
|
||||
#ifdef CFG_RIO_MEM_PHYS
|
||||
.long (CFG_RIO_MEM_PHYS>>12) & 0xfffff
|
||||
.long LAWAR_EN | LAWAR_TRGT_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)
|
||||
#endif
|
||||
4:
|
||||
entry_end
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2004 Freescale Semiconductor.
|
||||
* Copyright 2004, 2007 Freescale Semiconductor.
|
||||
*
|
||||
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
|
||||
*
|
||||
|
@ -26,6 +26,7 @@
|
|||
#include <pci.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/immap_85xx.h>
|
||||
#include <asm/immap_fsl_pci.h>
|
||||
#include <spd.h>
|
||||
#include <miiphy.h>
|
||||
|
||||
|
@ -33,10 +34,15 @@
|
|||
#include "../common/eeprom.h"
|
||||
#include "../common/via.h"
|
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
#include <ft_build.h>
|
||||
#endif
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
||||
extern void ddr_enable_ecc(unsigned int dram_size);
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
extern long int spd_sdram(void);
|
||||
|
||||
void local_bus_init(void);
|
||||
|
@ -56,13 +62,6 @@ int checkboard (void)
|
|||
/* PCI slot in USER bits CSR[6:7] by convention. */
|
||||
uint pci_slot = get_pci_slot ();
|
||||
|
||||
uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
|
||||
uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
|
||||
uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
|
||||
uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
|
||||
|
||||
uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
|
||||
|
||||
uint cpu_board_rev = get_cpu_board_revision ();
|
||||
|
||||
printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
|
||||
|
@ -71,20 +70,6 @@ int checkboard (void)
|
|||
printf ("CPU Board Revision %d.%d (0x%04x)\n",
|
||||
MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
|
||||
MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
|
||||
|
||||
printf (" PCI1: %d bit, %s MHz, %s\n",
|
||||
(pci1_32) ? 32 : 64,
|
||||
(pci1_speed == 33000000) ? "33" :
|
||||
(pci1_speed == 66000000) ? "66" : "unknown",
|
||||
pci1_clk_sel ? "sync" : "async");
|
||||
|
||||
if (pci_dual) {
|
||||
printf (" PCI2: 32 bit, 66 MHz, %s\n",
|
||||
pci2_clk_sel ? "sync" : "async");
|
||||
} else {
|
||||
printf (" PCI2: disabled\n");
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize local bus.
|
||||
*/
|
||||
|
@ -102,6 +87,8 @@ int checkboard (void)
|
|||
*/
|
||||
gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
|
||||
|
||||
ecm->eedr = 0xffffffff; /* clear ecm errors */
|
||||
ecm->eeer = 0xffffffff; /* enable ecm errors */
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -176,6 +163,9 @@ local_bus_init(void)
|
|||
lbc->lcrr |= 0x00030000;
|
||||
|
||||
asm("sync;isync;msync");
|
||||
|
||||
lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
|
||||
lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -301,7 +291,7 @@ testdram(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
|
||||
/* For some reason the Tundra PCI bridge shows up on itself as a
|
||||
* different device. Work around that by refusing to configure it.
|
||||
*/
|
||||
|
@ -309,32 +299,189 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta
|
|||
|
||||
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
|
||||
{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
|
||||
{0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
|
||||
{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1,
|
||||
{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
|
||||
{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
|
||||
mpc85xx_config_via_usbide, {0,0,0}},
|
||||
{0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
|
||||
{0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
|
||||
{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5,
|
||||
{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
|
||||
mpc85xx_config_via_usb, {0,0,0}},
|
||||
{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
|
||||
mpc85xx_config_via_usb2, {0,0,0}},
|
||||
{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
|
||||
mpc85xx_config_via_power, {0,0,0}},
|
||||
{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}},
|
||||
{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
|
||||
mpc85xx_config_via_ac97, {0,0,0}},
|
||||
{},
|
||||
};
|
||||
|
||||
static struct pci_controller hose[] = {
|
||||
{ config_table: pci_mpc85xxcds_config_table,},
|
||||
#ifdef CONFIG_MPC85XX_PCI2
|
||||
{},
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct pci_controller pci1_hose = {
|
||||
config_table: pci_mpc85xxcds_config_table};
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#ifdef CONFIG_PCI2
|
||||
static struct pci_controller pci2_hose;
|
||||
#endif /* CONFIG_PCI2 */
|
||||
|
||||
#ifdef CONFIG_PCIE1
|
||||
static struct pci_controller pcie1_hose;
|
||||
#endif /* CONFIG_PCIE1 */
|
||||
|
||||
int first_free_busno=0;
|
||||
|
||||
void
|
||||
pci_init_board(void)
|
||||
{
|
||||
#ifdef CONFIG_PCI
|
||||
pci_mpc85xx_init(&hose);
|
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
||||
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
|
||||
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
|
||||
|
||||
|
||||
#ifdef CONFIG_PCI1
|
||||
{
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pci1_hose;
|
||||
struct pci_config_table *table;
|
||||
|
||||
uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
|
||||
uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
|
||||
uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
|
||||
|
||||
uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
|
||||
|
||||
uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
|
||||
|
||||
if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
|
||||
printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
|
||||
(pci_32) ? 32 : 64,
|
||||
(pci_speed == 33333000) ? "33" :
|
||||
(pci_speed == 66666000) ? "66" : "unknown",
|
||||
pci_clk_sel ? "sync" : "async",
|
||||
pci_agent ? "agent" : "host",
|
||||
pci_arb ? "arbiter" : "external-arbiter"
|
||||
);
|
||||
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CFG_PCI1_MEM_BASE,
|
||||
CFG_PCI1_MEM_PHYS,
|
||||
CFG_PCI1_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(hose->regions + 1,
|
||||
CFG_PCI1_IO_BASE,
|
||||
CFG_PCI1_IO_PHYS,
|
||||
CFG_PCI1_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
hose->region_count = 2;
|
||||
|
||||
/* relocate config table pointers */
|
||||
hose->config_table = \
|
||||
(struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
|
||||
for (table = hose->config_table; table && table->vendor; table++)
|
||||
table->config_device += gd->reloc_off;
|
||||
|
||||
hose->first_busno=first_free_busno;
|
||||
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
|
||||
|
||||
fsl_pci_init(hose);
|
||||
first_free_busno=hose->last_busno+1;
|
||||
printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
|
||||
#ifdef CONFIG_PCIX_CHECK
|
||||
if (!(gur->pordevsr & PORDEVSR_PCI)) {
|
||||
/* PCI-X init */
|
||||
if (CONFIG_SYS_CLK_FREQ < 66000000)
|
||||
printf("PCI-X will only work at 66 MHz\n");
|
||||
|
||||
reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
|
||||
| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
|
||||
pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
|
||||
}
|
||||
#endif
|
||||
} else {
|
||||
printf (" PCI: disabled\n");
|
||||
}
|
||||
}
|
||||
#else
|
||||
gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI2
|
||||
{
|
||||
uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
|
||||
uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
|
||||
if (pci_dual) {
|
||||
printf (" PCI2: 32 bit, 66 MHz, %s\n",
|
||||
pci2_clk_sel ? "sync" : "async");
|
||||
} else {
|
||||
printf (" PCI2: disabled\n");
|
||||
}
|
||||
}
|
||||
#else
|
||||
gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
|
||||
#endif /* CONFIG_PCI2 */
|
||||
|
||||
#ifdef CONFIG_PCIE1
|
||||
{
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pcie1_hose;
|
||||
int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
|
||||
|
||||
int pcie_configured = io_sel >= 1;
|
||||
|
||||
if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
|
||||
printf ("\n PCIE connected to slot as %s (base address %x)",
|
||||
pcie_ep ? "End Point" : "Root Complex",
|
||||
(uint)pci);
|
||||
|
||||
if (pci->pme_msg_det) {
|
||||
pci->pme_msg_det = 0xffffffff;
|
||||
debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
|
||||
}
|
||||
printf ("\n");
|
||||
|
||||
/* inbound */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CFG_PCI_MEMORY_BUS,
|
||||
CFG_PCI_MEMORY_PHYS,
|
||||
CFG_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 1,
|
||||
CFG_PCIE1_MEM_BASE,
|
||||
CFG_PCIE1_MEM_PHYS,
|
||||
CFG_PCIE1_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(hose->regions + 2,
|
||||
CFG_PCIE1_IO_BASE,
|
||||
CFG_PCIE1_IO_PHYS,
|
||||
CFG_PCIE1_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 3;
|
||||
|
||||
hose->first_busno=first_free_busno;
|
||||
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
|
||||
|
||||
fsl_pci_init(hose);
|
||||
printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
|
||||
|
||||
first_free_busno=hose->last_busno+1;
|
||||
|
||||
} else {
|
||||
printf (" PCIE: disabled\n");
|
||||
}
|
||||
}
|
||||
#else
|
||||
gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
int last_stage_init(void)
|
||||
|
@ -367,3 +514,32 @@ int last_stage_init(void)
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
void
|
||||
ft_pci_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
u32 *p;
|
||||
int len;
|
||||
|
||||
|
||||
#ifdef CONFIG_PCI1
|
||||
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
|
||||
if (p != NULL) {
|
||||
p[0] = 0;
|
||||
p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
|
||||
debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCIE1
|
||||
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len);
|
||||
if (p != NULL) {
|
||||
p[0] = 0;
|
||||
p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
|
||||
debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2004 Freescale Semiconductor.
|
||||
* Copyright 2004, 2007 Freescale Semiconductor.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
@ -71,7 +71,6 @@ SECTIONS
|
|||
cpu/mpc85xx/cpu.o (.text)
|
||||
drivers/tsec.o (.text)
|
||||
cpu/mpc85xx/speed.o (.text)
|
||||
cpu/mpc85xx/pci.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
|
|
|
@ -473,14 +473,17 @@ void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_ta
|
|||
|
||||
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
|
||||
{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
|
||||
{0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
|
||||
{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1,
|
||||
{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
|
||||
{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
|
||||
mpc85xx_config_via_usbide, {0,0,0}},
|
||||
{0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
|
||||
{0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
|
||||
{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5,
|
||||
{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
|
||||
mpc85xx_config_via_usb, {0,0,0}},
|
||||
{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
|
||||
mpc85xx_config_via_usb2, {0,0,0}},
|
||||
{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
|
||||
mpc85xx_config_via_power, {0,0,0}},
|
||||
{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}},
|
||||
{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
|
||||
mpc85xx_config_via_ac97, {0,0,0}},
|
||||
{},
|
||||
};
|
||||
|
||||
|
|
|
@ -122,7 +122,7 @@ long int initdram(int board_type)
|
|||
mem_conf_t *mem_conf;
|
||||
|
||||
mem_conf = get_mem_config(board_type);
|
||||
|
||||
|
||||
/* configure SDRAM start/end for detection */
|
||||
*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
|
||||
|
||||
|
@ -303,7 +303,7 @@ int checkboard(void)
|
|||
hw_id_t hw_id_tmp;
|
||||
char module_name_tmp[MODULE_NAME_MAXLEN] = "";
|
||||
|
||||
/*
|
||||
/*
|
||||
* We need I2C to access HW ID data from EEPROM, so we call i2c_init()
|
||||
* here despite the fact that it will be called again later on. We
|
||||
* also use a little trick to silence I2C-related output.
|
||||
|
@ -321,7 +321,7 @@ int checkboard(void)
|
|||
else
|
||||
printf("Board: unrecognized cm5200 module (%s)\n",
|
||||
module_name_tmp);
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -138,7 +138,7 @@ static char **hw_id_list[] = {
|
|||
cmu1_qa_hw_id,
|
||||
};
|
||||
|
||||
/* indices to the above list - keep in sync */
|
||||
/* indices to the above list - keep in sync */
|
||||
enum {
|
||||
CM1_QA,
|
||||
CM11_QA,
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* (C) Copyright 2007 Markus Kappeler <markus.kappeler@objectxp.com>
|
||||
*
|
||||
* Adapted for U-Boot 1.2 by Piotr Kruszynski <ppk@semihalf.com>
|
||||
* Adapted for U-Boot 1.2 by Piotr Kruszynski <ppk@semihalf.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
@ -27,7 +27,7 @@
|
|||
#include <i2c.h>
|
||||
#include <usb.h>
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_BSP)
|
||||
#ifdef CONFIG_CMD_BSB
|
||||
|
||||
int do_i2c(char *argv[])
|
||||
{
|
||||
|
@ -445,4 +445,4 @@ U_BOOT_CMD(
|
|||
"fkt usb\n"
|
||||
" - Test USB communication\n"
|
||||
);
|
||||
#endif /* CFG_CMD_BSP */
|
||||
#endif /* CONFIG_CMD_BSP */
|
||||
|
|
2
board/cmc_pu2/Makefile
Normal file → Executable file
2
board/cmc_pu2/Makefile
Normal file → Executable file
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := cmc_pu2.o at45.o flash.o load_sernum_ethaddr.o
|
||||
COBJS := cmc_pu2.o flash.o load_sernum_ethaddr.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
|
|
@ -1,621 +0,0 @@
|
|||
/* Driver for ATMEL DataFlash support
|
||||
* Author : Hamid Ikdoumi (Atmel)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#ifdef CONFIG_HAS_DATAFLASH
|
||||
#include <dataflash.h>
|
||||
|
||||
#define AT91C_SPI_CLK 10000000 /* Max Value = 10MHz to be compliant to
|
||||
the Continuous Array Read function */
|
||||
|
||||
/* AC Characteristics */
|
||||
/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
|
||||
#define DATAFLASH_TCSS (0xC << 16)
|
||||
#define DATAFLASH_TCHS (0x1 << 24)
|
||||
|
||||
#define AT91C_TIMEOUT_WRDY 200000
|
||||
#define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0 : NPCS0 %1110 */
|
||||
#define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3 : NPCS3 %0111 */
|
||||
|
||||
void AT91F_SpiInit(void) {
|
||||
|
||||
/*-------------------------------------------------------------------*/
|
||||
/* SPI DataFlash Init */
|
||||
/*-------------------------------------------------------------------*/
|
||||
/* Configure PIOs */
|
||||
AT91C_BASE_PIOA->PIO_ASR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |
|
||||
AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK;
|
||||
AT91C_BASE_PIOA->PIO_PDR = AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI | AT91C_PA5_NPCS2 |
|
||||
AT91C_PA6_NPCS3 | AT91C_PA0_MISO | AT91C_PA2_SPCK;
|
||||
/* Enable CLock */
|
||||
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI;
|
||||
|
||||
/* Reset the SPI */
|
||||
AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;
|
||||
|
||||
/* Configure SPI in Master Mode with No CS selected !!! */
|
||||
AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;
|
||||
|
||||
/* Configure CS0 and CS3 */
|
||||
*(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
|
||||
DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
|
||||
|
||||
*(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT &
|
||||
DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
|
||||
|
||||
}
|
||||
|
||||
void AT91F_SpiEnable(int cs) {
|
||||
switch(cs) {
|
||||
case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
|
||||
AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
|
||||
AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) & AT91C_SPI_PCS);
|
||||
break;
|
||||
case 3: /* Configure SPI CS3 for Serial DataFlash Card */
|
||||
/* Set up PIO SDC_TYPE to switch on DataFlash Card and not MMC/SDCard */
|
||||
AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB7; /* Set in PIO mode */
|
||||
AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB7; /* Configure in output */
|
||||
/* Clear Output */
|
||||
AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7;
|
||||
/* Configure PCS */
|
||||
AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
|
||||
AT91C_BASE_SPI->SPI_MR |= ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
|
||||
break;
|
||||
}
|
||||
|
||||
/* SPI_Enable */
|
||||
AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/* \fn AT91F_SpiWrite */
|
||||
/* \brief Set the PDC registers for a transfert */
|
||||
/*----------------------------------------------------------------------------*/
|
||||
unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc )
|
||||
{
|
||||
unsigned int timeout;
|
||||
|
||||
pDesc->state = BUSY;
|
||||
|
||||
AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
|
||||
|
||||
/* Initialize the Transmit and Receive Pointer */
|
||||
AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ;
|
||||
AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ;
|
||||
|
||||
/* Intialize the Transmit and Receive Counters */
|
||||
AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size;
|
||||
AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size;
|
||||
|
||||
if ( pDesc->tx_data_size != 0 ) {
|
||||
/* Initialize the Next Transmit and Next Receive Pointer */
|
||||
AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ;
|
||||
AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ;
|
||||
|
||||
/* Intialize the Next Transmit and Next Receive Counters */
|
||||
AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ;
|
||||
AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ;
|
||||
}
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
reset_timer_masked();
|
||||
timeout = 0;
|
||||
|
||||
AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
|
||||
while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) && ((timeout = get_timer_masked() ) < CFG_SPI_WRITE_TOUT));
|
||||
AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
|
||||
pDesc->state = IDLE;
|
||||
|
||||
if (timeout >= CFG_SPI_WRITE_TOUT){
|
||||
printf("Error Timeout\n\r");
|
||||
return DATAFLASH_ERROR;
|
||||
}
|
||||
|
||||
return DATAFLASH_OK;
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
/* \fn AT91F_DataFlashSendCommand */
|
||||
/* \brief Generic function to send a command to the dataflash */
|
||||
/*----------------------------------------------------------------------*/
|
||||
AT91S_DataFlashStatus AT91F_DataFlashSendCommand(
|
||||
AT91PS_DataFlash pDataFlash,
|
||||
unsigned char OpCode,
|
||||
unsigned int CmdSize,
|
||||
unsigned int DataflashAddress)
|
||||
{
|
||||
unsigned int adr;
|
||||
|
||||
if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
|
||||
return DATAFLASH_BUSY;
|
||||
|
||||
/* process the address to obtain page address and byte address */
|
||||
adr = ((DataflashAddress / (pDataFlash->pDevice->pages_size)) << pDataFlash->pDevice->page_offset) + (DataflashAddress % (pDataFlash->pDevice->pages_size));
|
||||
|
||||
/* fill the command buffer */
|
||||
pDataFlash->pDataFlashDesc->command[0] = OpCode;
|
||||
if (pDataFlash->pDevice->pages_number >= 16384) {
|
||||
pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x0F000000) >> 24);
|
||||
pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x00FF0000) >> 16);
|
||||
pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((adr & 0x0000FF00) >> 8);
|
||||
pDataFlash->pDataFlashDesc->command[4] = (unsigned char)(adr & 0x000000FF);
|
||||
} else {
|
||||
pDataFlash->pDataFlashDesc->command[1] = (unsigned char)((adr & 0x00FF0000) >> 16);
|
||||
pDataFlash->pDataFlashDesc->command[2] = (unsigned char)((adr & 0x0000FF00) >> 8);
|
||||
pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(adr & 0x000000FF) ;
|
||||
pDataFlash->pDataFlashDesc->command[4] = 0;
|
||||
}
|
||||
pDataFlash->pDataFlashDesc->command[5] = 0;
|
||||
pDataFlash->pDataFlashDesc->command[6] = 0;
|
||||
pDataFlash->pDataFlashDesc->command[7] = 0;
|
||||
|
||||
/* Initialize the SpiData structure for the spi write fuction */
|
||||
pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
|
||||
pDataFlash->pDataFlashDesc->tx_cmd_size = CmdSize ;
|
||||
pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
|
||||
pDataFlash->pDataFlashDesc->rx_cmd_size = CmdSize ;
|
||||
|
||||
/* send the command and read the data */
|
||||
return AT91F_SpiWrite (pDataFlash->pDataFlashDesc);
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
/* \fn AT91F_DataFlashGetStatus */
|
||||
/* \brief Read the status register of the dataflash */
|
||||
/*----------------------------------------------------------------------*/
|
||||
AT91S_DataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDesc pDesc)
|
||||
{
|
||||
AT91S_DataFlashStatus status;
|
||||
|
||||
/* if a transfert is in progress ==> return 0 */
|
||||
if( (pDesc->state) != IDLE)
|
||||
return DATAFLASH_BUSY;
|
||||
|
||||
/* first send the read status command (D7H) */
|
||||
pDesc->command[0] = DB_STATUS;
|
||||
pDesc->command[1] = 0;
|
||||
|
||||
pDesc->DataFlash_state = GET_STATUS;
|
||||
pDesc->tx_data_size = 0 ; /* Transmit the command and receive response */
|
||||
pDesc->tx_cmd_pt = pDesc->command ;
|
||||
pDesc->rx_cmd_pt = pDesc->command ;
|
||||
pDesc->rx_cmd_size = 2 ;
|
||||
pDesc->tx_cmd_size = 2 ;
|
||||
status = AT91F_SpiWrite (pDesc);
|
||||
|
||||
pDesc->DataFlash_state = *( (unsigned char *) (pDesc->rx_cmd_pt) +1);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
/* \fn AT91F_DataFlashWaitReady */
|
||||
/* \brief wait for dataflash ready (bit7 of the status register == 1) */
|
||||
/*----------------------------------------------------------------------*/
|
||||
AT91S_DataFlashStatus AT91F_DataFlashWaitReady(AT91PS_DataflashDesc pDataFlashDesc, unsigned int timeout)
|
||||
{
|
||||
pDataFlashDesc->DataFlash_state = IDLE;
|
||||
|
||||
do {
|
||||
AT91F_DataFlashGetStatus(pDataFlashDesc);
|
||||
timeout--;
|
||||
} while( ((pDataFlashDesc->DataFlash_state & 0x80) != 0x80) && (timeout > 0) );
|
||||
|
||||
if((pDataFlashDesc->DataFlash_state & 0x80) != 0x80)
|
||||
return DATAFLASH_ERROR;
|
||||
|
||||
return DATAFLASH_OK;
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* Function Name : AT91F_DataFlashContinuousRead */
|
||||
/* Object : Continuous stream Read */
|
||||
/* Input Parameters : DataFlash Service */
|
||||
/* : <src> = dataflash address */
|
||||
/* : <*dataBuffer> = data buffer pointer */
|
||||
/* : <sizeToRead> = data buffer size */
|
||||
/* Return value : State of the dataflash */
|
||||
/*------------------------------------------------------------------------------*/
|
||||
AT91S_DataFlashStatus AT91F_DataFlashContinuousRead (
|
||||
AT91PS_DataFlash pDataFlash,
|
||||
int src,
|
||||
unsigned char *dataBuffer,
|
||||
int sizeToRead )
|
||||
{
|
||||
AT91S_DataFlashStatus status;
|
||||
/* Test the size to read in the device */
|
||||
if ( (src + sizeToRead) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
|
||||
return DATAFLASH_MEMORY_OVERFLOW;
|
||||
|
||||
pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer;
|
||||
pDataFlash->pDataFlashDesc->rx_data_size = sizeToRead;
|
||||
pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer;
|
||||
pDataFlash->pDataFlashDesc->tx_data_size = sizeToRead;
|
||||
|
||||
status = AT91F_DataFlashSendCommand (pDataFlash, DB_CONTINUOUS_ARRAY_READ, 8, src);
|
||||
/* Send the command to the dataflash */
|
||||
return(status);
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* Function Name : AT91F_DataFlashPagePgmBuf */
|
||||
/* Object : Main memory page program through buffer 1 or buffer 2 */
|
||||
/* Input Parameters : DataFlash Service */
|
||||
/* : <*src> = Source buffer */
|
||||
/* : <dest> = dataflash destination address */
|
||||
/* : <SizeToWrite> = data buffer size */
|
||||
/* Return value : State of the dataflash */
|
||||
/*------------------------------------------------------------------------------*/
|
||||
AT91S_DataFlashStatus AT91F_DataFlashPagePgmBuf(
|
||||
AT91PS_DataFlash pDataFlash,
|
||||
unsigned char *src,
|
||||
unsigned int dest,
|
||||
unsigned int SizeToWrite)
|
||||
{
|
||||
int cmdsize;
|
||||
pDataFlash->pDataFlashDesc->tx_data_pt = src ;
|
||||
pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ;
|
||||
pDataFlash->pDataFlashDesc->rx_data_pt = src;
|
||||
pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite;
|
||||
|
||||
cmdsize = 4;
|
||||
/* Send the command to the dataflash */
|
||||
if (pDataFlash->pDevice->pages_number >= 16384)
|
||||
cmdsize = 5;
|
||||
return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_PGM_BUF1, cmdsize, dest));
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* Function Name : AT91F_MainMemoryToBufferTransfert */
|
||||
/* Object : Read a page in the SRAM Buffer 1 or 2 */
|
||||
/* Input Parameters : DataFlash Service */
|
||||
/* : Page concerned */
|
||||
/* : */
|
||||
/* Return value : State of the dataflash */
|
||||
/*------------------------------------------------------------------------------*/
|
||||
AT91S_DataFlashStatus AT91F_MainMemoryToBufferTransfert(
|
||||
AT91PS_DataFlash pDataFlash,
|
||||
unsigned char BufferCommand,
|
||||
unsigned int page)
|
||||
{
|
||||
int cmdsize;
|
||||
/* Test if the buffer command is legal */
|
||||
if ((BufferCommand != DB_PAGE_2_BUF1_TRF) && (BufferCommand != DB_PAGE_2_BUF2_TRF))
|
||||
return DATAFLASH_BAD_COMMAND;
|
||||
|
||||
/* no data to transmit or receive */
|
||||
pDataFlash->pDataFlashDesc->tx_data_size = 0;
|
||||
cmdsize = 4;
|
||||
if (pDataFlash->pDevice->pages_number >= 16384)
|
||||
cmdsize = 5;
|
||||
return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, page*pDataFlash->pDevice->pages_size));
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------- */
|
||||
/* Function Name : AT91F_DataFlashWriteBuffer */
|
||||
/* Object : Write data to the internal sram buffer 1 or 2 */
|
||||
/* Input Parameters : DataFlash Service */
|
||||
/* : <BufferCommand> = command to write buffer1 or buffer2 */
|
||||
/* : <*dataBuffer> = data buffer to write */
|
||||
/* : <bufferAddress> = address in the internal buffer */
|
||||
/* : <SizeToWrite> = data buffer size */
|
||||
/* Return value : State of the dataflash */
|
||||
/*------------------------------------------------------------------------------*/
|
||||
AT91S_DataFlashStatus AT91F_DataFlashWriteBuffer (
|
||||
AT91PS_DataFlash pDataFlash,
|
||||
unsigned char BufferCommand,
|
||||
unsigned char *dataBuffer,
|
||||
unsigned int bufferAddress,
|
||||
int SizeToWrite )
|
||||
{
|
||||
int cmdsize;
|
||||
/* Test if the buffer command is legal */
|
||||
if ((BufferCommand != DB_BUF1_WRITE) && (BufferCommand != DB_BUF2_WRITE))
|
||||
return DATAFLASH_BAD_COMMAND;
|
||||
|
||||
/* buffer address must be lower than page size */
|
||||
if (bufferAddress > pDataFlash->pDevice->pages_size)
|
||||
return DATAFLASH_BAD_ADDRESS;
|
||||
|
||||
if ( (pDataFlash->pDataFlashDesc->state) != IDLE)
|
||||
return DATAFLASH_BUSY;
|
||||
|
||||
/* Send first Write Command */
|
||||
pDataFlash->pDataFlashDesc->command[0] = BufferCommand;
|
||||
pDataFlash->pDataFlashDesc->command[1] = 0;
|
||||
if (pDataFlash->pDevice->pages_number >= 16384) {
|
||||
pDataFlash->pDataFlashDesc->command[2] = 0;
|
||||
pDataFlash->pDataFlashDesc->command[3] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ;
|
||||
pDataFlash->pDataFlashDesc->command[4] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ;
|
||||
cmdsize = 5;
|
||||
} else {
|
||||
pDataFlash->pDataFlashDesc->command[2] = (unsigned char)(((unsigned int)(bufferAddress & pDataFlash->pDevice->byte_mask)) >> 8) ;
|
||||
pDataFlash->pDataFlashDesc->command[3] = (unsigned char)((unsigned int)bufferAddress & 0x00FF) ;
|
||||
pDataFlash->pDataFlashDesc->command[4] = 0;
|
||||
cmdsize = 4;
|
||||
}
|
||||
|
||||
pDataFlash->pDataFlashDesc->tx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
|
||||
pDataFlash->pDataFlashDesc->tx_cmd_size = cmdsize ;
|
||||
pDataFlash->pDataFlashDesc->rx_cmd_pt = pDataFlash->pDataFlashDesc->command ;
|
||||
pDataFlash->pDataFlashDesc->rx_cmd_size = cmdsize ;
|
||||
|
||||
pDataFlash->pDataFlashDesc->rx_data_pt = dataBuffer ;
|
||||
pDataFlash->pDataFlashDesc->tx_data_pt = dataBuffer ;
|
||||
pDataFlash->pDataFlashDesc->rx_data_size = SizeToWrite ;
|
||||
pDataFlash->pDataFlashDesc->tx_data_size = SizeToWrite ;
|
||||
|
||||
return AT91F_SpiWrite(pDataFlash->pDataFlashDesc);
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* Function Name : AT91F_PageErase */
|
||||
/* Object : Erase a page */
|
||||
/* Input Parameters : DataFlash Service */
|
||||
/* : Page concerned */
|
||||
/* : */
|
||||
/* Return value : State of the dataflash */
|
||||
/*------------------------------------------------------------------------------*/
|
||||
AT91S_DataFlashStatus AT91F_PageErase(
|
||||
AT91PS_DataFlash pDataFlash,
|
||||
unsigned int page)
|
||||
{
|
||||
int cmdsize;
|
||||
/* Test if the buffer command is legal */
|
||||
/* no data to transmit or receive */
|
||||
pDataFlash->pDataFlashDesc->tx_data_size = 0;
|
||||
|
||||
cmdsize = 4;
|
||||
if (pDataFlash->pDevice->pages_number >= 16384)
|
||||
cmdsize = 5;
|
||||
return(AT91F_DataFlashSendCommand (pDataFlash, DB_PAGE_ERASE, cmdsize, page*pDataFlash->pDevice->pages_size));
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* Function Name : AT91F_BlockErase */
|
||||
/* Object : Erase a Block */
|
||||
/* Input Parameters : DataFlash Service */
|
||||
/* : Page concerned */
|
||||
/* : */
|
||||
/* Return value : State of the dataflash */
|
||||
/*------------------------------------------------------------------------------*/
|
||||
AT91S_DataFlashStatus AT91F_BlockErase(
|
||||
AT91PS_DataFlash pDataFlash,
|
||||
unsigned int block)
|
||||
{
|
||||
int cmdsize;
|
||||
/* Test if the buffer command is legal */
|
||||
/* no data to transmit or receive */
|
||||
pDataFlash->pDataFlashDesc->tx_data_size = 0;
|
||||
cmdsize = 4;
|
||||
if (pDataFlash->pDevice->pages_number >= 16384)
|
||||
cmdsize = 5;
|
||||
return(AT91F_DataFlashSendCommand (pDataFlash, DB_BLOCK_ERASE,cmdsize, block*8*pDataFlash->pDevice->pages_size));
|
||||
}
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* Function Name : AT91F_WriteBufferToMain */
|
||||
/* Object : Write buffer to the main memory */
|
||||
/* Input Parameters : DataFlash Service */
|
||||
/* : <BufferCommand> = command to send to buffer1 or buffer2 */
|
||||
/* : <dest> = main memory address */
|
||||
/* Return value : State of the dataflash */
|
||||
/*------------------------------------------------------------------------------*/
|
||||
AT91S_DataFlashStatus AT91F_WriteBufferToMain (
|
||||
AT91PS_DataFlash pDataFlash,
|
||||
unsigned char BufferCommand,
|
||||
unsigned int dest )
|
||||
{
|
||||
int cmdsize;
|
||||
/* Test if the buffer command is correct */
|
||||
if ((BufferCommand != DB_BUF1_PAGE_PGM) &&
|
||||
(BufferCommand != DB_BUF1_PAGE_ERASE_PGM) &&
|
||||
(BufferCommand != DB_BUF2_PAGE_PGM) &&
|
||||
(BufferCommand != DB_BUF2_PAGE_ERASE_PGM) )
|
||||
return DATAFLASH_BAD_COMMAND;
|
||||
|
||||
/* no data to transmit or receive */
|
||||
pDataFlash->pDataFlashDesc->tx_data_size = 0;
|
||||
|
||||
cmdsize = 4;
|
||||
if (pDataFlash->pDevice->pages_number >= 16384)
|
||||
cmdsize = 5;
|
||||
/* Send the command to the dataflash */
|
||||
return(AT91F_DataFlashSendCommand (pDataFlash, BufferCommand, cmdsize, dest));
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* Function Name : AT91F_PartialPageWrite */
|
||||
/* Object : Erase partielly a page */
|
||||
/* Input Parameters : <page> = page number */
|
||||
/* : <AdrInpage> = adr to begin the fading */
|
||||
/* : <length> = Number of bytes to erase */
|
||||
/*------------------------------------------------------------------------------*/
|
||||
AT91S_DataFlashStatus AT91F_PartialPageWrite (
|
||||
AT91PS_DataFlash pDataFlash,
|
||||
unsigned char *src,
|
||||
unsigned int dest,
|
||||
unsigned int size)
|
||||
{
|
||||
unsigned int page;
|
||||
unsigned int AdrInPage;
|
||||
|
||||
page = dest / (pDataFlash->pDevice->pages_size);
|
||||
AdrInPage = dest % (pDataFlash->pDevice->pages_size);
|
||||
|
||||
/* Read the contents of the page in the Sram Buffer */
|
||||
AT91F_MainMemoryToBufferTransfert(pDataFlash, DB_PAGE_2_BUF1_TRF, page);
|
||||
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
|
||||
/*Update the SRAM buffer */
|
||||
AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, AdrInPage, size);
|
||||
|
||||
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
|
||||
|
||||
/* Erase page if a 128 Mbits device */
|
||||
if (pDataFlash->pDevice->pages_number >= 16384) {
|
||||
AT91F_PageErase(pDataFlash, page);
|
||||
/* Rewrite the modified Sram Buffer in the main memory */
|
||||
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
|
||||
}
|
||||
|
||||
/* Rewrite the modified Sram Buffer in the main memory */
|
||||
return(AT91F_WriteBufferToMain(pDataFlash, DB_BUF1_PAGE_ERASE_PGM, (page*pDataFlash->pDevice->pages_size)));
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* Function Name : AT91F_DataFlashWrite */
|
||||
/* Object : */
|
||||
/* Input Parameters : <*src> = Source buffer */
|
||||
/* : <dest> = dataflash adress */
|
||||
/* : <size> = data buffer size */
|
||||
/*------------------------------------------------------------------------------*/
|
||||
AT91S_DataFlashStatus AT91F_DataFlashWrite(
|
||||
AT91PS_DataFlash pDataFlash,
|
||||
unsigned char *src,
|
||||
int dest,
|
||||
int size )
|
||||
{
|
||||
unsigned int length;
|
||||
unsigned int page;
|
||||
unsigned int status;
|
||||
|
||||
AT91F_SpiEnable(pDataFlash->pDevice->cs);
|
||||
|
||||
if ( (dest + size) > (pDataFlash->pDevice->pages_size * (pDataFlash->pDevice->pages_number)))
|
||||
return DATAFLASH_MEMORY_OVERFLOW;
|
||||
|
||||
/* If destination does not fit a page start address */
|
||||
if ((dest % ((unsigned int)(pDataFlash->pDevice->pages_size))) != 0 ) {
|
||||
length = pDataFlash->pDevice->pages_size - (dest % ((unsigned int)(pDataFlash->pDevice->pages_size)));
|
||||
|
||||
if (size < length)
|
||||
length = size;
|
||||
|
||||
if(!AT91F_PartialPageWrite(pDataFlash,src, dest, length))
|
||||
return DATAFLASH_ERROR;
|
||||
|
||||
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
|
||||
|
||||
/* Update size, source and destination pointers */
|
||||
size -= length;
|
||||
dest += length;
|
||||
src += length;
|
||||
}
|
||||
|
||||
while (( size - pDataFlash->pDevice->pages_size ) >= 0 ) {
|
||||
/* program dataflash page */
|
||||
page = (unsigned int)dest / (pDataFlash->pDevice->pages_size);
|
||||
|
||||
status = AT91F_DataFlashWriteBuffer(pDataFlash, DB_BUF1_WRITE, src, 0, pDataFlash->pDevice->pages_size);
|
||||
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
|
||||
|
||||
status = AT91F_PageErase(pDataFlash, page);
|
||||
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
|
||||
if (!status)
|
||||
return DATAFLASH_ERROR;
|
||||
|
||||
status = AT91F_WriteBufferToMain (pDataFlash, DB_BUF1_PAGE_PGM, dest);
|
||||
if(!status)
|
||||
return DATAFLASH_ERROR;
|
||||
|
||||
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
|
||||
|
||||
/* Update size, source and destination pointers */
|
||||
size -= pDataFlash->pDevice->pages_size ;
|
||||
dest += pDataFlash->pDevice->pages_size ;
|
||||
src += pDataFlash->pDevice->pages_size ;
|
||||
}
|
||||
|
||||
/* If still some bytes to read */
|
||||
if ( size > 0 ) {
|
||||
/* program dataflash page */
|
||||
if(!AT91F_PartialPageWrite(pDataFlash, src, dest, size) )
|
||||
return DATAFLASH_ERROR;
|
||||
|
||||
AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY);
|
||||
}
|
||||
return DATAFLASH_OK;
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* Function Name : AT91F_DataFlashRead */
|
||||
/* Object : Read a block in dataflash */
|
||||
/* Input Parameters : */
|
||||
/* Return value : */
|
||||
/*------------------------------------------------------------------------------*/
|
||||
int AT91F_DataFlashRead(
|
||||
AT91PS_DataFlash pDataFlash,
|
||||
unsigned long addr,
|
||||
unsigned long size,
|
||||
char *buffer)
|
||||
{
|
||||
unsigned long SizeToRead;
|
||||
|
||||
AT91F_SpiEnable(pDataFlash->pDevice->cs);
|
||||
|
||||
if(AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
|
||||
return -1;
|
||||
|
||||
while (size) {
|
||||
SizeToRead = (size < 0x8000)? size:0x8000;
|
||||
|
||||
if (AT91F_DataFlashWaitReady(pDataFlash->pDataFlashDesc, AT91C_TIMEOUT_WRDY) != DATAFLASH_OK)
|
||||
return -1;
|
||||
|
||||
if (AT91F_DataFlashContinuousRead (pDataFlash, addr, buffer, SizeToRead) != DATAFLASH_OK)
|
||||
return -1;
|
||||
|
||||
size -= SizeToRead;
|
||||
addr += SizeToRead;
|
||||
buffer += SizeToRead;
|
||||
}
|
||||
|
||||
return DATAFLASH_OK;
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
/* Function Name : AT91F_DataflashProbe */
|
||||
/* Object : */
|
||||
/* Input Parameters : */
|
||||
/* Return value : Dataflash status register */
|
||||
/*------------------------------------------------------------------------------*/
|
||||
int AT91F_DataflashProbe(int cs, AT91PS_DataflashDesc pDesc)
|
||||
{
|
||||
AT91F_SpiEnable(cs);
|
||||
AT91F_DataFlashGetStatus(pDesc);
|
||||
return((pDesc->command[1] == 0xFF)? 0: pDesc->command[1] & 0x3C);
|
||||
}
|
||||
|
||||
#endif
|
52
board/davinci/dv-evm/Makefile
Normal file
52
board/davinci/dv-evm/Makefile
Normal file
|
@ -0,0 +1,52 @@
|
|||
#
|
||||
# (C) Copyright 2000, 2001, 2002
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := dv_board.o
|
||||
SOBJS := board_init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak *~ .depend
|
||||
|
||||
#########################################################################
|
||||
# This is for $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
29
board/davinci/dv-evm/board_init.S
Normal file
29
board/davinci/dv-evm/board_init.S
Normal file
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
*
|
||||
* Board-specific low level initialization code. Called at the very end
|
||||
* of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
|
||||
* initialization required.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
.globl dv_board_init
|
||||
dv_board_init:
|
||||
|
||||
mov pc, lr
|
39
board/davinci/dv-evm/config.mk
Normal file
39
board/davinci/dv-evm/config.mk
Normal file
|
@ -0,0 +1,39 @@
|
|||
#
|
||||
# (C) Copyright 2002
|
||||
# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
|
||||
#
|
||||
# (C) Copyright 2003
|
||||
# Texas Instruments, <www.ti.com>
|
||||
# Swaminathan <swami.iyer@ti.com>
|
||||
#
|
||||
# Davinci EVM board (ARM925EJS) cpu
|
||||
# see http://www.ti.com/ for more information on Texas Instruments
|
||||
#
|
||||
# Davinci EVM has 1 bank of 256 MB DDR RAM
|
||||
# Physical Address:
|
||||
# 8000'0000 to 9000'0000
|
||||
#
|
||||
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
#
|
||||
# Visioneering Corp. Sonata board (ARM926EJS) cpu
|
||||
#
|
||||
# Sonata board has 1 bank of 128 MB DDR RAM
|
||||
# Physical Address:
|
||||
# 8000'0000 to 8800'0000
|
||||
#
|
||||
# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
|
||||
#
|
||||
# Schmoogie board has 1 bank of 128 MB DDR RAM
|
||||
# Physical Address:
|
||||
# 8000'0000 to 8800'0000
|
||||
#
|
||||
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
|
||||
# (mem base + reserved)
|
||||
#
|
||||
# we load ourself to 8108 '0000
|
||||
#
|
||||
#
|
||||
|
||||
#Provide at least 16MB spacing between us and the Linux Kernel image
|
||||
TEXT_BASE = 0x81080000
|
211
board/davinci/dv-evm/dv_board.c
Normal file
211
board/davinci/dv-evm/dv_board.c
Normal file
|
@ -0,0 +1,211 @@
|
|||
/*
|
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
*
|
||||
* Parts are shamelessly stolen from various TI sources, original copyright
|
||||
* follows:
|
||||
* -----------------------------------------------------------------
|
||||
*
|
||||
* Copyright (C) 2004 Texas Instruments.
|
||||
*
|
||||
* ----------------------------------------------------------------------------
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
* ----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/emac_defs.h>
|
||||
|
||||
#define MACH_TYPE_DAVINCI_EVM 901
|
||||
|
||||
extern void i2c_init(int speed, int slaveaddr);
|
||||
extern void timer_init(void);
|
||||
extern int eth_hw_init(void);
|
||||
extern phy_t phy;
|
||||
|
||||
|
||||
/* Works on Always On power domain only (no PD argument) */
|
||||
void lpsc_on(unsigned int id)
|
||||
{
|
||||
dv_reg_p mdstat, mdctl;
|
||||
|
||||
if (id >= DAVINCI_LPSC_GEM)
|
||||
return; /* Don't work on DSP Power Domain */
|
||||
|
||||
mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
|
||||
mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
|
||||
|
||||
while (REG(PSC_PTSTAT) & 0x01) {;}
|
||||
|
||||
if ((*mdstat & 0x1f) == 0x03)
|
||||
return; /* Already on and enabled */
|
||||
|
||||
*mdctl |= 0x03;
|
||||
|
||||
/* Special treatment for some modules as for sprue14 p.7.4.2 */
|
||||
if ( (id == DAVINCI_LPSC_VPSSSLV) ||
|
||||
(id == DAVINCI_LPSC_EMAC) ||
|
||||
(id == DAVINCI_LPSC_EMAC_WRAPPER) ||
|
||||
(id == DAVINCI_LPSC_MDIO) ||
|
||||
(id == DAVINCI_LPSC_USB) ||
|
||||
(id == DAVINCI_LPSC_ATA) ||
|
||||
(id == DAVINCI_LPSC_VLYNQ) ||
|
||||
(id == DAVINCI_LPSC_UHPI) ||
|
||||
(id == DAVINCI_LPSC_DDR_EMIF) ||
|
||||
(id == DAVINCI_LPSC_AEMIF) ||
|
||||
(id == DAVINCI_LPSC_MMC_SD) ||
|
||||
(id == DAVINCI_LPSC_MEMSTICK) ||
|
||||
(id == DAVINCI_LPSC_McBSP) ||
|
||||
(id == DAVINCI_LPSC_GPIO)
|
||||
)
|
||||
*mdctl |= 0x200;
|
||||
|
||||
REG(PSC_PTCMD) = 0x01;
|
||||
|
||||
while (REG(PSC_PTSTAT) & 0x03) {;}
|
||||
while ((*mdstat & 0x1f) != 0x03) {;} /* Probably an overkill... */
|
||||
}
|
||||
|
||||
void dsp_on(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (REG(PSC_PDSTAT1) & 0x1f)
|
||||
return; /* Already on */
|
||||
|
||||
REG(PSC_GBLCTL) |= 0x01;
|
||||
REG(PSC_PDCTL1) |= 0x01;
|
||||
REG(PSC_PDCTL1) &= ~0x100;
|
||||
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
|
||||
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
|
||||
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
|
||||
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
|
||||
REG(PSC_PTCMD) = 0x02;
|
||||
|
||||
for (i = 0; i < 100; i++) {
|
||||
if (REG(PSC_EPCPR) & 0x02)
|
||||
break;
|
||||
}
|
||||
|
||||
REG(PSC_CHP_SHRTSW) = 0x01;
|
||||
REG(PSC_PDCTL1) |= 0x100;
|
||||
REG(PSC_EPCCR) = 0x02;
|
||||
|
||||
for (i = 0; i < 100; i++) {
|
||||
if (!(REG(PSC_PTSTAT) & 0x02))
|
||||
break;
|
||||
}
|
||||
|
||||
REG(PSC_GBLCTL) &= ~0x1f;
|
||||
}
|
||||
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* arch number of the board */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM;
|
||||
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
|
||||
|
||||
/* Workaround for TMS320DM6446 errata 1.3.22 */
|
||||
REG(PSC_SILVER_BULLET) = 0;
|
||||
|
||||
/* Power on required peripherals */
|
||||
lpsc_on(DAVINCI_LPSC_EMAC);
|
||||
lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
|
||||
lpsc_on(DAVINCI_LPSC_MDIO);
|
||||
lpsc_on(DAVINCI_LPSC_I2C);
|
||||
lpsc_on(DAVINCI_LPSC_UART0);
|
||||
lpsc_on(DAVINCI_LPSC_TIMER1);
|
||||
lpsc_on(DAVINCI_LPSC_GPIO);
|
||||
|
||||
/* Powerup the DSP */
|
||||
dsp_on();
|
||||
|
||||
/* Bringup UART0 out of reset */
|
||||
REG(UART0_PWREMU_MGMT) = 0x0000e003;
|
||||
|
||||
/* Enable GIO3.3V cells used for EMAC */
|
||||
REG(VDD3P3V_PWDN) = 0;
|
||||
|
||||
/* Enable UART0 MUX lines */
|
||||
REG(PINMUX1) |= 1;
|
||||
|
||||
/* Enable EMAC and AEMIF pins */
|
||||
REG(PINMUX0) = 0x80000c1f;
|
||||
|
||||
/* Enable I2C pin Mux */
|
||||
REG(PINMUX1) |= (1 << 7);
|
||||
|
||||
/* Set the Bus Priority Register to appropriate value */
|
||||
REG(VBPR) = 0x20;
|
||||
|
||||
timer_init();
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
int misc_init_r (void)
|
||||
{
|
||||
u_int8_t tmp[20], buf[10];
|
||||
int i = 0;
|
||||
int clk = 0;
|
||||
|
||||
clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1);
|
||||
|
||||
printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2);
|
||||
printf ("DDR Clock : %dMHz\n", (clk / 2));
|
||||
|
||||
/* Set Ethernet MAC address from EEPROM */
|
||||
if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x7f00, CFG_I2C_EEPROM_ADDR_LEN, buf, 6)) {
|
||||
printf("\nEEPROM @ 0x%02x read FAILED!!!\n", CFG_I2C_EEPROM_ADDR);
|
||||
} else {
|
||||
tmp[0] = 0xff;
|
||||
for (i = 0; i < 6; i++)
|
||||
tmp[0] &= buf[i];
|
||||
|
||||
if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) {
|
||||
sprintf((char *)&tmp[0], "%02x:%02x:%02x:%02x:%02x:%02x",
|
||||
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
|
||||
setenv("ethaddr", (char *)&tmp[0]);
|
||||
}
|
||||
}
|
||||
|
||||
if (!eth_hw_init()) {
|
||||
printf("ethernet init failed!\n");
|
||||
} else {
|
||||
printf("ETH PHY : %s\n", phy.name);
|
||||
}
|
||||
|
||||
i2c_read (0x39, 0x00, 1, (u_int8_t *)&i, 1);
|
||||
|
||||
setenv ("videostd", ((i & 0x80) ? "pal" : "ntsc"));
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
||||
|
||||
return(0);
|
||||
}
|
52
board/davinci/dv-evm/u-boot.lds
Normal file
52
board/davinci/dv-evm/u-boot.lds
Normal file
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
cpu/arm926ejs/start.o (.text)
|
||||
*(.text)
|
||||
}
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
. = ALIGN(4);
|
||||
.got : { *(.got) }
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
.bss : { *(.bss) }
|
||||
_end = .;
|
||||
}
|
52
board/davinci/schmoogie/Makefile
Normal file
52
board/davinci/schmoogie/Makefile
Normal file
|
@ -0,0 +1,52 @@
|
|||
#
|
||||
# (C) Copyright 2000, 2001, 2002
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := dv_board.o
|
||||
SOBJS := board_init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak *~ .depend
|
||||
|
||||
#########################################################################
|
||||
# This is for $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
29
board/davinci/schmoogie/board_init.S
Normal file
29
board/davinci/schmoogie/board_init.S
Normal file
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
*
|
||||
* Board-specific low level initialization code. Called at the very end
|
||||
* of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
|
||||
* initialization required.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
.globl dv_board_init
|
||||
dv_board_init:
|
||||
|
||||
mov pc, lr
|
39
board/davinci/schmoogie/config.mk
Normal file
39
board/davinci/schmoogie/config.mk
Normal file
|
@ -0,0 +1,39 @@
|
|||
#
|
||||
# (C) Copyright 2002
|
||||
# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
|
||||
#
|
||||
# (C) Copyright 2003
|
||||
# Texas Instruments, <www.ti.com>
|
||||
# Swaminathan <swami.iyer@ti.com>
|
||||
#
|
||||
# Davinci EVM board (ARM925EJS) cpu
|
||||
# see http://www.ti.com/ for more information on Texas Instruments
|
||||
#
|
||||
# Davinci EVM has 1 bank of 256 MB DDR RAM
|
||||
# Physical Address:
|
||||
# 8000'0000 to 9000'0000
|
||||
#
|
||||
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
#
|
||||
# Visioneering Corp. Sonata board (ARM926EJS) cpu
|
||||
#
|
||||
# Sonata board has 1 bank of 128 MB DDR RAM
|
||||
# Physical Address:
|
||||
# 8000'0000 to 8800'0000
|
||||
#
|
||||
# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
|
||||
#
|
||||
# Schmoogie board has 1 bank of 128 MB DDR RAM
|
||||
# Physical Address:
|
||||
# 8000'0000 to 8800'0000
|
||||
#
|
||||
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
|
||||
# (mem base + reserved)
|
||||
#
|
||||
# we load ourself to 8108 '0000
|
||||
#
|
||||
#
|
||||
|
||||
#Provide at least 16MB spacing between us and the Linux Kernel image
|
||||
TEXT_BASE = 0x81080000
|
253
board/davinci/schmoogie/dv_board.c
Normal file
253
board/davinci/schmoogie/dv_board.c
Normal file
|
@ -0,0 +1,253 @@
|
|||
/*
|
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
*
|
||||
* Parts are shamelessly stolen from various TI sources, original copyright
|
||||
* follows:
|
||||
* -----------------------------------------------------------------
|
||||
*
|
||||
* Copyright (C) 2004 Texas Instruments.
|
||||
*
|
||||
* ----------------------------------------------------------------------------
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
* ----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/emac_defs.h>
|
||||
|
||||
#define MACH_TYPE_SCHMOOGIE 1255
|
||||
|
||||
extern void i2c_init(int speed, int slaveaddr);
|
||||
extern void timer_init(void);
|
||||
extern int eth_hw_init(void);
|
||||
extern phy_t phy;
|
||||
|
||||
|
||||
/* Works on Always On power domain only (no PD argument) */
|
||||
void lpsc_on(unsigned int id)
|
||||
{
|
||||
dv_reg_p mdstat, mdctl;
|
||||
|
||||
if (id >= DAVINCI_LPSC_GEM)
|
||||
return; /* Don't work on DSP Power Domain */
|
||||
|
||||
mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
|
||||
mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
|
||||
|
||||
while (REG(PSC_PTSTAT) & 0x01) {;}
|
||||
|
||||
if ((*mdstat & 0x1f) == 0x03)
|
||||
return; /* Already on and enabled */
|
||||
|
||||
*mdctl |= 0x03;
|
||||
|
||||
/* Special treatment for some modules as for sprue14 p.7.4.2 */
|
||||
if ( (id == DAVINCI_LPSC_VPSSSLV) ||
|
||||
(id == DAVINCI_LPSC_EMAC) ||
|
||||
(id == DAVINCI_LPSC_EMAC_WRAPPER) ||
|
||||
(id == DAVINCI_LPSC_MDIO) ||
|
||||
(id == DAVINCI_LPSC_USB) ||
|
||||
(id == DAVINCI_LPSC_ATA) ||
|
||||
(id == DAVINCI_LPSC_VLYNQ) ||
|
||||
(id == DAVINCI_LPSC_UHPI) ||
|
||||
(id == DAVINCI_LPSC_DDR_EMIF) ||
|
||||
(id == DAVINCI_LPSC_AEMIF) ||
|
||||
(id == DAVINCI_LPSC_MMC_SD) ||
|
||||
(id == DAVINCI_LPSC_MEMSTICK) ||
|
||||
(id == DAVINCI_LPSC_McBSP) ||
|
||||
(id == DAVINCI_LPSC_GPIO)
|
||||
)
|
||||
*mdctl |= 0x200;
|
||||
|
||||
REG(PSC_PTCMD) = 0x01;
|
||||
|
||||
while (REG(PSC_PTSTAT) & 0x03) {;}
|
||||
while ((*mdstat & 0x1f) != 0x03) {;} /* Probably an overkill... */
|
||||
}
|
||||
|
||||
void dsp_on(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (REG(PSC_PDSTAT1) & 0x1f)
|
||||
return; /* Already on */
|
||||
|
||||
REG(PSC_GBLCTL) |= 0x01;
|
||||
REG(PSC_PDCTL1) |= 0x01;
|
||||
REG(PSC_PDCTL1) &= ~0x100;
|
||||
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
|
||||
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
|
||||
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
|
||||
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
|
||||
REG(PSC_PTCMD) = 0x02;
|
||||
|
||||
for (i = 0; i < 100; i++) {
|
||||
if (REG(PSC_EPCPR) & 0x02)
|
||||
break;
|
||||
}
|
||||
|
||||
REG(PSC_CHP_SHRTSW) = 0x01;
|
||||
REG(PSC_PDCTL1) |= 0x100;
|
||||
REG(PSC_EPCCR) = 0x02;
|
||||
|
||||
for (i = 0; i < 100; i++) {
|
||||
if (!(REG(PSC_PTSTAT) & 0x02))
|
||||
break;
|
||||
}
|
||||
|
||||
REG(PSC_GBLCTL) &= ~0x1f;
|
||||
}
|
||||
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* arch number of the board */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_SCHMOOGIE;
|
||||
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
|
||||
|
||||
/* Workaround for TMS320DM6446 errata 1.3.22 */
|
||||
REG(PSC_SILVER_BULLET) = 0;
|
||||
|
||||
/* Power on required peripherals */
|
||||
lpsc_on(DAVINCI_LPSC_EMAC);
|
||||
lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
|
||||
lpsc_on(DAVINCI_LPSC_MDIO);
|
||||
lpsc_on(DAVINCI_LPSC_I2C);
|
||||
lpsc_on(DAVINCI_LPSC_UART0);
|
||||
lpsc_on(DAVINCI_LPSC_TIMER1);
|
||||
lpsc_on(DAVINCI_LPSC_GPIO);
|
||||
|
||||
/* Powerup the DSP */
|
||||
dsp_on();
|
||||
|
||||
/* Bringup UART0 out of reset */
|
||||
REG(UART0_PWREMU_MGMT) = 0x0000e003;
|
||||
|
||||
/* Enable GIO3.3V cells used for EMAC */
|
||||
REG(VDD3P3V_PWDN) = 0;
|
||||
|
||||
/* Enable UART0 MUX lines */
|
||||
REG(PINMUX1) |= 1;
|
||||
|
||||
/* Enable EMAC and AEMIF pins */
|
||||
REG(PINMUX0) = 0x80000c1f;
|
||||
|
||||
/* Enable I2C pin Mux */
|
||||
REG(PINMUX1) |= (1 << 7);
|
||||
|
||||
/* Set the Bus Priority Register to appropriate value */
|
||||
REG(VBPR) = 0x20;
|
||||
|
||||
timer_init();
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
int misc_init_r (void)
|
||||
{
|
||||
u_int8_t tmp[20], buf[10];
|
||||
int i = 0;
|
||||
int clk = 0;
|
||||
|
||||
/* Set serial number from UID chip */
|
||||
u_int8_t crc_tbl[256] = {
|
||||
0x00, 0x5e, 0xbc, 0xe2, 0x61, 0x3f, 0xdd, 0x83,
|
||||
0xc2, 0x9c, 0x7e, 0x20, 0xa3, 0xfd, 0x1f, 0x41,
|
||||
0x9d, 0xc3, 0x21, 0x7f, 0xfc, 0xa2, 0x40, 0x1e,
|
||||
0x5f, 0x01, 0xe3, 0xbd, 0x3e, 0x60, 0x82, 0xdc,
|
||||
0x23, 0x7d, 0x9f, 0xc1, 0x42, 0x1c, 0xfe, 0xa0,
|
||||
0xe1, 0xbf, 0x5d, 0x03, 0x80, 0xde, 0x3c, 0x62,
|
||||
0xbe, 0xe0, 0x02, 0x5c, 0xdf, 0x81, 0x63, 0x3d,
|
||||
0x7c, 0x22, 0xc0, 0x9e, 0x1d, 0x43, 0xa1, 0xff,
|
||||
0x46, 0x18, 0xfa, 0xa4, 0x27, 0x79, 0x9b, 0xc5,
|
||||
0x84, 0xda, 0x38, 0x66, 0xe5, 0xbb, 0x59, 0x07,
|
||||
0xdb, 0x85, 0x67, 0x39, 0xba, 0xe4, 0x06, 0x58,
|
||||
0x19, 0x47, 0xa5, 0xfb, 0x78, 0x26, 0xc4, 0x9a,
|
||||
0x65, 0x3b, 0xd9, 0x87, 0x04, 0x5a, 0xb8, 0xe6,
|
||||
0xa7, 0xf9, 0x1b, 0x45, 0xc6, 0x98, 0x7a, 0x24,
|
||||
0xf8, 0xa6, 0x44, 0x1a, 0x99, 0xc7, 0x25, 0x7b,
|
||||
0x3a, 0x64, 0x86, 0xd8, 0x5b, 0x05, 0xe7, 0xb9,
|
||||
0x8c, 0xd2, 0x30, 0x6e, 0xed, 0xb3, 0x51, 0x0f,
|
||||
0x4e, 0x10, 0xf2, 0xac, 0x2f, 0x71, 0x93, 0xcd,
|
||||
0x11, 0x4f, 0xad, 0xf3, 0x70, 0x2e, 0xcc, 0x92,
|
||||
0xd3, 0x8d, 0x6f, 0x31, 0xb2, 0xec, 0x0e, 0x50,
|
||||
0xaf, 0xf1, 0x13, 0x4d, 0xce, 0x90, 0x72, 0x2c,
|
||||
0x6d, 0x33, 0xd1, 0x8f, 0x0c, 0x52, 0xb0, 0xee,
|
||||
0x32, 0x6c, 0x8e, 0xd0, 0x53, 0x0d, 0xef, 0xb1,
|
||||
0xf0, 0xae, 0x4c, 0x12, 0x91, 0xcf, 0x2d, 0x73,
|
||||
0xca, 0x94, 0x76, 0x28, 0xab, 0xf5, 0x17, 0x49,
|
||||
0x08, 0x56, 0xb4, 0xea, 0x69, 0x37, 0xd5, 0x8b,
|
||||
0x57, 0x09, 0xeb, 0xb5, 0x36, 0x68, 0x8a, 0xd4,
|
||||
0x95, 0xcb, 0x29, 0x77, 0xf4, 0xaa, 0x48, 0x16,
|
||||
0xe9, 0xb7, 0x55, 0x0b, 0x88, 0xd6, 0x34, 0x6a,
|
||||
0x2b, 0x75, 0x97, 0xc9, 0x4a, 0x14, 0xf6, 0xa8,
|
||||
0x74, 0x2a, 0xc8, 0x96, 0x15, 0x4b, 0xa9, 0xf7,
|
||||
0xb6, 0xe8, 0x0a, 0x54, 0xd7, 0x89, 0x6b, 0x35
|
||||
};
|
||||
|
||||
clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1);
|
||||
|
||||
printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2);
|
||||
printf ("DDR Clock : %dMHz\n", (clk / 2));
|
||||
|
||||
/* Set serial number from UID chip */
|
||||
if (i2c_read(CFG_UID_ADDR, 0, 1, buf, 8)) {
|
||||
printf("\nUID @ 0x%02x read FAILED!!!\n", CFG_UID_ADDR);
|
||||
forceenv("serial#", "FAILED");
|
||||
} else {
|
||||
if (buf[0] != 0x70) { /* Device Family Code */
|
||||
printf("\nUID @ 0x%02x read FAILED!!!\n", CFG_UID_ADDR);
|
||||
forceenv("serial#", "FAILED");
|
||||
}
|
||||
}
|
||||
/* Now check CRC */
|
||||
tmp[0] = 0;
|
||||
for (i = 0; i < 8; i++)
|
||||
tmp[0] = crc_tbl[tmp[0] ^ buf[i]];
|
||||
|
||||
if (tmp[0] != 0) {
|
||||
printf("\nUID @ 0x%02x - BAD CRC!!!\n", CFG_UID_ADDR);
|
||||
forceenv("serial#", "FAILED");
|
||||
} else {
|
||||
/* CRC OK, set "serial" env variable */
|
||||
sprintf((char *)&tmp[0], "%02x%02x%02x%02x%02x%02x",
|
||||
buf[6], buf[5], buf[4], buf[3], buf[2], buf[1]);
|
||||
forceenv("serial#", (char *)&tmp[0]);
|
||||
}
|
||||
|
||||
if (!eth_hw_init()) {
|
||||
printf("ethernet init failed!\n");
|
||||
} else {
|
||||
printf("ETH PHY : %s\n", phy.name);
|
||||
}
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
||||
|
||||
return(0);
|
||||
}
|
52
board/davinci/schmoogie/u-boot.lds
Normal file
52
board/davinci/schmoogie/u-boot.lds
Normal file
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
cpu/arm926ejs/start.o (.text)
|
||||
*(.text)
|
||||
}
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
. = ALIGN(4);
|
||||
.got : { *(.got) }
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
.bss : { *(.bss) }
|
||||
_end = .;
|
||||
}
|
52
board/davinci/sonata/Makefile
Normal file
52
board/davinci/sonata/Makefile
Normal file
|
@ -0,0 +1,52 @@
|
|||
#
|
||||
# (C) Copyright 2000, 2001, 2002
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := dv_board.o
|
||||
SOBJS := board_init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak *~ .depend
|
||||
|
||||
#########################################################################
|
||||
# This is for $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
100
board/davinci/sonata/board_init.S
Normal file
100
board/davinci/sonata/board_init.S
Normal file
|
@ -0,0 +1,100 @@
|
|||
/*
|
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
*
|
||||
* Board-specific low level initialization code. Called at the very end
|
||||
* of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no
|
||||
* initialization required.
|
||||
*
|
||||
* For _OLDER_ Sonata boards sets up GPIO4 to control NAND WP line. Newer
|
||||
* Sonata boards, AFAIK, don't use this so it's just return by default. Ask
|
||||
* Visioneering if they reinvented the wheel once again to make sure :)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
.globl dv_board_init
|
||||
dv_board_init:
|
||||
#ifdef SONATA_BOARD_GPIOWP
|
||||
/* Set PINMUX0 to enable GPIO4 */
|
||||
ldr r0, _PINMUX0
|
||||
ldr r1, GPIO4_EN_MASK
|
||||
ldr r2, [r0]
|
||||
and r2, r2, r1
|
||||
str r2, [r0]
|
||||
|
||||
/* Enable GPIO LPSC module */
|
||||
ldr r0, PTSTAT
|
||||
|
||||
gpio_ptstat_loop1:
|
||||
ldr r2, [r0]
|
||||
tst r2, $0x00000001
|
||||
bne gpio_ptstat_loop1
|
||||
|
||||
ldr r1, MDCTL_GPIO
|
||||
ldr r2, [r1]
|
||||
and r2, r2, $0xfffffff8
|
||||
orr r2, r2, $0x00000003
|
||||
str r2, [r1]
|
||||
|
||||
orr r2, r2, $0x00000200
|
||||
str r2, [r1]
|
||||
|
||||
ldr r1, PTCMD
|
||||
mov r2, $0x00000001
|
||||
str r2, [r1]
|
||||
|
||||
gpio_ptstat_loop2:
|
||||
ldr r2, [r0]
|
||||
tst r2, $0x00000001
|
||||
bne gpio_ptstat_loop2
|
||||
|
||||
ldr r0, MDSTAT_GPIO
|
||||
gpio_mdstat_loop:
|
||||
ldr r2, [r0]
|
||||
and r2, r2, $0x0000001f
|
||||
teq r2, $0x00000003
|
||||
bne gpio_mdstat_loop
|
||||
|
||||
/* GPIO4 -> output */
|
||||
ldr r0, GPIO_DIR01
|
||||
mov r1, $0x10
|
||||
ldr r2, [r0]
|
||||
bic r2, r2, r0
|
||||
str r2, [r0]
|
||||
|
||||
/* Set it to 0 (Write Protect) */
|
||||
ldr r0, GPIO_CLR_DATA01
|
||||
str r1, [r0]
|
||||
#endif
|
||||
|
||||
mov pc, lr
|
||||
|
||||
#ifdef SONATA_BOARD_GPIOWP
|
||||
.ltorg
|
||||
|
||||
GPIO4_EN_MASK:
|
||||
.word 0xf77fffff
|
||||
MDCTL_GPIO:
|
||||
.word 0x01c41a68
|
||||
MDSTAT_GPIO:
|
||||
.word 0x01c41868
|
||||
GPIO_DIR01:
|
||||
.word 0x01c67010
|
||||
GPIO_CLR_DATA01:
|
||||
.word 0x01c6701c
|
||||
#endif
|
39
board/davinci/sonata/config.mk
Normal file
39
board/davinci/sonata/config.mk
Normal file
|
@ -0,0 +1,39 @@
|
|||
#
|
||||
# (C) Copyright 2002
|
||||
# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
|
||||
#
|
||||
# (C) Copyright 2003
|
||||
# Texas Instruments, <www.ti.com>
|
||||
# Swaminathan <swami.iyer@ti.com>
|
||||
#
|
||||
# Davinci EVM board (ARM925EJS) cpu
|
||||
# see http://www.ti.com/ for more information on Texas Instruments
|
||||
#
|
||||
# Davinci EVM has 1 bank of 256 MB DDR RAM
|
||||
# Physical Address:
|
||||
# 8000'0000 to 9000'0000
|
||||
#
|
||||
# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
#
|
||||
# Visioneering Corp. Sonata board (ARM926EJS) cpu
|
||||
#
|
||||
# Sonata board has 1 bank of 128 MB DDR RAM
|
||||
# Physical Address:
|
||||
# 8000'0000 to 8800'0000
|
||||
#
|
||||
# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
|
||||
#
|
||||
# Schmoogie board has 1 bank of 128 MB DDR RAM
|
||||
# Physical Address:
|
||||
# 8000'0000 to 8800'0000
|
||||
#
|
||||
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
|
||||
# (mem base + reserved)
|
||||
#
|
||||
# we load ourself to 8108 '0000
|
||||
#
|
||||
#
|
||||
|
||||
#Provide at least 16MB spacing between us and the Linux Kernel image
|
||||
TEXT_BASE = 0x81080000
|
208
board/davinci/sonata/dv_board.c
Normal file
208
board/davinci/sonata/dv_board.c
Normal file
|
@ -0,0 +1,208 @@
|
|||
/*
|
||||
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
||||
*
|
||||
* Parts are shamelessly stolen from various TI sources, original copyright
|
||||
* follows:
|
||||
* -----------------------------------------------------------------
|
||||
*
|
||||
* Copyright (C) 2004 Texas Instruments.
|
||||
*
|
||||
* ----------------------------------------------------------------------------
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
* ----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/emac_defs.h>
|
||||
|
||||
#define MACH_TYPE_SONATA 1254
|
||||
|
||||
extern void i2c_init(int speed, int slaveaddr);
|
||||
extern void timer_init(void);
|
||||
extern int eth_hw_init(void);
|
||||
extern phy_t phy;
|
||||
|
||||
|
||||
/* Works on Always On power domain only (no PD argument) */
|
||||
void lpsc_on(unsigned int id)
|
||||
{
|
||||
dv_reg_p mdstat, mdctl;
|
||||
|
||||
if (id >= DAVINCI_LPSC_GEM)
|
||||
return; /* Don't work on DSP Power Domain */
|
||||
|
||||
mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
|
||||
mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
|
||||
|
||||
while (REG(PSC_PTSTAT) & 0x01) {;}
|
||||
|
||||
if ((*mdstat & 0x1f) == 0x03)
|
||||
return; /* Already on and enabled */
|
||||
|
||||
*mdctl |= 0x03;
|
||||
|
||||
/* Special treatment for some modules as for sprue14 p.7.4.2 */
|
||||
if ( (id == DAVINCI_LPSC_VPSSSLV) ||
|
||||
(id == DAVINCI_LPSC_EMAC) ||
|
||||
(id == DAVINCI_LPSC_EMAC_WRAPPER) ||
|
||||
(id == DAVINCI_LPSC_MDIO) ||
|
||||
(id == DAVINCI_LPSC_USB) ||
|
||||
(id == DAVINCI_LPSC_ATA) ||
|
||||
(id == DAVINCI_LPSC_VLYNQ) ||
|
||||
(id == DAVINCI_LPSC_UHPI) ||
|
||||
(id == DAVINCI_LPSC_DDR_EMIF) ||
|
||||
(id == DAVINCI_LPSC_AEMIF) ||
|
||||
(id == DAVINCI_LPSC_MMC_SD) ||
|
||||
(id == DAVINCI_LPSC_MEMSTICK) ||
|
||||
(id == DAVINCI_LPSC_McBSP) ||
|
||||
(id == DAVINCI_LPSC_GPIO)
|
||||
)
|
||||
*mdctl |= 0x200;
|
||||
|
||||
REG(PSC_PTCMD) = 0x01;
|
||||
|
||||
while (REG(PSC_PTSTAT) & 0x03) {;}
|
||||
while ((*mdstat & 0x1f) != 0x03) {;} /* Probably an overkill... */
|
||||
}
|
||||
|
||||
void dsp_on(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (REG(PSC_PDSTAT1) & 0x1f)
|
||||
return; /* Already on */
|
||||
|
||||
REG(PSC_GBLCTL) |= 0x01;
|
||||
REG(PSC_PDCTL1) |= 0x01;
|
||||
REG(PSC_PDCTL1) &= ~0x100;
|
||||
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
|
||||
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
|
||||
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
|
||||
REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
|
||||
REG(PSC_PTCMD) = 0x02;
|
||||
|
||||
for (i = 0; i < 100; i++) {
|
||||
if (REG(PSC_EPCPR) & 0x02)
|
||||
break;
|
||||
}
|
||||
|
||||
REG(PSC_CHP_SHRTSW) = 0x01;
|
||||
REG(PSC_PDCTL1) |= 0x100;
|
||||
REG(PSC_EPCCR) = 0x02;
|
||||
|
||||
for (i = 0; i < 100; i++) {
|
||||
if (!(REG(PSC_PTSTAT) & 0x02))
|
||||
break;
|
||||
}
|
||||
|
||||
REG(PSC_GBLCTL) &= ~0x1f;
|
||||
}
|
||||
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* arch number of the board */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_SONATA;
|
||||
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
|
||||
|
||||
/* Workaround for TMS320DM6446 errata 1.3.22 */
|
||||
REG(PSC_SILVER_BULLET) = 0;
|
||||
|
||||
/* Power on required peripherals */
|
||||
lpsc_on(DAVINCI_LPSC_EMAC);
|
||||
lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
|
||||
lpsc_on(DAVINCI_LPSC_MDIO);
|
||||
lpsc_on(DAVINCI_LPSC_I2C);
|
||||
lpsc_on(DAVINCI_LPSC_UART0);
|
||||
lpsc_on(DAVINCI_LPSC_TIMER1);
|
||||
lpsc_on(DAVINCI_LPSC_GPIO);
|
||||
|
||||
/* Powerup the DSP */
|
||||
dsp_on();
|
||||
|
||||
/* Bringup UART0 out of reset */
|
||||
REG(UART0_PWREMU_MGMT) = 0x0000e003;
|
||||
|
||||
/* Enable GIO3.3V cells used for EMAC */
|
||||
REG(VDD3P3V_PWDN) = 0;
|
||||
|
||||
/* Enable UART0 MUX lines */
|
||||
REG(PINMUX1) |= 1;
|
||||
|
||||
/* Enable EMAC and AEMIF pins */
|
||||
REG(PINMUX0) = 0x80000c1f;
|
||||
|
||||
/* Enable I2C pin Mux */
|
||||
REG(PINMUX1) |= (1 << 7);
|
||||
|
||||
/* Set the Bus Priority Register to appropriate value */
|
||||
REG(VBPR) = 0x20;
|
||||
|
||||
timer_init();
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
int misc_init_r (void)
|
||||
{
|
||||
u_int8_t tmp[20], buf[10];
|
||||
int i = 0;
|
||||
int clk = 0;
|
||||
|
||||
|
||||
clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1);
|
||||
|
||||
printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2);
|
||||
printf ("DDR Clock : %dMHz\n", (clk / 2));
|
||||
|
||||
/* Set Ethernet MAC address from EEPROM */
|
||||
if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x7f00, CFG_I2C_EEPROM_ADDR_LEN, buf, 6)) {
|
||||
printf("\nEEPROM @ 0x%02x read FAILED!!!\n", CFG_I2C_EEPROM_ADDR);
|
||||
} else {
|
||||
tmp[0] = 0xff;
|
||||
for (i = 0; i < 6; i++)
|
||||
tmp[0] &= buf[i];
|
||||
|
||||
if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) {
|
||||
sprintf((char *)&tmp[0], "%02x:%02x:%02x:%02x:%02x:%02x",
|
||||
buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
|
||||
setenv("ethaddr", (char *)&tmp[0]);
|
||||
}
|
||||
}
|
||||
|
||||
if (!eth_hw_init()) {
|
||||
printf("ethernet init failed!\n");
|
||||
} else {
|
||||
printf("ETH PHY : %s\n", phy.name);
|
||||
}
|
||||
|
||||
return(0);
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
||||
|
||||
return(0);
|
||||
}
|
52
board/davinci/sonata/u-boot.lds
Normal file
52
board/davinci/sonata/u-boot.lds
Normal file
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
cpu/arm926ejs/start.o (.text)
|
||||
*(.text)
|
||||
}
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
. = ALIGN(4);
|
||||
.got : { *(.got) }
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
.bss : { *(.bss) }
|
||||
_end = .;
|
||||
}
|
|
@ -1,10 +1,6 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
* (C) Copyright 2006
|
||||
* DENX Software Engineering
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
@ -98,7 +94,6 @@ int board_late_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Magic Key Handling, mainly copied from board/lwmon/lwmon.c
|
||||
*/
|
||||
|
@ -324,6 +319,12 @@ static void init_DA9030()
|
|||
return;
|
||||
}
|
||||
|
||||
val = 0x80;
|
||||
if(i2c_write(addr, IRQ_MASK_B, 1, &val, 1)) {
|
||||
printf("Error accessing DA9030 via i2c.\n");
|
||||
return;
|
||||
}
|
||||
|
||||
i2c_reg_write(addr, REG_CONTROL_1_97, 0xfd); /* disable LDO1, enable LDO6 */
|
||||
i2c_reg_write(addr, LDO2_3, 0xd1); /* LDO2 =1,9V, LDO3=3,1V */
|
||||
i2c_reg_write(addr, LDO4_5, 0xcc); /* LDO2 =1,9V, LDO3=3,1V */
|
||||
|
|
File diff suppressed because it is too large
Load diff
50
board/freescale/mpc8323erdb/Makefile
Normal file
50
board/freescale/mpc8323erdb/Makefile
Normal file
|
@ -0,0 +1,50 @@
|
|||
#
|
||||
# (C) Copyright 2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := $(BOARD).o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
28
board/freescale/mpc8323erdb/config.mk
Normal file
28
board/freescale/mpc8323erdb/config.mk
Normal file
|
@ -0,0 +1,28 @@
|
|||
#
|
||||
# (C) Copyright 2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# MPC8323ERDB
|
||||
#
|
||||
|
||||
TEXT_BASE = 0xFE000000
|
217
board/freescale/mpc8323erdb/mpc8323erdb.c
Normal file
217
board/freescale/mpc8323erdb/mpc8323erdb.c
Normal file
|
@ -0,0 +1,217 @@
|
|||
/*
|
||||
* Copyright (C) 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Michael Barkowski <michael.barkowski@freescale.com>
|
||||
* Based on mpc832xmds file by Dave Liu <daveliu@freescale.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License version 2 as published
|
||||
* by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <ioports.h>
|
||||
#include <mpc83xx.h>
|
||||
#include <i2c.h>
|
||||
#include <spd.h>
|
||||
#include <miiphy.h>
|
||||
#include <command.h>
|
||||
#include <libfdt.h>
|
||||
#include <libfdt_env.h>
|
||||
#if defined(CONFIG_PCI)
|
||||
#include <pci.h>
|
||||
#endif
|
||||
#if defined(CONFIG_SPD_EEPROM)
|
||||
#include <spd_sdram.h>
|
||||
#else
|
||||
#include <asm/mmu.h>
|
||||
#endif
|
||||
|
||||
const qe_iop_conf_t qe_iop_conf_tab[] = {
|
||||
/* UCC3 */
|
||||
{1, 0, 1, 0, 1}, /* TxD0 */
|
||||
{1, 1, 1, 0, 1}, /* TxD1 */
|
||||
{1, 2, 1, 0, 1}, /* TxD2 */
|
||||
{1, 3, 1, 0, 1}, /* TxD3 */
|
||||
{1, 9, 1, 0, 1}, /* TxER */
|
||||
{1, 12, 1, 0, 1}, /* TxEN */
|
||||
{3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
|
||||
|
||||
{1, 4, 2, 0, 1}, /* RxD0 */
|
||||
{1, 5, 2, 0, 1}, /* RxD1 */
|
||||
{1, 6, 2, 0, 1}, /* RxD2 */
|
||||
{1, 7, 2, 0, 1}, /* RxD3 */
|
||||
{1, 8, 2, 0, 1}, /* RxER */
|
||||
{1, 10, 2, 0, 1}, /* RxDV */
|
||||
{0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
|
||||
{1, 11, 2, 0, 1}, /* COL */
|
||||
{1, 13, 2, 0, 1}, /* CRS */
|
||||
|
||||
/* UCC2 */
|
||||
{0, 18, 1, 0, 1}, /* TxD0 */
|
||||
{0, 19, 1, 0, 1}, /* TxD1 */
|
||||
{0, 20, 1, 0, 1}, /* TxD2 */
|
||||
{0, 21, 1, 0, 1}, /* TxD3 */
|
||||
{0, 27, 1, 0, 1}, /* TxER */
|
||||
{0, 30, 1, 0, 1}, /* TxEN */
|
||||
{3, 23, 2, 0, 1}, /* TxCLK->CLK3 */
|
||||
|
||||
{0, 22, 2, 0, 1}, /* RxD0 */
|
||||
{0, 23, 2, 0, 1}, /* RxD1 */
|
||||
{0, 24, 2, 0, 1}, /* RxD2 */
|
||||
{0, 25, 2, 0, 1}, /* RxD3 */
|
||||
{0, 26, 1, 0, 1}, /* RxER */
|
||||
{0, 28, 2, 0, 1}, /* Rx_DV */
|
||||
{3, 21, 2, 0, 1}, /* RxCLK->CLK16 */
|
||||
{0, 29, 2, 0, 1}, /* COL */
|
||||
{0, 31, 2, 0, 1}, /* CRS */
|
||||
|
||||
{3, 4, 3, 0, 2}, /* MDIO */
|
||||
{3, 5, 1, 0, 2}, /* MDC */
|
||||
|
||||
{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
|
||||
};
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int fixed_sdram(void);
|
||||
|
||||
long int initdram(int board_type)
|
||||
{
|
||||
volatile immap_t *im = (immap_t *) CFG_IMMR;
|
||||
u32 msize = 0;
|
||||
|
||||
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
|
||||
return -1;
|
||||
|
||||
/* DDR SDRAM - Main SODIMM */
|
||||
im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
|
||||
|
||||
msize = fixed_sdram();
|
||||
|
||||
puts("\n DDR RAM: ");
|
||||
|
||||
/* return total bus SDRAM size(bytes) -- DDR */
|
||||
return (msize * 1024 * 1024);
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* fixed sdram init -- doesn't use serial presence detect.
|
||||
************************************************************************/
|
||||
int fixed_sdram(void)
|
||||
{
|
||||
volatile immap_t *im = (immap_t *) CFG_IMMR;
|
||||
u32 msize = 0;
|
||||
u32 ddr_size;
|
||||
u32 ddr_size_log2;
|
||||
|
||||
msize = CFG_DDR_SIZE;
|
||||
for (ddr_size = msize << 20, ddr_size_log2 = 0;
|
||||
(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
|
||||
if (ddr_size & 1) {
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
im->sysconf.ddrlaw[0].ar =
|
||||
LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
|
||||
im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
|
||||
im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
|
||||
im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
|
||||
im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
|
||||
im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
|
||||
im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
|
||||
im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
|
||||
im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
|
||||
im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
|
||||
im->ddr.sdram_mode = CFG_DDR_MODE;
|
||||
im->ddr.sdram_mode2 = CFG_DDR_MODE2;
|
||||
im->ddr.sdram_interval = CFG_DDR_INTERVAL;
|
||||
__asm__ __volatile__ ("sync");
|
||||
udelay(200);
|
||||
|
||||
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
|
||||
__asm__ __volatile__ ("sync");
|
||||
return msize;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: Freescale MPC8323ERDB\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct pci_region pci_regions[] = {
|
||||
{
|
||||
bus_start: CFG_PCI1_MEM_BASE,
|
||||
phys_start: CFG_PCI1_MEM_PHYS,
|
||||
size: CFG_PCI1_MEM_SIZE,
|
||||
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
|
||||
},
|
||||
{
|
||||
bus_start: CFG_PCI1_MMIO_BASE,
|
||||
phys_start: CFG_PCI1_MMIO_PHYS,
|
||||
size: CFG_PCI1_MMIO_SIZE,
|
||||
flags: PCI_REGION_MEM
|
||||
},
|
||||
{
|
||||
bus_start: CFG_PCI1_IO_BASE,
|
||||
phys_start: CFG_PCI1_IO_PHYS,
|
||||
size: CFG_PCI1_IO_SIZE,
|
||||
flags: PCI_REGION_IO
|
||||
}
|
||||
};
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
|
||||
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
|
||||
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
|
||||
struct pci_region *reg[] = { pci_regions };
|
||||
|
||||
/* Enable all 3 PCI_CLK_OUTPUTs. */
|
||||
clk->occr |= 0xe0000000;
|
||||
|
||||
/* Configure PCI Local Access Windows */
|
||||
pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
|
||||
pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
|
||||
|
||||
pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
|
||||
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
|
||||
|
||||
mpc83xx_pci_init(1, reg, 0);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
|
||||
/*
|
||||
* Prototypes of functions that we use.
|
||||
*/
|
||||
void ft_cpu_setup(void *blob, bd_t *bd);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
void ft_pci_setup(void *blob, bd_t *bd);
|
||||
#endif
|
||||
|
||||
void
|
||||
ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
int nodeoffset;
|
||||
int tmp[2];
|
||||
|
||||
nodeoffset = fdt_find_node_by_path(blob, "/memory");
|
||||
if (nodeoffset >= 0) {
|
||||
tmp[0] = cpu_to_be32(bd->bi_memstart);
|
||||
tmp[1] = cpu_to_be32(bd->bi_memsize);
|
||||
fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp));
|
||||
}
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
ft_pci_setup(blob, bd);
|
||||
#endif
|
||||
}
|
||||
#endif /* CONFIG_OF_BOARD_SETUP */
|
|
@ -52,8 +52,8 @@
|
|||
*/
|
||||
|
||||
#define entry_start \
|
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
mflr r1 ; \
|
||||
bl 0f ;
|
||||
|
||||
#define entry_end \
|
||||
0: mflr r0 ; \
|
||||
|
@ -214,7 +214,7 @@ law_entry:
|
|||
.long 0
|
||||
.long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
|
||||
|
||||
.long (CFG_PCI1_MEM_BASE>>12) & 0xfffff
|
||||
.long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
|
||||
.long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
|
||||
|
||||
.long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
|
||||
|
|
|
@ -22,8 +22,10 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <pci.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/immap_85xx.h>
|
||||
#include <asm/immap_fsl_pci.h>
|
||||
#include <spd.h>
|
||||
#include <miiphy.h>
|
||||
|
||||
|
@ -51,12 +53,19 @@ int checkboard (void)
|
|||
{
|
||||
volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
|
||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
||||
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
|
||||
volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
|
||||
|
||||
if ((uint)&gur->porpllsr != 0xe00e0000) {
|
||||
printf("immap size error %x\n",&gur->porpllsr);
|
||||
}
|
||||
printf ("Board: MPC8544DS\n");
|
||||
|
||||
lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
|
||||
lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
|
||||
ecm->eedr = 0xffffffff; /* Clear ecm errors */
|
||||
ecm->eeer = 0xffffffff; /* Enable ecm errors */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -118,6 +127,316 @@ testdram(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCI1
|
||||
static struct pci_controller pci1_hose;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCIE1
|
||||
static struct pci_controller pcie1_hose;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCIE2
|
||||
static struct pci_controller pcie2_hose;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCIE3
|
||||
static struct pci_controller pcie3_hose;
|
||||
#endif
|
||||
|
||||
int first_free_busno=0;
|
||||
|
||||
void
|
||||
pci_init_board(void)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
||||
uint devdisr = gur->devdisr;
|
||||
uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
|
||||
uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
|
||||
|
||||
debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
|
||||
devdisr, io_sel, host_agent);
|
||||
|
||||
if (io_sel & 1) {
|
||||
if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
|
||||
printf (" eTSEC1 is in sgmii mode.\n");
|
||||
if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
|
||||
printf (" eTSEC3 is in sgmii mode.\n");
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCIE3
|
||||
{
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pcie3_hose;
|
||||
int pcie_ep = (host_agent == 3);
|
||||
int pcie_configured = io_sel >= 1;
|
||||
|
||||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
|
||||
printf ("\n PCIE3 connected to ULI as %s (base address %x)",
|
||||
pcie_ep ? "End Point" : "Root Complex",
|
||||
(uint)pci);
|
||||
if (pci->pme_msg_det) {
|
||||
pci->pme_msg_det = 0xffffffff;
|
||||
debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
|
||||
}
|
||||
printf ("\n");
|
||||
|
||||
/* inbound */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CFG_PCI_MEMORY_BUS,
|
||||
CFG_PCI_MEMORY_PHYS,
|
||||
CFG_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 1,
|
||||
CFG_PCIE3_MEM_BASE,
|
||||
CFG_PCIE3_MEM_PHYS,
|
||||
CFG_PCIE3_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(hose->regions + 2,
|
||||
CFG_PCIE3_IO_BASE,
|
||||
CFG_PCIE3_IO_PHYS,
|
||||
CFG_PCIE3_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 3;
|
||||
#ifdef CFG_PCIE3_MEM_BASE2
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 3,
|
||||
CFG_PCIE3_MEM_BASE2,
|
||||
CFG_PCIE3_MEM_PHYS2,
|
||||
CFG_PCIE3_MEM_SIZE2,
|
||||
PCI_REGION_MEM);
|
||||
hose->region_count++;
|
||||
#endif
|
||||
hose->first_busno=first_free_busno;
|
||||
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
|
||||
|
||||
fsl_pci_init(hose);
|
||||
|
||||
first_free_busno=hose->last_busno+1;
|
||||
printf (" PCIE3 on bus %02x - %02x\n",
|
||||
hose->first_busno,hose->last_busno);
|
||||
|
||||
} else {
|
||||
printf (" PCIE3: disabled\n");
|
||||
}
|
||||
|
||||
}
|
||||
#else
|
||||
gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCIE1
|
||||
{
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pcie1_hose;
|
||||
int pcie_ep = (host_agent == 5);
|
||||
int pcie_configured = io_sel & 6;
|
||||
|
||||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
|
||||
printf ("\n PCIE1 connected to Slot2 as %s (base address %x)",
|
||||
pcie_ep ? "End Point" : "Root Complex",
|
||||
(uint)pci);
|
||||
if (pci->pme_msg_det) {
|
||||
pci->pme_msg_det = 0xffffffff;
|
||||
debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
|
||||
}
|
||||
printf ("\n");
|
||||
|
||||
/* inbound */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CFG_PCI_MEMORY_BUS,
|
||||
CFG_PCI_MEMORY_PHYS,
|
||||
CFG_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 1,
|
||||
CFG_PCIE1_MEM_BASE,
|
||||
CFG_PCIE1_MEM_PHYS,
|
||||
CFG_PCIE1_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(hose->regions + 2,
|
||||
CFG_PCIE1_IO_BASE,
|
||||
CFG_PCIE1_IO_PHYS,
|
||||
CFG_PCIE1_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 3;
|
||||
#ifdef CFG_PCIE1_MEM_BASE2
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 3,
|
||||
CFG_PCIE1_MEM_BASE2,
|
||||
CFG_PCIE1_MEM_PHYS2,
|
||||
CFG_PCIE1_MEM_SIZE2,
|
||||
PCI_REGION_MEM);
|
||||
hose->region_count++;
|
||||
#endif
|
||||
hose->first_busno=first_free_busno;
|
||||
|
||||
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
|
||||
|
||||
fsl_pci_init(hose);
|
||||
|
||||
first_free_busno=hose->last_busno+1;
|
||||
printf(" PCIE1 on bus %02x - %02x\n",
|
||||
hose->first_busno,hose->last_busno);
|
||||
|
||||
} else {
|
||||
printf (" PCIE1: disabled\n");
|
||||
}
|
||||
|
||||
}
|
||||
#else
|
||||
gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PCIE2
|
||||
{
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pcie2_hose;
|
||||
int pcie_ep = (host_agent == 3);
|
||||
int pcie_configured = io_sel & 4;
|
||||
|
||||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
|
||||
printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
|
||||
pcie_ep ? "End Point" : "Root Complex",
|
||||
(uint)pci);
|
||||
if (pci->pme_msg_det) {
|
||||
pci->pme_msg_det = 0xffffffff;
|
||||
debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
|
||||
}
|
||||
printf ("\n");
|
||||
|
||||
/* inbound */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CFG_PCI_MEMORY_BUS,
|
||||
CFG_PCI_MEMORY_PHYS,
|
||||
CFG_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 1,
|
||||
CFG_PCIE2_MEM_BASE,
|
||||
CFG_PCIE2_MEM_PHYS,
|
||||
CFG_PCIE2_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(hose->regions + 2,
|
||||
CFG_PCIE2_IO_BASE,
|
||||
CFG_PCIE2_IO_PHYS,
|
||||
CFG_PCIE2_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 3;
|
||||
#ifdef CFG_PCIE2_MEM_BASE2
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 3,
|
||||
CFG_PCIE2_MEM_BASE2,
|
||||
CFG_PCIE2_MEM_PHYS2,
|
||||
CFG_PCIE2_MEM_SIZE2,
|
||||
PCI_REGION_MEM);
|
||||
hose->region_count++;
|
||||
#endif
|
||||
hose->first_busno=first_free_busno;
|
||||
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
|
||||
|
||||
fsl_pci_init(hose);
|
||||
first_free_busno=hose->last_busno+1;
|
||||
printf (" PCIE2 on bus %02x - %02x\n",
|
||||
hose->first_busno,hose->last_busno);
|
||||
|
||||
} else {
|
||||
printf (" PCIE2: disabled\n");
|
||||
}
|
||||
|
||||
}
|
||||
#else
|
||||
gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_PCI1
|
||||
{
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pci1_hose;
|
||||
|
||||
uint pci_agent = (host_agent == 6);
|
||||
uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
|
||||
uint pci_32 = 1;
|
||||
uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
|
||||
uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
|
||||
|
||||
|
||||
if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
|
||||
printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
|
||||
(pci_32) ? 32 : 64,
|
||||
(pci_speed == 33333000) ? "33" :
|
||||
(pci_speed == 66666000) ? "66" : "unknown",
|
||||
pci_clk_sel ? "sync" : "async",
|
||||
pci_agent ? "agent" : "host",
|
||||
pci_arb ? "arbiter" : "external-arbiter",
|
||||
(uint)pci
|
||||
);
|
||||
|
||||
/* inbound */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CFG_PCI_MEMORY_BUS,
|
||||
CFG_PCI_MEMORY_PHYS,
|
||||
CFG_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 1,
|
||||
CFG_PCI1_MEM_BASE,
|
||||
CFG_PCI1_MEM_PHYS,
|
||||
CFG_PCI1_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(hose->regions + 2,
|
||||
CFG_PCI1_IO_BASE,
|
||||
CFG_PCI1_IO_PHYS,
|
||||
CFG_PCI1_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
hose->region_count = 3;
|
||||
#ifdef CFG_PCIE3_MEM_BASE2
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 3,
|
||||
CFG_PCIE3_MEM_BASE2,
|
||||
CFG_PCIE3_MEM_PHYS2,
|
||||
CFG_PCIE3_MEM_SIZE2,
|
||||
PCI_REGION_MEM);
|
||||
hose->region_count++;
|
||||
#endif
|
||||
hose->first_busno=first_free_busno;
|
||||
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
|
||||
|
||||
fsl_pci_init(hose);
|
||||
first_free_busno=hose->last_busno+1;
|
||||
printf ("PCI on bus %02x - %02x\n",
|
||||
hose->first_busno,hose->last_busno);
|
||||
} else {
|
||||
printf (" PCI: disabled\n");
|
||||
}
|
||||
}
|
||||
#else
|
||||
gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
int last_stage_init(void)
|
||||
{
|
||||
return 0;
|
||||
|
@ -192,6 +511,37 @@ ft_board_setup(void *blob, bd_t *bd)
|
|||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
p = ft_get_prop(blob, "/memory/reg", &len);
|
||||
if (p != NULL) {
|
||||
*p++ = cpu_to_be32(bd->bi_memstart);
|
||||
*p = cpu_to_be32(bd->bi_memsize);
|
||||
}
|
||||
#ifdef CONFIG_PCIE1
|
||||
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len);
|
||||
if (p != NULL) {
|
||||
p[0] = 0;
|
||||
p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
|
||||
debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE2
|
||||
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len);
|
||||
if (p != NULL) {
|
||||
p[0] = 0;
|
||||
p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
|
||||
debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE3
|
||||
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@b000/bus-range", &len);
|
||||
if (p != NULL) {
|
||||
p[0] = 0;
|
||||
p[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;;
|
||||
debug("PCI@b000 first_busno=%d last_busno=%d\n",p[0],p[1]);
|
||||
}
|
||||
#endif
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
p = ft_get_prop(blob, "/memory/reg", &len);
|
||||
if (p != NULL) {
|
||||
*p++ = cpu_to_be32(bd->bi_memstart);
|
||||
|
|
|
@ -45,16 +45,16 @@ int board_early_init_f(void)
|
|||
mtdcr(uic0sr, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
|
||||
mtdcr(uic0er, 0x00000000); /* disable all */
|
||||
mtdcr(uic0cr, 0x00000000); /* we have not critical interrupts at the moment */
|
||||
mtdcr(uic0pr, 0xfffff7ff); /* Adjustment of the polarity */
|
||||
mtdcr(uic0tr, 0x00000810); /* per ref-board manual */
|
||||
mtdcr(uic0pr, 0xFFBFF1EF); /* Adjustment of the polarity */
|
||||
mtdcr(uic0tr, 0x00000900); /* per ref-board manual */
|
||||
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
|
||||
mtdcr(uic0sr, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr(uic1sr, 0xffffffff); /* clear all */
|
||||
mtdcr(uic1er, 0x00000000); /* disable all */
|
||||
mtdcr(uic1cr, 0x00000000); /* all non-critical */
|
||||
mtdcr(uic1pr, 0xFFFFC7AD); /* Adjustment of the polarity */
|
||||
mtdcr(uic1tr, 0x0600384A); /* per ref-board manual */
|
||||
mtdcr(uic1pr, 0xFFFFC6A5); /* Adjustment of the polarity */
|
||||
mtdcr(uic1tr, 0x60000040); /* per ref-board manual */
|
||||
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
|
||||
mtdcr(uic1sr, 0xffffffff); /* clear all */
|
||||
|
||||
|
@ -62,9 +62,9 @@ int board_early_init_f(void)
|
|||
mtdcr(uic2er, 0x00000000); /* disable all */
|
||||
mtdcr(uic2cr, 0x00000000); /* all non-critical */
|
||||
mtdcr(uic2pr, 0x27C00000); /* Adjustment of the polarity */
|
||||
mtdcr(uic2tr, 0xDFC00000); /* per ref-board manual */
|
||||
mtdcr(uic2tr, 0x3C000000); /* per ref-board manual */
|
||||
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
|
||||
mtdcr(uic2sr, 0xffffffff); /* clear all. Why this??? */
|
||||
mtdcr(uic2sr, 0xffffffff); /* clear all */
|
||||
|
||||
/* Trace Pins are disabled. SDR0_PFC0 Register */
|
||||
mtsdr(SDR0_PFC0, 0x0);
|
||||
|
@ -158,13 +158,13 @@ int misc_init_r(void)
|
|||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
-CFG_MONITOR_LEN,
|
||||
0xffffffff,
|
||||
&flash_info[0]);
|
||||
&flash_info[1]);
|
||||
|
||||
/* Env protection ON by default */
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
CFG_ENV_ADDR_REDUND,
|
||||
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
|
||||
&flash_info[0]);
|
||||
&flash_info[1]);
|
||||
|
||||
/*
|
||||
* USB suff...
|
||||
|
@ -221,8 +221,8 @@ int misc_init_r(void)
|
|||
udelay(500);
|
||||
gpio_write_bit(CFG_GPIO_LIME_RST, 1);
|
||||
|
||||
/* Lime memory clock adjusted to 133MHz */
|
||||
out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_133MHZ);
|
||||
/* Lime memory clock adjusted to 100MHz */
|
||||
out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_100MHZ);
|
||||
/* Wait untill time expired. Because of requirements in lime manual */
|
||||
udelay(300);
|
||||
/* Write lime controller memory parameters */
|
||||
|
@ -237,6 +237,64 @@ int misc_init_r(void)
|
|||
gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
|
||||
gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
|
||||
|
||||
/*
|
||||
* Init display controller
|
||||
*/
|
||||
/* Setup dot clock (internal PLL, division rate 1/16) */
|
||||
out_be32((void *)0xc1fd0100, 0x00000f00);
|
||||
|
||||
/* Lime L0 init (16 bpp, 640x480) */
|
||||
out_be32((void *)0xc1fd0020, 0x801401df);
|
||||
out_be32((void *)0xc1fd0024, 0x0);
|
||||
out_be32((void *)0xc1fd0028, 0x0);
|
||||
out_be32((void *)0xc1fd002c, 0x0);
|
||||
out_be32((void *)0xc1fd0110, 0x0);
|
||||
out_be32((void *)0xc1fd0114, 0x0);
|
||||
out_be32((void *)0xc1fd0118, 0x01df0280);
|
||||
|
||||
/* Display timing init */
|
||||
out_be32((void *)0xc1fd0004, 0x031f0000);
|
||||
out_be32((void *)0xc1fd0008, 0x027f027f);
|
||||
out_be32((void *)0xc1fd000c, 0x015f028f);
|
||||
out_be32((void *)0xc1fd0010, 0x020c0000);
|
||||
out_be32((void *)0xc1fd0014, 0x01df01ea);
|
||||
out_be32((void *)0xc1fd0018, 0x0);
|
||||
out_be32((void *)0xc1fd001c, 0x01e00280);
|
||||
|
||||
#if 1
|
||||
/*
|
||||
* Clear framebuffer using Lime's drawing engine
|
||||
* (draw blue rect. with white border around it)
|
||||
*/
|
||||
/* Setup mode and fbbase, xres, fg, bg */
|
||||
out_be32((void *)0xc1ff0420, 0x8300);
|
||||
out_be32((void *)0xc1ff0440, 0x0000);
|
||||
out_be32((void *)0xc1ff0444, 0x0280);
|
||||
out_be32((void *)0xc1ff0480, 0x7fff);
|
||||
out_be32((void *)0xc1ff0484, 0x0000);
|
||||
/* Reset clipping rectangle */
|
||||
out_be32((void *)0xc1ff0454, 0x0000);
|
||||
out_be32((void *)0xc1ff0458, 0x0280);
|
||||
out_be32((void *)0xc1ff045c, 0x0000);
|
||||
out_be32((void *)0xc1ff0460, 0x01e0);
|
||||
/* Draw white rect. */
|
||||
out_be32((void *)0xc1ff04a0, 0x09410000);
|
||||
out_be32((void *)0xc1ff04a0, 0x00000000);
|
||||
out_be32((void *)0xc1ff04a0, 0x01e00280);
|
||||
udelay(2000);
|
||||
/* Draw blue rect. */
|
||||
out_be32((void *)0xc1ff0480, 0x001f);
|
||||
out_be32((void *)0xc1ff04a0, 0x09410000);
|
||||
out_be32((void *)0xc1ff04a0, 0x00010001);
|
||||
out_be32((void *)0xc1ff04a0, 0x01de027e);
|
||||
#endif
|
||||
/* Display enable, L0 layer */
|
||||
out_be32((void *)0xc1fd0100, 0x80010f00);
|
||||
|
||||
/* TFT-LCD enable - PWM duty, lamp on */
|
||||
out_be32((void *)0xc4000024, 0x64);
|
||||
out_be32((void *)0xc4000020, 0x701);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -463,3 +521,14 @@ void hw_watchdog_reset(void)
|
|||
val = gpio_read_out_bit(CFG_GPIO_WATCHDOG) == 0 ? 1 : 0;
|
||||
gpio_write_bit(CFG_GPIO_WATCHDOG, val);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_POST
|
||||
/*
|
||||
* Returns 1 if keys pressed to start the power-on long-running tests
|
||||
* Called from board_init_f().
|
||||
*/
|
||||
int post_hotkeys_pressed(void)
|
||||
{
|
||||
return (ctrlc());
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -54,7 +54,6 @@
|
|||
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
|
||||
#endif
|
||||
|
||||
void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
|
||||
void dcbz_area(u32 start_address, u32 num_bytes);
|
||||
void dflush(void);
|
||||
|
||||
|
@ -474,7 +473,7 @@ static void program_ecc(u32 start_address,
|
|||
blank_string(strlen(str));
|
||||
} else {
|
||||
/* ECC bit set method for cached memory */
|
||||
#if 1 /* test-only: will remove this define later, when ECC problems are solved! */
|
||||
#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
|
||||
/*
|
||||
* Some boards (like lwmon5) need to preserve the memory
|
||||
* content upon ECC generation (for the log-buffer).
|
||||
|
@ -487,6 +486,11 @@ static void program_ecc(u32 start_address,
|
|||
|
||||
current_address = start_address;
|
||||
while (current_address < end_address) {
|
||||
/*
|
||||
* TODO: Th following sequence doesn't work correctly.
|
||||
* Just invalidating and flushing the cache doesn't
|
||||
* seem to trigger the re-write of the memory.
|
||||
*/
|
||||
ppcDcbi(current_address);
|
||||
ppcDcbf(current_address);
|
||||
current_address += CFG_CACHELINE_SIZE;
|
||||
|
@ -515,19 +519,6 @@ static void program_ecc(u32 start_address,
|
|||
}
|
||||
#endif
|
||||
|
||||
static __inline__ u32 get_mcsr(void)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
|
||||
return val;
|
||||
}
|
||||
|
||||
static __inline__ void set_mcsr(u32 val)
|
||||
{
|
||||
asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
*
|
||||
* initdram -- 440EPx's DDR controller is a DENALI Core
|
||||
|
@ -535,8 +526,6 @@ static __inline__ void set_mcsr(u32 val)
|
|||
************************************************************************/
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
|
||||
/* CL=3 */
|
||||
mtsdram(DDR0_02, 0x00000000);
|
||||
|
@ -641,14 +630,6 @@ long int initdram (int board_type)
|
|||
* Perform data eye search if requested.
|
||||
*/
|
||||
denali_core_search_data_eye(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20);
|
||||
|
||||
/*
|
||||
* Clear possible errors resulting from data-eye-search.
|
||||
* If not done, then we could get an interrupt later on when
|
||||
* exceptions are enabled.
|
||||
*/
|
||||
val = get_mcsr();
|
||||
set_mcsr(val);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
|
@ -658,5 +639,12 @@ long int initdram (int board_type)
|
|||
program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Clear possible errors resulting from data-eye-search.
|
||||
* If not done, then we could get an interrupt later on when
|
||||
* exceptions are enabled.
|
||||
*/
|
||||
set_mcsr(get_mcsr());
|
||||
|
||||
return (CFG_MBYTES_SDRAM << 20);
|
||||
}
|
||||
|
|
|
@ -330,6 +330,8 @@ int do_auto_update(void)
|
|||
int i, res = 0, bitmap_first, cnt, old_ctrlc, got_ctrlc;
|
||||
char *env;
|
||||
long start, end;
|
||||
|
||||
#if 0 /* disable key-press detection to speed up boot-up time */
|
||||
uchar keypad_status1[2] = {0,0}, keypad_status2[2] = {0,0};
|
||||
|
||||
/*
|
||||
|
@ -347,6 +349,7 @@ int do_auto_update(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
au_usb_stor_curr_dev = -1;
|
||||
/* start USB */
|
||||
if (usb_stop() < 0) {
|
||||
|
@ -364,18 +367,21 @@ int do_auto_update(void)
|
|||
au_usb_stor_curr_dev = usb_stor_scan(0);
|
||||
if (au_usb_stor_curr_dev == -1) {
|
||||
debug ("No device found. Not initialized?\n");
|
||||
return -1;
|
||||
res = -1;
|
||||
goto xit;
|
||||
}
|
||||
/* check whether it has a partition table */
|
||||
stor_dev = get_dev("usb", 0);
|
||||
if (stor_dev == NULL) {
|
||||
debug ("uknown device type\n");
|
||||
return -1;
|
||||
res = -1;
|
||||
goto xit;
|
||||
}
|
||||
if (fat_register_device(stor_dev, 1) != 0) {
|
||||
debug ("Unable to use USB %d:%d for fatls\n",
|
||||
au_usb_stor_curr_dev, 1);
|
||||
return -1;
|
||||
res = -1;
|
||||
goto xit;
|
||||
}
|
||||
if (file_fat_detectfs() != 0) {
|
||||
debug ("file_fat_detectfs failed\n");
|
||||
|
@ -504,7 +510,7 @@ int do_auto_update(void)
|
|||
} while (res < 0);
|
||||
#endif
|
||||
}
|
||||
usb_stop();
|
||||
|
||||
/* restore the old state */
|
||||
disable_ctrlc(old_ctrlc);
|
||||
#ifdef CONFIG_PROGRESSBAR
|
||||
|
@ -517,6 +523,8 @@ int do_auto_update(void)
|
|||
lcd_enable();
|
||||
}
|
||||
#endif
|
||||
return 0;
|
||||
xit:
|
||||
usb_stop();
|
||||
return res;
|
||||
}
|
||||
#endif /* CONFIG_AUTO_UPDATE */
|
||||
|
|
|
@ -29,7 +29,6 @@
|
|||
#include <i2c.h>
|
||||
#include <spd.h>
|
||||
#include <miiphy.h>
|
||||
#include <command.h>
|
||||
#if defined(CONFIG_SPD_EEPROM)
|
||||
#include <spd_sdram.h>
|
||||
#endif
|
||||
|
@ -258,332 +257,6 @@ void sdram_init(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
|
||||
/*
|
||||
* ECC user commands
|
||||
*/
|
||||
void ecc_print_status(void)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
||||
volatile ddr83xx_t *ddr = &immap->ddr;
|
||||
|
||||
printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
|
||||
|
||||
/* Interrupts */
|
||||
printf("Memory Error Interrupt Enable:\n");
|
||||
printf(" Multiple-Bit Error Interrupt Enable: %d\n",
|
||||
(ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
|
||||
printf(" Single-Bit Error Interrupt Enable: %d\n",
|
||||
(ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
|
||||
printf(" Memory Select Error Interrupt Enable: %d\n\n",
|
||||
(ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
|
||||
|
||||
/* Error disable */
|
||||
printf("Memory Error Disable:\n");
|
||||
printf(" Multiple-Bit Error Disable: %d\n",
|
||||
(ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
|
||||
printf(" Sinle-Bit Error Disable: %d\n",
|
||||
(ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
|
||||
printf(" Memory Select Error Disable: %d\n\n",
|
||||
(ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
|
||||
|
||||
/* Error injection */
|
||||
printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
|
||||
ddr->data_err_inject_hi, ddr->data_err_inject_lo);
|
||||
|
||||
printf("Memory Data Path Error Injection Mask ECC:\n");
|
||||
printf(" ECC Mirror Byte: %d\n",
|
||||
(ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
|
||||
printf(" ECC Injection Enable: %d\n",
|
||||
(ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
|
||||
printf(" ECC Error Injection Mask: 0x%02x\n\n",
|
||||
ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
|
||||
|
||||
/* SBE counter/threshold */
|
||||
printf("Memory Single-Bit Error Management (0..255):\n");
|
||||
printf(" Single-Bit Error Threshold: %d\n",
|
||||
(ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
|
||||
printf(" Single-Bit Error Counter: %d\n\n",
|
||||
(ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
|
||||
|
||||
/* Error detect */
|
||||
printf("Memory Error Detect:\n");
|
||||
printf(" Multiple Memory Errors: %d\n",
|
||||
(ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
|
||||
printf(" Multiple-Bit Error: %d\n",
|
||||
(ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
|
||||
printf(" Single-Bit Error: %d\n",
|
||||
(ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
|
||||
printf(" Memory Select Error: %d\n\n",
|
||||
(ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
|
||||
|
||||
/* Capture data */
|
||||
printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
|
||||
printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
|
||||
ddr->capture_data_hi, ddr->capture_data_lo);
|
||||
printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
|
||||
ddr->capture_ecc & CAPTURE_ECC_ECE);
|
||||
|
||||
printf("Memory Error Attributes Capture:\n");
|
||||
printf(" Data Beat Number: %d\n",
|
||||
(ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT);
|
||||
printf(" Transaction Size: %d\n",
|
||||
(ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT);
|
||||
printf(" Transaction Source: %d\n",
|
||||
(ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT);
|
||||
printf(" Transaction Type: %d\n",
|
||||
(ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT);
|
||||
printf(" Error Information Valid: %d\n\n",
|
||||
ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
|
||||
}
|
||||
|
||||
int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
||||
volatile ddr83xx_t *ddr = &immap->ddr;
|
||||
volatile u32 val;
|
||||
u64 *addr, count, val64;
|
||||
register u64 *i;
|
||||
|
||||
if (argc > 4) {
|
||||
printf ("Usage:\n%s\n", cmdtp->usage);
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (argc == 2) {
|
||||
if (strcmp(argv[1], "status") == 0) {
|
||||
ecc_print_status();
|
||||
return 0;
|
||||
} else if (strcmp(argv[1], "captureclear") == 0) {
|
||||
ddr->capture_address = 0;
|
||||
ddr->capture_data_hi = 0;
|
||||
ddr->capture_data_lo = 0;
|
||||
ddr->capture_ecc = 0;
|
||||
ddr->capture_attributes = 0;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
if (argc == 3) {
|
||||
if (strcmp(argv[1], "sbecnt") == 0) {
|
||||
val = simple_strtoul(argv[2], NULL, 10);
|
||||
if (val > 255) {
|
||||
printf("Incorrect Counter value, should be 0..255\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
|
||||
val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
|
||||
|
||||
ddr->err_sbe = val;
|
||||
return 0;
|
||||
} else if (strcmp(argv[1], "sbethr") == 0) {
|
||||
val = simple_strtoul(argv[2], NULL, 10);
|
||||
if (val > 255) {
|
||||
printf("Incorrect Counter value, should be 0..255\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
val = (val << ECC_ERROR_MAN_SBET_SHIFT);
|
||||
val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
|
||||
|
||||
ddr->err_sbe = val;
|
||||
return 0;
|
||||
} else if (strcmp(argv[1], "errdisable") == 0) {
|
||||
val = ddr->err_disable;
|
||||
|
||||
if (strcmp(argv[2], "+sbe") == 0) {
|
||||
val |= ECC_ERROR_DISABLE_SBED;
|
||||
} else if (strcmp(argv[2], "+mbe") == 0) {
|
||||
val |= ECC_ERROR_DISABLE_MBED;
|
||||
} else if (strcmp(argv[2], "+mse") == 0) {
|
||||
val |= ECC_ERROR_DISABLE_MSED;
|
||||
} else if (strcmp(argv[2], "+all") == 0) {
|
||||
val |= (ECC_ERROR_DISABLE_SBED |
|
||||
ECC_ERROR_DISABLE_MBED |
|
||||
ECC_ERROR_DISABLE_MSED);
|
||||
} else if (strcmp(argv[2], "-sbe") == 0) {
|
||||
val &= ~ECC_ERROR_DISABLE_SBED;
|
||||
} else if (strcmp(argv[2], "-mbe") == 0) {
|
||||
val &= ~ECC_ERROR_DISABLE_MBED;
|
||||
} else if (strcmp(argv[2], "-mse") == 0) {
|
||||
val &= ~ECC_ERROR_DISABLE_MSED;
|
||||
} else if (strcmp(argv[2], "-all") == 0) {
|
||||
val &= ~(ECC_ERROR_DISABLE_SBED |
|
||||
ECC_ERROR_DISABLE_MBED |
|
||||
ECC_ERROR_DISABLE_MSED);
|
||||
} else {
|
||||
printf("Incorrect err_disable field\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
ddr->err_disable = val;
|
||||
__asm__ __volatile__ ("sync");
|
||||
__asm__ __volatile__ ("isync");
|
||||
return 0;
|
||||
} else if (strcmp(argv[1], "errdetectclr") == 0) {
|
||||
val = ddr->err_detect;
|
||||
|
||||
if (strcmp(argv[2], "mme") == 0) {
|
||||
val |= ECC_ERROR_DETECT_MME;
|
||||
} else if (strcmp(argv[2], "sbe") == 0) {
|
||||
val |= ECC_ERROR_DETECT_SBE;
|
||||
} else if (strcmp(argv[2], "mbe") == 0) {
|
||||
val |= ECC_ERROR_DETECT_MBE;
|
||||
} else if (strcmp(argv[2], "mse") == 0) {
|
||||
val |= ECC_ERROR_DETECT_MSE;
|
||||
} else if (strcmp(argv[2], "all") == 0) {
|
||||
val |= (ECC_ERROR_DETECT_MME |
|
||||
ECC_ERROR_DETECT_MBE |
|
||||
ECC_ERROR_DETECT_SBE |
|
||||
ECC_ERROR_DETECT_MSE);
|
||||
} else {
|
||||
printf("Incorrect err_detect field\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
ddr->err_detect = val;
|
||||
return 0;
|
||||
} else if (strcmp(argv[1], "injectdatahi") == 0) {
|
||||
val = simple_strtoul(argv[2], NULL, 16);
|
||||
|
||||
ddr->data_err_inject_hi = val;
|
||||
return 0;
|
||||
} else if (strcmp(argv[1], "injectdatalo") == 0) {
|
||||
val = simple_strtoul(argv[2], NULL, 16);
|
||||
|
||||
ddr->data_err_inject_lo = val;
|
||||
return 0;
|
||||
} else if (strcmp(argv[1], "injectecc") == 0) {
|
||||
val = simple_strtoul(argv[2], NULL, 16);
|
||||
if (val > 0xff) {
|
||||
printf("Incorrect ECC inject mask, should be 0x00..0xff\n");
|
||||
return 1;
|
||||
}
|
||||
val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
|
||||
|
||||
ddr->ecc_err_inject = val;
|
||||
return 0;
|
||||
} else if (strcmp(argv[1], "inject") == 0) {
|
||||
val = ddr->ecc_err_inject;
|
||||
|
||||
if (strcmp(argv[2], "en") == 0)
|
||||
val |= ECC_ERR_INJECT_EIEN;
|
||||
else if (strcmp(argv[2], "dis") == 0)
|
||||
val &= ~ECC_ERR_INJECT_EIEN;
|
||||
else
|
||||
printf("Incorrect command\n");
|
||||
|
||||
ddr->ecc_err_inject = val;
|
||||
__asm__ __volatile__ ("sync");
|
||||
__asm__ __volatile__ ("isync");
|
||||
return 0;
|
||||
} else if (strcmp(argv[1], "mirror") == 0) {
|
||||
val = ddr->ecc_err_inject;
|
||||
|
||||
if (strcmp(argv[2], "en") == 0)
|
||||
val |= ECC_ERR_INJECT_EMB;
|
||||
else if (strcmp(argv[2], "dis") == 0)
|
||||
val &= ~ECC_ERR_INJECT_EMB;
|
||||
else
|
||||
printf("Incorrect command\n");
|
||||
|
||||
ddr->ecc_err_inject = val;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
if (argc == 4) {
|
||||
if (strcmp(argv[1], "test") == 0) {
|
||||
addr = (u64 *)simple_strtoul(argv[2], NULL, 16);
|
||||
count = simple_strtoul(argv[3], NULL, 16);
|
||||
|
||||
if ((u32)addr % 8) {
|
||||
printf("Address not alligned on double word boundary\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
disable_interrupts();
|
||||
icache_disable();
|
||||
|
||||
for (i = addr; i < addr + count; i++) {
|
||||
/* enable injects */
|
||||
ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
|
||||
__asm__ __volatile__ ("sync");
|
||||
__asm__ __volatile__ ("isync");
|
||||
|
||||
/* write memory location injecting errors */
|
||||
*i = 0x1122334455667788ULL;
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
/* disable injects */
|
||||
ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
|
||||
__asm__ __volatile__ ("sync");
|
||||
__asm__ __volatile__ ("isync");
|
||||
|
||||
/* read data, this generates ECC error */
|
||||
val64 = *i;
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
/* disable errors for ECC */
|
||||
ddr->err_disable |= ~ECC_ERROR_ENABLE;
|
||||
__asm__ __volatile__ ("sync");
|
||||
__asm__ __volatile__ ("isync");
|
||||
|
||||
/* re-initialize memory, write the location again
|
||||
* NOT injecting errors this time */
|
||||
*i = 0xcafecafecafecafeULL;
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
/* enable errors for ECC */
|
||||
ddr->err_disable &= ECC_ERROR_ENABLE;
|
||||
__asm__ __volatile__ ("sync");
|
||||
__asm__ __volatile__ ("isync");
|
||||
}
|
||||
|
||||
icache_enable();
|
||||
enable_interrupts();
|
||||
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
printf ("Usage:\n%s\n", cmdtp->usage);
|
||||
return 1;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
ecc, 4, 0, do_ecc,
|
||||
"ecc - support for DDR ECC features\n",
|
||||
"status - print out status info\n"
|
||||
"ecc captureclear - clear capture regs data\n"
|
||||
"ecc sbecnt <val> - set Single-Bit Error counter\n"
|
||||
"ecc sbethr <val> - set Single-Bit Threshold\n"
|
||||
"ecc errdisable <flag> - clear/set disable Memory Error Disable, flag:\n"
|
||||
" [-|+]sbe - Single-Bit Error\n"
|
||||
" [-|+]mbe - Multiple-Bit Error\n"
|
||||
" [-|+]mse - Memory Select Error\n"
|
||||
" [-|+]all - all errors\n"
|
||||
"ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
|
||||
" mme - Multiple Memory Errors\n"
|
||||
" sbe - Single-Bit Error\n"
|
||||
" mbe - Multiple-Bit Error\n"
|
||||
" mse - Memory Select Error\n"
|
||||
" all - all errors\n"
|
||||
"ecc injectdatahi <hi> - set Memory Data Path Error Injection Mask High\n"
|
||||
"ecc injectdatalo <lo> - set Memory Data Path Error Injection Mask Low\n"
|
||||
"ecc injectecc <ecc> - set ECC Error Injection Mask\n"
|
||||
"ecc inject <en|dis> - enable/disable error injection\n"
|
||||
"ecc mirror <en|dis> - enable/disable mirror byte\n"
|
||||
"ecc test <addr> <cnt> - test mem region:\n"
|
||||
" - enables injects\n"
|
||||
" - writes pattern injecting errors\n"
|
||||
" - disables injects\n"
|
||||
" - reads pattern back, generates error\n"
|
||||
" - re-inits memory"
|
||||
);
|
||||
#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
|
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
void
|
||||
ft_board_setup(void *blob, bd_t *bd)
|
||||
|
|
|
@ -29,9 +29,3 @@ sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
|
|||
ifndef TEXT_BASE
|
||||
TEXT_BASE = 0xFEF00000
|
||||
endif
|
||||
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
# We are building u-boot in a separate directory, use generated
|
||||
# .lds script from OBJTREE directory.
|
||||
LDSCRIPT := $(OBJTREE)/board/$(BOARDDIR)/u-boot.lds
|
||||
endif
|
||||
|
|
|
@ -1,8 +1,6 @@
|
|||
/*
|
||||
* Copyright (C) 2006 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Dave Liu <daveliu@freescale.com>
|
||||
* based on board/mpc8349emds/mpc8349emds.c
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
@ -19,7 +17,6 @@
|
|||
#include <i2c.h>
|
||||
#include <spd.h>
|
||||
#include <miiphy.h>
|
||||
#include <command.h>
|
||||
#if defined(CONFIG_PCI)
|
||||
#include <pci.h>
|
||||
#endif
|
||||
|
@ -30,8 +27,7 @@
|
|||
#endif
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
#include <ft_build.h>
|
||||
#endif
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
#elif defined(CONFIG_OF_LIBFDT)
|
||||
#include <libfdt.h>
|
||||
#include <libfdt_env.h>
|
||||
#endif
|
||||
|
@ -103,7 +99,9 @@ int board_early_init_f(void)
|
|||
|
||||
/* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2 h/w bug workaround) */
|
||||
if (immr->sysconf.spridr == SPR_8360_REV20 ||
|
||||
immr->sysconf.spridr == SPR_8360E_REV20)
|
||||
immr->sysconf.spridr == SPR_8360E_REV20 ||
|
||||
immr->sysconf.spridr == SPR_8360_REV21 ||
|
||||
immr->sysconf.spridr == SPR_8360E_REV21)
|
||||
bcsr[0xe] = 0x30;
|
||||
|
||||
return 0;
|
||||
|
@ -287,381 +285,6 @@ void sdram_init(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
|
||||
/*
|
||||
* ECC user commands
|
||||
*/
|
||||
void ecc_print_status(void)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||
volatile ddr83xx_t *ddr = &immap->ddr;
|
||||
|
||||
printf("\nECC mode: %s\n\n",
|
||||
(ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
|
||||
|
||||
/* Interrupts */
|
||||
printf("Memory Error Interrupt Enable:\n");
|
||||
printf(" Multiple-Bit Error Interrupt Enable: %d\n",
|
||||
(ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
|
||||
printf(" Single-Bit Error Interrupt Enable: %d\n",
|
||||
(ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
|
||||
printf(" Memory Select Error Interrupt Enable: %d\n\n",
|
||||
(ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
|
||||
|
||||
/* Error disable */
|
||||
printf("Memory Error Disable:\n");
|
||||
printf(" Multiple-Bit Error Disable: %d\n",
|
||||
(ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
|
||||
printf(" Sinle-Bit Error Disable: %d\n",
|
||||
(ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
|
||||
printf(" Memory Select Error Disable: %d\n\n",
|
||||
(ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
|
||||
|
||||
/* Error injection */
|
||||
printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
|
||||
ddr->data_err_inject_hi, ddr->data_err_inject_lo);
|
||||
|
||||
printf("Memory Data Path Error Injection Mask ECC:\n");
|
||||
printf(" ECC Mirror Byte: %d\n",
|
||||
(ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
|
||||
printf(" ECC Injection Enable: %d\n",
|
||||
(ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
|
||||
printf(" ECC Error Injection Mask: 0x%02x\n\n",
|
||||
ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
|
||||
|
||||
/* SBE counter/threshold */
|
||||
printf("Memory Single-Bit Error Management (0..255):\n");
|
||||
printf(" Single-Bit Error Threshold: %d\n",
|
||||
(ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
|
||||
printf(" Single-Bit Error Counter: %d\n\n",
|
||||
(ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
|
||||
|
||||
/* Error detect */
|
||||
printf("Memory Error Detect:\n");
|
||||
printf(" Multiple Memory Errors: %d\n",
|
||||
(ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
|
||||
printf(" Multiple-Bit Error: %d\n",
|
||||
(ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
|
||||
printf(" Single-Bit Error: %d\n",
|
||||
(ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
|
||||
printf(" Memory Select Error: %d\n\n",
|
||||
(ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
|
||||
|
||||
/* Capture data */
|
||||
printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
|
||||
printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
|
||||
ddr->capture_data_hi, ddr->capture_data_lo);
|
||||
printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
|
||||
ddr->capture_ecc & CAPTURE_ECC_ECE);
|
||||
|
||||
printf("Memory Error Attributes Capture:\n");
|
||||
printf(" Data Beat Number: %d\n",
|
||||
(ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >>
|
||||
ECC_CAPT_ATTR_BNUM_SHIFT);
|
||||
printf(" Transaction Size: %d\n",
|
||||
(ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >>
|
||||
ECC_CAPT_ATTR_TSIZ_SHIFT);
|
||||
printf(" Transaction Source: %d\n",
|
||||
(ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >>
|
||||
ECC_CAPT_ATTR_TSRC_SHIFT);
|
||||
printf(" Transaction Type: %d\n",
|
||||
(ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >>
|
||||
ECC_CAPT_ATTR_TTYP_SHIFT);
|
||||
printf(" Error Information Valid: %d\n\n",
|
||||
ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
|
||||
}
|
||||
|
||||
int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||
volatile ddr83xx_t *ddr = &immap->ddr;
|
||||
volatile u32 val;
|
||||
u64 *addr;
|
||||
u32 count;
|
||||
register u64 *i;
|
||||
u32 ret[2];
|
||||
u32 pattern[2];
|
||||
u32 writeback[2];
|
||||
|
||||
/* The pattern is written into memory to generate error */
|
||||
pattern[0] = 0xfedcba98UL;
|
||||
pattern[1] = 0x76543210UL;
|
||||
|
||||
/* After injecting error, re-initialize the memory with the value */
|
||||
writeback[0] = 0x01234567UL;
|
||||
writeback[1] = 0x89abcdefUL;
|
||||
|
||||
if (argc > 4) {
|
||||
printf("Usage:\n%s\n", cmdtp->usage);
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (argc == 2) {
|
||||
if (strcmp(argv[1], "status") == 0) {
|
||||
ecc_print_status();
|
||||
return 0;
|
||||
} else if (strcmp(argv[1], "captureclear") == 0) {
|
||||
ddr->capture_address = 0;
|
||||
ddr->capture_data_hi = 0;
|
||||
ddr->capture_data_lo = 0;
|
||||
ddr->capture_ecc = 0;
|
||||
ddr->capture_attributes = 0;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
if (argc == 3) {
|
||||
if (strcmp(argv[1], "sbecnt") == 0) {
|
||||
val = simple_strtoul(argv[2], NULL, 10);
|
||||
if (val > 255) {
|
||||
printf("Incorrect Counter value, "
|
||||
"should be 0..255\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
|
||||
val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
|
||||
|
||||
ddr->err_sbe = val;
|
||||
return 0;
|
||||
} else if (strcmp(argv[1], "sbethr") == 0) {
|
||||
val = simple_strtoul(argv[2], NULL, 10);
|
||||
if (val > 255) {
|
||||
printf("Incorrect Counter value, "
|
||||
"should be 0..255\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
val = (val << ECC_ERROR_MAN_SBET_SHIFT);
|
||||
val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
|
||||
|
||||
ddr->err_sbe = val;
|
||||
return 0;
|
||||
} else if (strcmp(argv[1], "errdisable") == 0) {
|
||||
val = ddr->err_disable;
|
||||
|
||||
if (strcmp(argv[2], "+sbe") == 0) {
|
||||
val |= ECC_ERROR_DISABLE_SBED;
|
||||
} else if (strcmp(argv[2], "+mbe") == 0) {
|
||||
val |= ECC_ERROR_DISABLE_MBED;
|
||||
} else if (strcmp(argv[2], "+mse") == 0) {
|
||||
val |= ECC_ERROR_DISABLE_MSED;
|
||||
} else if (strcmp(argv[2], "+all") == 0) {
|
||||
val |= (ECC_ERROR_DISABLE_SBED |
|
||||
ECC_ERROR_DISABLE_MBED |
|
||||
ECC_ERROR_DISABLE_MSED);
|
||||
} else if (strcmp(argv[2], "-sbe") == 0) {
|
||||
val &= ~ECC_ERROR_DISABLE_SBED;
|
||||
} else if (strcmp(argv[2], "-mbe") == 0) {
|
||||
val &= ~ECC_ERROR_DISABLE_MBED;
|
||||
} else if (strcmp(argv[2], "-mse") == 0) {
|
||||
val &= ~ECC_ERROR_DISABLE_MSED;
|
||||
} else if (strcmp(argv[2], "-all") == 0) {
|
||||
val &= ~(ECC_ERROR_DISABLE_SBED |
|
||||
ECC_ERROR_DISABLE_MBED |
|
||||
ECC_ERROR_DISABLE_MSED);
|
||||
} else {
|
||||
printf("Incorrect err_disable field\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
ddr->err_disable = val;
|
||||
__asm__ __volatile__("sync");
|
||||
__asm__ __volatile__("isync");
|
||||
return 0;
|
||||
} else if (strcmp(argv[1], "errdetectclr") == 0) {
|
||||
val = ddr->err_detect;
|
||||
|
||||
if (strcmp(argv[2], "mme") == 0) {
|
||||
val |= ECC_ERROR_DETECT_MME;
|
||||
} else if (strcmp(argv[2], "sbe") == 0) {
|
||||
val |= ECC_ERROR_DETECT_SBE;
|
||||
} else if (strcmp(argv[2], "mbe") == 0) {
|
||||
val |= ECC_ERROR_DETECT_MBE;
|
||||
} else if (strcmp(argv[2], "mse") == 0) {
|
||||
val |= ECC_ERROR_DETECT_MSE;
|
||||
} else if (strcmp(argv[2], "all") == 0) {
|
||||
val |= (ECC_ERROR_DETECT_MME |
|
||||
ECC_ERROR_DETECT_MBE |
|
||||
ECC_ERROR_DETECT_SBE |
|
||||
ECC_ERROR_DETECT_MSE);
|
||||
} else {
|
||||
printf("Incorrect err_detect field\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
ddr->err_detect = val;
|
||||
return 0;
|
||||
} else if (strcmp(argv[1], "injectdatahi") == 0) {
|
||||
val = simple_strtoul(argv[2], NULL, 16);
|
||||
|
||||
ddr->data_err_inject_hi = val;
|
||||
return 0;
|
||||
} else if (strcmp(argv[1], "injectdatalo") == 0) {
|
||||
val = simple_strtoul(argv[2], NULL, 16);
|
||||
|
||||
ddr->data_err_inject_lo = val;
|
||||
return 0;
|
||||
} else if (strcmp(argv[1], "injectecc") == 0) {
|
||||
val = simple_strtoul(argv[2], NULL, 16);
|
||||
if (val > 0xff) {
|
||||
printf("Incorrect ECC inject mask, "
|
||||
"should be 0x00..0xff\n");
|
||||
return 1;
|
||||
}
|
||||
val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
|
||||
|
||||
ddr->ecc_err_inject = val;
|
||||
return 0;
|
||||
} else if (strcmp(argv[1], "inject") == 0) {
|
||||
val = ddr->ecc_err_inject;
|
||||
|
||||
if (strcmp(argv[2], "en") == 0)
|
||||
val |= ECC_ERR_INJECT_EIEN;
|
||||
else if (strcmp(argv[2], "dis") == 0)
|
||||
val &= ~ECC_ERR_INJECT_EIEN;
|
||||
else
|
||||
printf("Incorrect command\n");
|
||||
|
||||
ddr->ecc_err_inject = val;
|
||||
__asm__ __volatile__("sync");
|
||||
__asm__ __volatile__("isync");
|
||||
return 0;
|
||||
} else if (strcmp(argv[1], "mirror") == 0) {
|
||||
val = ddr->ecc_err_inject;
|
||||
|
||||
if (strcmp(argv[2], "en") == 0)
|
||||
val |= ECC_ERR_INJECT_EMB;
|
||||
else if (strcmp(argv[2], "dis") == 0)
|
||||
val &= ~ECC_ERR_INJECT_EMB;
|
||||
else
|
||||
printf("Incorrect command\n");
|
||||
|
||||
ddr->ecc_err_inject = val;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
if (argc == 4) {
|
||||
if (strcmp(argv[1], "testdw") == 0) {
|
||||
addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
|
||||
count = simple_strtoul(argv[3], NULL, 16);
|
||||
|
||||
if ((u32) addr % 8) {
|
||||
printf("Address not alligned on "
|
||||
"double word boundary\n");
|
||||
return 1;
|
||||
}
|
||||
disable_interrupts();
|
||||
|
||||
for (i = addr; i < addr + count; i++) {
|
||||
|
||||
/* enable injects */
|
||||
ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
|
||||
__asm__ __volatile__("sync");
|
||||
__asm__ __volatile__("isync");
|
||||
|
||||
/* write memory location injecting errors */
|
||||
ppcDWstore((u32 *) i, pattern);
|
||||
__asm__ __volatile__("sync");
|
||||
|
||||
/* disable injects */
|
||||
ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
|
||||
__asm__ __volatile__("sync");
|
||||
__asm__ __volatile__("isync");
|
||||
|
||||
/* read data, this generates ECC error */
|
||||
ppcDWload((u32 *) i, ret);
|
||||
__asm__ __volatile__("sync");
|
||||
|
||||
/* re-initialize memory, double word write the location again,
|
||||
* generates new ECC code this time */
|
||||
ppcDWstore((u32 *) i, writeback);
|
||||
__asm__ __volatile__("sync");
|
||||
}
|
||||
enable_interrupts();
|
||||
return 0;
|
||||
}
|
||||
if (strcmp(argv[1], "testword") == 0) {
|
||||
addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
|
||||
count = simple_strtoul(argv[3], NULL, 16);
|
||||
|
||||
if ((u32) addr % 8) {
|
||||
printf("Address not alligned on "
|
||||
"double word boundary\n");
|
||||
return 1;
|
||||
}
|
||||
disable_interrupts();
|
||||
|
||||
for (i = addr; i < addr + count; i++) {
|
||||
|
||||
/* enable injects */
|
||||
ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
|
||||
__asm__ __volatile__("sync");
|
||||
__asm__ __volatile__("isync");
|
||||
|
||||
/* write memory location injecting errors */
|
||||
*(u32 *) i = 0xfedcba98UL;
|
||||
__asm__ __volatile__("sync");
|
||||
|
||||
/* sub double word write,
|
||||
* bus will read-modify-write,
|
||||
* generates ECC error */
|
||||
*((u32 *) i + 1) = 0x76543210UL;
|
||||
__asm__ __volatile__("sync");
|
||||
|
||||
/* disable injects */
|
||||
ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
|
||||
__asm__ __volatile__("sync");
|
||||
__asm__ __volatile__("isync");
|
||||
|
||||
/* re-initialize memory,
|
||||
* double word write the location again,
|
||||
* generates new ECC code this time */
|
||||
ppcDWstore((u32 *) i, writeback);
|
||||
__asm__ __volatile__("sync");
|
||||
}
|
||||
enable_interrupts();
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
printf("Usage:\n%s\n", cmdtp->usage);
|
||||
return 1;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(ecc, 4, 0, do_ecc,
|
||||
"ecc - support for DDR ECC features\n",
|
||||
"status - print out status info\n"
|
||||
"ecc captureclear - clear capture regs data\n"
|
||||
"ecc sbecnt <val> - set Single-Bit Error counter\n"
|
||||
"ecc sbethr <val> - set Single-Bit Threshold\n"
|
||||
"ecc errdisable <flag> - clear/set disable Memory Error Disable, flag:\n"
|
||||
" [-|+]sbe - Single-Bit Error\n"
|
||||
" [-|+]mbe - Multiple-Bit Error\n"
|
||||
" [-|+]mse - Memory Select Error\n"
|
||||
" [-|+]all - all errors\n"
|
||||
"ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
|
||||
" mme - Multiple Memory Errors\n"
|
||||
" sbe - Single-Bit Error\n"
|
||||
" mbe - Multiple-Bit Error\n"
|
||||
" mse - Memory Select Error\n"
|
||||
" all - all errors\n"
|
||||
"ecc injectdatahi <hi> - set Memory Data Path Error Injection Mask High\n"
|
||||
"ecc injectdatalo <lo> - set Memory Data Path Error Injection Mask Low\n"
|
||||
"ecc injectecc <ecc> - set ECC Error Injection Mask\n"
|
||||
"ecc inject <en|dis> - enable/disable error injection\n"
|
||||
"ecc mirror <en|dis> - enable/disable mirror byte\n"
|
||||
"ecc testdw <addr> <cnt> - test mem region with double word access:\n"
|
||||
" - enables injects\n"
|
||||
" - writes pattern injecting errors with double word access\n"
|
||||
" - disables injects\n"
|
||||
" - reads pattern back with double word access, generates error\n"
|
||||
" - re-inits memory\n"
|
||||
"ecc testword <addr> <cnt> - test mem region with word access:\n"
|
||||
" - enables injects\n"
|
||||
" - writes pattern injecting errors with word access\n"
|
||||
" - writes pattern with word access, generates error\n"
|
||||
" - disables injects\n" " - re-inits memory");
|
||||
#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
|
||||
|
||||
#if (defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)) \
|
||||
&& defined(CONFIG_OF_BOARD_SETUP)
|
||||
|
||||
|
@ -681,11 +304,11 @@ ft_board_setup(void *blob, bd_t *bd)
|
|||
int nodeoffset;
|
||||
int tmp[2];
|
||||
|
||||
nodeoffset = fdt_path_offset (fdt, "/memory");
|
||||
nodeoffset = fdt_find_node_by_path(blob, "/memory");
|
||||
if (nodeoffset >= 0) {
|
||||
tmp[0] = cpu_to_be32(bd->bi_memstart);
|
||||
tmp[1] = cpu_to_be32(bd->bi_memsize);
|
||||
fdt_setprop(fdt, nodeoffset, "reg", tmp, sizeof(tmp));
|
||||
fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp));
|
||||
}
|
||||
#else
|
||||
u32 *p;
|
||||
|
|
|
@ -20,8 +20,7 @@
|
|||
#include <i2c.h>
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
#include <ft_build.h>
|
||||
#endif
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
#elif defined(CONFIG_OF_LIBFDT)
|
||||
#include <libfdt.h>
|
||||
#include <libfdt_env.h>
|
||||
#endif
|
||||
|
@ -207,7 +206,7 @@ void pci_init_board(void)
|
|||
|
||||
/* Switch temporarily to I2C bus #2 */
|
||||
orig_i2c_bus = i2c_get_bus_num();
|
||||
i2c_set_bus_num(1);
|
||||
i2c_set_bus_num(1);
|
||||
|
||||
val8 = 0;
|
||||
i2c_write(0x23, 0x6, 1, &val8, 1);
|
||||
|
@ -311,26 +310,25 @@ ft_pci_setup(void *blob, bd_t *bd)
|
|||
int err;
|
||||
int tmp[2];
|
||||
|
||||
nodeoffset = fdt_path_offset (fdt, "/" OF_SOC "/pci@8500");
|
||||
nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500");
|
||||
if (nodeoffset >= 0) {
|
||||
tmp[0] = cpu_to_be32(hose[0].first_busno);
|
||||
tmp[1] = cpu_to_be32(hose[0].last_busno);
|
||||
err = fdt_setprop(fdt, nodeoffset, "bus-range", tmp, sizeof(tmp));
|
||||
err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp));
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_OF_LIBFDT */
|
||||
#ifdef CONFIG_OF_FLAT_TREE
|
||||
#elif defined(CONFIG_OF_FLAT_TREE)
|
||||
void
|
||||
ft_pci_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
u32 *p;
|
||||
int len;
|
||||
u32 *p;
|
||||
int len;
|
||||
|
||||
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
|
||||
if (p != NULL) {
|
||||
p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
|
||||
if (p != NULL) {
|
||||
p[0] = hose[0].first_busno;
|
||||
p[1] = hose[0].last_busno;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_OF_FLAT_TREE */
|
||||
#endif /* CONFIG_PCI */
|
||||
|
|
|
@ -554,7 +554,6 @@ ft_soc_setup(void *blob, bd_t *bd)
|
|||
{
|
||||
u32 *p;
|
||||
int len;
|
||||
ulong data;
|
||||
|
||||
p = ft_get_prop(blob, "/" OF_SOC "/cpm@e0000000/brg-frequency", &len);
|
||||
|
||||
|
|
|
@ -47,3 +47,10 @@ void disable_8568mds_flash_write()
|
|||
|
||||
bcsr[9] &= ~(0x01);
|
||||
}
|
||||
|
||||
void enable_8568mds_qe_mdio()
|
||||
{
|
||||
u8 *bcsr = (u8 *)(CFG_BCSR);
|
||||
|
||||
bcsr[7] |= 0x01;
|
||||
}
|
||||
|
|
|
@ -95,5 +95,6 @@
|
|||
void enable_8568mds_duart(void);
|
||||
void enable_8568mds_flash_write(void);
|
||||
void disable_8568mds_flash_write(void);
|
||||
void enable_8568mds_qe_mdio(void);
|
||||
|
||||
#endif /* __BCSR_H_ */
|
||||
|
|
|
@ -143,54 +143,42 @@ tlb1_entry:
|
|||
.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
|
||||
|
||||
/*
|
||||
* TLBe 2: 256M Non-cacheable, guarded
|
||||
* 0x80000000 256M PCI1 MEM
|
||||
* TLBe 2: 1G Non-cacheable, guarded
|
||||
* 0x80000000 512M PCI1 MEM
|
||||
* 0xa0000000 512M PCIe MEM
|
||||
*/
|
||||
.long TLB1_MAS0(1, 2, 0)
|
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
|
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
|
||||
|
||||
/*
|
||||
* TLBe 3: 256M Non-cacheable, guarded
|
||||
* 0xa0000000 256M PCIe Mem
|
||||
*/
|
||||
.long TLB1_MAS0(1, 3, 0)
|
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
|
||||
|
||||
/*
|
||||
* TLBe 4: Reserved for future usage
|
||||
*/
|
||||
|
||||
/*
|
||||
* TLBe 5: 64M Non-cacheable, guarded
|
||||
* TLBe 3: 64M Non-cacheable, guarded
|
||||
* 0xe000_0000 1M CCSRBAR
|
||||
* 0xe200_0000 8M PCI1 IO
|
||||
* 0xe280_0000 8M PCIe IO
|
||||
*/
|
||||
.long TLB1_MAS0(1, 5, 0)
|
||||
.long TLB1_MAS0(1, 3, 0)
|
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
|
||||
|
||||
/*
|
||||
* TLBe 6: 64M Cacheable, non-guarded
|
||||
* TLBe 4: 64M Cacheable, non-guarded
|
||||
* 0xf000_0000 64M LBC SDRAM
|
||||
*/
|
||||
.long TLB1_MAS0(1, 6, 0)
|
||||
.long TLB1_MAS0(1, 4, 0)
|
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
|
||||
|
||||
/*
|
||||
* TLBe 7: 256K Non-cacheable, guarded
|
||||
* TLBe 5: 256K Non-cacheable, guarded
|
||||
* 0xf8000000 32K BCSR
|
||||
* 0xf8008000 32K PIB (CS4)
|
||||
* 0xf8010000 32K PIB (CS5)
|
||||
*/
|
||||
.long TLB1_MAS0(1, 7, 0)
|
||||
.long TLB1_MAS0(1, 5, 0)
|
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR_BASE), 0,0,0,0,1,0,1,0)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR_BASE), 0,0,0,0,0,1,0,1,0,1)
|
||||
|
@ -202,12 +190,12 @@ tlb1_entry:
|
|||
* LAW(Local Access Window) configuration:
|
||||
*
|
||||
*0) 0x0000_0000 0x7fff_ffff DDR 2G
|
||||
*1) 0x8000_0000 0x9fff_ffff PCI1 MEM 256MB
|
||||
*2) 0xa000_0000 0xbfff_ffff PCIe MEM 256MB
|
||||
*5) 0xc000_0000 0xdfff_ffff SRIO 256MB
|
||||
*1) 0x8000_0000 0x9fff_ffff PCI1 MEM 512MB
|
||||
*2) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB
|
||||
*-) 0xe000_0000 0xe00f_ffff CCSR 1M
|
||||
*3) 0xe200_0000 0xe27f_ffff PCI1 I/O 8M
|
||||
*4) 0xe280_0000 0xe2ff_ffff PCIe I/0 8M
|
||||
*4) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M
|
||||
*5) 0xc000_0000 0xdfff_ffff SRIO 512MB
|
||||
*6.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB
|
||||
*6.b) 0xf800_0000 0xf800_7fff BCSR 32KB
|
||||
*6.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB
|
||||
|
@ -226,20 +214,20 @@ tlb1_entry:
|
|||
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
|
||||
|
||||
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
|
||||
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
|
||||
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
|
||||
|
||||
#define LAWBAR2 ((CFG_PEX_MEM_BASE>>12) & 0xfffff)
|
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_256M))
|
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M))
|
||||
|
||||
#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
|
||||
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
|
||||
|
||||
#define LAWBAR4 ((CFG_PEX_IO_PHYS>>12) & 0xfffff)
|
||||
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M))
|
||||
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_8M))
|
||||
|
||||
|
||||
#define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff)
|
||||
#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_256M))
|
||||
#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
|
||||
|
||||
/* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */
|
||||
#define LAWBAR6 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
|
||||
|
|
|
@ -27,9 +27,66 @@
|
|||
#include <asm/processor.h>
|
||||
#include <asm/immap_85xx.h>
|
||||
#include <spd.h>
|
||||
#include <i2c.h>
|
||||
#include <ioports.h>
|
||||
|
||||
#include "bcsr.h"
|
||||
|
||||
const qe_iop_conf_t qe_iop_conf_tab[] = {
|
||||
/* GETH1 */
|
||||
{4, 10, 1, 0, 2}, /* TxD0 */
|
||||
{4, 9, 1, 0, 2}, /* TxD1 */
|
||||
{4, 8, 1, 0, 2}, /* TxD2 */
|
||||
{4, 7, 1, 0, 2}, /* TxD3 */
|
||||
{4, 23, 1, 0, 2}, /* TxD4 */
|
||||
{4, 22, 1, 0, 2}, /* TxD5 */
|
||||
{4, 21, 1, 0, 2}, /* TxD6 */
|
||||
{4, 20, 1, 0, 2}, /* TxD7 */
|
||||
{4, 15, 2, 0, 2}, /* RxD0 */
|
||||
{4, 14, 2, 0, 2}, /* RxD1 */
|
||||
{4, 13, 2, 0, 2}, /* RxD2 */
|
||||
{4, 12, 2, 0, 2}, /* RxD3 */
|
||||
{4, 29, 2, 0, 2}, /* RxD4 */
|
||||
{4, 28, 2, 0, 2}, /* RxD5 */
|
||||
{4, 27, 2, 0, 2}, /* RxD6 */
|
||||
{4, 26, 2, 0, 2}, /* RxD7 */
|
||||
{4, 11, 1, 0, 2}, /* TX_EN */
|
||||
{4, 24, 1, 0, 2}, /* TX_ER */
|
||||
{4, 16, 2, 0, 2}, /* RX_DV */
|
||||
{4, 30, 2, 0, 2}, /* RX_ER */
|
||||
{4, 17, 2, 0, 2}, /* RX_CLK */
|
||||
{4, 19, 1, 0, 2}, /* GTX_CLK */
|
||||
{1, 31, 2, 0, 3}, /* GTX125 */
|
||||
|
||||
/* GETH2 */
|
||||
{5, 10, 1, 0, 2}, /* TxD0 */
|
||||
{5, 9, 1, 0, 2}, /* TxD1 */
|
||||
{5, 8, 1, 0, 2}, /* TxD2 */
|
||||
{5, 7, 1, 0, 2}, /* TxD3 */
|
||||
{5, 23, 1, 0, 2}, /* TxD4 */
|
||||
{5, 22, 1, 0, 2}, /* TxD5 */
|
||||
{5, 21, 1, 0, 2}, /* TxD6 */
|
||||
{5, 20, 1, 0, 2}, /* TxD7 */
|
||||
{5, 15, 2, 0, 2}, /* RxD0 */
|
||||
{5, 14, 2, 0, 2}, /* RxD1 */
|
||||
{5, 13, 2, 0, 2}, /* RxD2 */
|
||||
{5, 12, 2, 0, 2}, /* RxD3 */
|
||||
{5, 29, 2, 0, 2}, /* RxD4 */
|
||||
{5, 28, 2, 0, 2}, /* RxD5 */
|
||||
{5, 27, 2, 0, 3}, /* RxD6 */
|
||||
{5, 26, 2, 0, 2}, /* RxD7 */
|
||||
{5, 11, 1, 0, 2}, /* TX_EN */
|
||||
{5, 24, 1, 0, 2}, /* TX_ER */
|
||||
{5, 16, 2, 0, 2}, /* RX_DV */
|
||||
{5, 30, 2, 0, 2}, /* RX_ER */
|
||||
{5, 17, 2, 0, 2}, /* RX_CLK */
|
||||
{5, 19, 1, 0, 2}, /* GTX_CLK */
|
||||
{1, 31, 2, 0, 3}, /* GTX125 */
|
||||
{4, 6, 3, 0, 2}, /* MDIO */
|
||||
{4, 5, 1, 0, 2}, /* MDC */
|
||||
{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
|
||||
};
|
||||
|
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
||||
extern void ddr_enable_ecc(unsigned int dram_size);
|
||||
|
@ -49,6 +106,18 @@ int board_early_init_f (void)
|
|||
|
||||
enable_8568mds_duart();
|
||||
enable_8568mds_flash_write();
|
||||
#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
|
||||
enable_8568mds_qe_mdio();
|
||||
#endif
|
||||
|
||||
#ifdef CFG_I2C2_OFFSET
|
||||
/* Enable I2C2_SCL and I2C2_SDA */
|
||||
volatile struct par_io *port_c;
|
||||
port_c = (struct par_io*)(CFG_IMMR + 0xe0140);
|
||||
port_c->cpdir2 |= 0x0f000000;
|
||||
port_c->cppar2 &= ~0x0f000000;
|
||||
port_c->cppar2 |= 0x0a000000;
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -269,20 +338,62 @@ static struct pci_config_table pci_mpc8568mds_config_table[] = {
|
|||
#endif
|
||||
|
||||
static struct pci_controller hose[] = {
|
||||
{
|
||||
#ifndef CONFIG_PCI_PNP
|
||||
{ config_table: pci_mpc8568mds_config_table,},
|
||||
#endif
|
||||
#ifdef CONFIG_MPC85XX_PCI2
|
||||
{},
|
||||
config_table: pci_mpc8568mds_config_table,
|
||||
#endif
|
||||
}
|
||||
};
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
/*
|
||||
* pib_init() -- Initialize the PCA9555 IO expander on the PIB board
|
||||
*/
|
||||
void
|
||||
pib_init(void)
|
||||
{
|
||||
u8 val8, orig_i2c_bus;
|
||||
/*
|
||||
* Assign PIB PMC2/3 to PCI bus
|
||||
*/
|
||||
|
||||
/*switch temporarily to I2C bus #2 */
|
||||
orig_i2c_bus = i2c_get_bus_num();
|
||||
i2c_set_bus_num(1);
|
||||
|
||||
val8 = 0x00;
|
||||
i2c_write(0x23, 0x6, 1, &val8, 1);
|
||||
i2c_write(0x23, 0x7, 1, &val8, 1);
|
||||
val8 = 0xff;
|
||||
i2c_write(0x23, 0x2, 1, &val8, 1);
|
||||
i2c_write(0x23, 0x3, 1, &val8, 1);
|
||||
|
||||
val8 = 0x00;
|
||||
i2c_write(0x26, 0x6, 1, &val8, 1);
|
||||
val8 = 0x34;
|
||||
i2c_write(0x26, 0x7, 1, &val8, 1);
|
||||
val8 = 0xf9;
|
||||
i2c_write(0x26, 0x2, 1, &val8, 1);
|
||||
val8 = 0xff;
|
||||
i2c_write(0x26, 0x3, 1, &val8, 1);
|
||||
|
||||
val8 = 0x00;
|
||||
i2c_write(0x27, 0x6, 1, &val8, 1);
|
||||
i2c_write(0x27, 0x7, 1, &val8, 1);
|
||||
val8 = 0xff;
|
||||
i2c_write(0x27, 0x2, 1, &val8, 1);
|
||||
val8 = 0xef;
|
||||
i2c_write(0x27, 0x3, 1, &val8, 1);
|
||||
|
||||
asm("eieio");
|
||||
}
|
||||
|
||||
void
|
||||
pci_init_board(void)
|
||||
{
|
||||
#ifdef CONFIG_PCI
|
||||
pci_mpc85xx_init(&hose);
|
||||
pib_init();
|
||||
pci_mpc85xx_init(hose);
|
||||
#endif
|
||||
}
|
||||
|
|
|
@ -268,8 +268,8 @@ void pci_init_board(void)
|
|||
* Activate ULI1575 legacy chip by performing a fake
|
||||
* memory access. Needed to make ULI RTC work.
|
||||
*/
|
||||
in_be32((unsigned *) CFG_PCI1_MEM_BASE
|
||||
+ CFG_PCI1_MEM_SIZE - 0x1000000);
|
||||
in_be32((unsigned *) ((char *)(CFG_PCI1_MEM_BASE
|
||||
+ CFG_PCI1_MEM_SIZE - 0x1000000)));
|
||||
|
||||
} else {
|
||||
puts("PCI-EXPRESS 1: Disabled\n");
|
||||
|
|
528
board/netstal/common/flash.c
Normal file
528
board/netstal/common/flash.c
Normal file
|
@ -0,0 +1,528 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* Modified 4/5/2001
|
||||
* Wait for completion of each sector erase command issued
|
||||
* 4/5/2001
|
||||
* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
|
||||
*
|
||||
* Modified 6/6/2007
|
||||
* Added isync
|
||||
* Niklaus Giger, Netstal Maschinen, niklaus.giger@netstal.com
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <ppc4xx.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
#if CFG_MAX_FLASH_BANKS != 1
|
||||
#error "CFG_MAX_FLASH_BANKS must be 1"
|
||||
#endif
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
static ulong flash_get_size (vu_long * addr, flash_info_t * info);
|
||||
static int write_word (flash_info_t * info, ulong dest, ulong data);
|
||||
static void flash_get_offsets (ulong base, flash_info_t * info);
|
||||
|
||||
#define ADDR0 0x5555
|
||||
#define ADDR1 0x2aaa
|
||||
#define FLASH_WORD_SIZE unsigned char
|
||||
|
||||
/*-----------------------------------------------------------------------*/
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
unsigned long size_b0;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
flash_info[0].flash_id = FLASH_UNKNOWN;
|
||||
|
||||
/* Static FLASH Bank configuration here - FIXME XXX */
|
||||
|
||||
size_b0 = flash_get_size ((vu_long *) FLASH_BASE0_PRELIM,
|
||||
&flash_info[0]);
|
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
|
||||
printf ("## Unknown FLASH on Bank 0- Size=0x%08lx=%ld MB\n",
|
||||
size_b0, size_b0 << 20);
|
||||
}
|
||||
|
||||
/* Only one bank */
|
||||
/* Setup offsets */
|
||||
flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
|
||||
|
||||
/* Monitor protection ON by default */
|
||||
(void) flash_protect (FLAG_PROTECT_SET,
|
||||
FLASH_BASE0_PRELIM,
|
||||
FLASH_BASE0_PRELIM + monitor_flash_len - 1,
|
||||
&flash_info[0]);
|
||||
flash_info[0].size = size_b0;
|
||||
|
||||
return size_b0;
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------*/
|
||||
/*
|
||||
* This implementation assumes that the flash chips are uniform sector
|
||||
* devices. This is true for all likely flash devices on a HCUx.
|
||||
*/
|
||||
static void flash_get_offsets (ulong base, flash_info_t * info)
|
||||
{
|
||||
unsigned idx;
|
||||
unsigned long sector_size = info->size / info->sector_count;
|
||||
|
||||
for (idx = 0; idx < info->sector_count; idx += 1) {
|
||||
info->start[idx] = base + (idx * sector_size);
|
||||
}
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------*/
|
||||
void flash_print_info (flash_info_t * info)
|
||||
{
|
||||
int i;
|
||||
int k;
|
||||
int size;
|
||||
int erased;
|
||||
volatile unsigned long *flash;
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("missing or unknown FLASH type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case FLASH_MAN_AMD:
|
||||
printf ("AMD ");
|
||||
break;
|
||||
case FLASH_MAN_FUJ:
|
||||
printf ("FUJITSU ");
|
||||
break;
|
||||
case FLASH_MAN_SST:
|
||||
printf ("SST ");
|
||||
break;
|
||||
case FLASH_MAN_STM:
|
||||
printf ("ST Micro ");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Vendor ");
|
||||
break;
|
||||
}
|
||||
|
||||
/* (Reduced table of only parts expected in HCUx boards.) */
|
||||
switch (info->flash_id) {
|
||||
case FLASH_MAN_AMD | FLASH_AM040:
|
||||
printf ("AM29F040 (512 Kbit, uniform sector size)\n");
|
||||
break;
|
||||
case FLASH_MAN_STM | FLASH_AM040:
|
||||
printf ("MM29W040W (512 Kbit, uniform sector size)\n");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Chip Type\n");
|
||||
break;
|
||||
}
|
||||
|
||||
printf (" Size: %ld KB in %d Sectors\n",
|
||||
info->size >> 10, info->sector_count);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i = 0; i < info->sector_count; ++i) {
|
||||
/*
|
||||
* Check if whole sector is erased
|
||||
*/
|
||||
if (i != (info->sector_count - 1))
|
||||
size = info->start[i + 1] - info->start[i];
|
||||
else
|
||||
size = info->start[0] + info->size - info->start[i];
|
||||
erased = 1;
|
||||
flash = (volatile unsigned long *) info->start[i];
|
||||
size = size >> 2; /* divide by 4 for longword access */
|
||||
for (k = 0; k < size; k++) {
|
||||
if (*flash++ != 0xffffffff) {
|
||||
erased = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if ((i % 5) == 0)
|
||||
printf ("\n ");
|
||||
printf (" %08lX%s%s",
|
||||
info->start[i],
|
||||
erased ? " E" : " ", info->protect[i] ? "RO " : " "
|
||||
);
|
||||
}
|
||||
printf ("\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH!
|
||||
*/
|
||||
static ulong flash_get_size (vu_long * addr, flash_info_t * info)
|
||||
{
|
||||
short i;
|
||||
FLASH_WORD_SIZE value;
|
||||
ulong base = (ulong) addr;
|
||||
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
|
||||
|
||||
/* Write auto select command: read Manufacturer ID */
|
||||
asm("isync");
|
||||
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
|
||||
asm("isync");
|
||||
addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
|
||||
asm("isync");
|
||||
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090;
|
||||
asm("isync");
|
||||
|
||||
value = addr2[0];
|
||||
asm("isync");
|
||||
|
||||
switch (value) {
|
||||
case (FLASH_WORD_SIZE) AMD_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_AMD;
|
||||
break;
|
||||
case (FLASH_WORD_SIZE) FUJ_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_FUJ;
|
||||
break;
|
||||
case (FLASH_WORD_SIZE) SST_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_SST;
|
||||
break;
|
||||
case (FLASH_WORD_SIZE)STM_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_STM;
|
||||
break;
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
printf("Unknown flash manufacturer code: 0x%x at %p\n",
|
||||
value, addr);
|
||||
addr2[ADDR0] = (FLASH_WORD_SIZE) 0;
|
||||
return (0); /* no or unknown flash */
|
||||
}
|
||||
|
||||
value = addr2[1]; /* device ID */
|
||||
|
||||
switch (value) {
|
||||
case (FLASH_WORD_SIZE) AMD_ID_F040B:
|
||||
info->flash_id += FLASH_AM040;
|
||||
info->sector_count = 8;
|
||||
info->size = 0x0080000; /* => 512 ko */
|
||||
break;
|
||||
case (FLASH_WORD_SIZE) AMD_ID_LV040B:
|
||||
info->flash_id += FLASH_AM040;
|
||||
info->sector_count = 8;
|
||||
info->size = 0x0080000; /* => 512 ko */
|
||||
break;
|
||||
case (FLASH_WORD_SIZE)STM_ID_M29W040B: /* most likele HCU5 chip */
|
||||
info->flash_id += FLASH_AM040;
|
||||
info->sector_count = 8;
|
||||
info->size = 0x0080000; /* => 512 ko */
|
||||
break;
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
return (0); /* => no or unknown flash */
|
||||
|
||||
}
|
||||
|
||||
/* Calculate the sector offsets (Use HCUx Optimized code). */
|
||||
flash_get_offsets(base, info);
|
||||
|
||||
/* check for protected sectors */
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
/* read sector protection at sector address,
|
||||
*(A7 .. A0) = 0x02
|
||||
* D0 = 1 if protected
|
||||
*/
|
||||
addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
|
||||
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
|
||||
info->protect[i] = 0;
|
||||
else
|
||||
info->protect[i] = addr2[2] & 1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Prevent writes to uninitialized FLASH.
|
||||
*/
|
||||
if (info->flash_id != FLASH_UNKNOWN) {
|
||||
addr2 = (FLASH_WORD_SIZE *) info->start[0];
|
||||
*addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
|
||||
}
|
||||
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
int wait_for_DQ7 (flash_info_t * info, int sect)
|
||||
{
|
||||
ulong start, now, last;
|
||||
volatile FLASH_WORD_SIZE *addr =
|
||||
(FLASH_WORD_SIZE *) (info->start[sect]);
|
||||
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
|
||||
(FLASH_WORD_SIZE) 0x00800080) {
|
||||
if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
return -1;
|
||||
}
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
putc ('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------*/
|
||||
|
||||
int flash_erase (flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
|
||||
volatile FLASH_WORD_SIZE *addr2;
|
||||
int flag, prot, sect, l_sect;
|
||||
int i;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("- missing\n");
|
||||
} else {
|
||||
printf ("- no sectors to erase\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("Can't erase unknown flash type - aborted\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors not erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
l_sect = -1;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts ();
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect <= s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
|
||||
printf ("Erasing sector %p\n", addr2); /* CLH */
|
||||
|
||||
if ((info->flash_id & FLASH_VENDMASK) ==
|
||||
FLASH_MAN_SST) {
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
|
||||
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
|
||||
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
|
||||
/* block erase */
|
||||
addr2[0] = (FLASH_WORD_SIZE) 0x00500050;
|
||||
for (i = 0; i < 50; i++) udelay (1000);
|
||||
} else {
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
|
||||
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080;
|
||||
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
|
||||
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
|
||||
/* sector erase */
|
||||
addr2[0] = (FLASH_WORD_SIZE) 0x00300030;
|
||||
}
|
||||
l_sect = sect;
|
||||
/*
|
||||
* Wait for each sector to complete, it's more
|
||||
* reliable. According to AMD Spec, you must
|
||||
* issue all erase commands within a specified
|
||||
* timeout. This has been seen to fail, especially
|
||||
* if printf()s are included (for debug)!!
|
||||
*/
|
||||
wait_for_DQ7 (info, sect);
|
||||
}
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts ();
|
||||
|
||||
/* wait at least 80us - let's wait 1 ms */
|
||||
udelay (1000);
|
||||
|
||||
#if 0
|
||||
/*
|
||||
* We wait for the last triggered sector
|
||||
*/
|
||||
if (l_sect < 0)
|
||||
goto DONE;
|
||||
wait_for_DQ7 (info, l_sect);
|
||||
|
||||
DONE:
|
||||
#endif
|
||||
/* reset to read mode */
|
||||
addr = (FLASH_WORD_SIZE *) info->start[0];
|
||||
addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
|
||||
|
||||
printf (" done\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
|
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong cp, wp, data;
|
||||
int i, l, rc;
|
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - wp) != 0) {
|
||||
data = 0;
|
||||
for (i = 0, cp = wp; i < l; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *) cp);
|
||||
}
|
||||
for (; i < 4 && cnt > 0; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
++cp;
|
||||
}
|
||||
for (; cnt == 0 && i < 4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *) cp);
|
||||
}
|
||||
|
||||
if ((rc = write_word (info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
while (cnt >= 4) {
|
||||
data = 0;
|
||||
for (i = 0; i < 4; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
}
|
||||
if ((rc = write_word (info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
cnt -= 4;
|
||||
}
|
||||
|
||||
if (cnt == 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
data = 0;
|
||||
for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
}
|
||||
for (; i < 4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *) cp);
|
||||
}
|
||||
|
||||
return (write_word (info, wp, data));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_word (flash_info_t * info, ulong dest, ulong data)
|
||||
{
|
||||
volatile FLASH_WORD_SIZE *addr2 =
|
||||
(FLASH_WORD_SIZE *) (info->start[0]);
|
||||
volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest;
|
||||
volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
|
||||
ulong start;
|
||||
int i;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*((volatile FLASH_WORD_SIZE *) dest) &
|
||||
(FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
|
||||
return (2);
|
||||
}
|
||||
|
||||
for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
|
||||
int flag;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts ();
|
||||
|
||||
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA;
|
||||
addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
|
||||
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0;
|
||||
|
||||
dest2[i] = data2[i];
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts ();
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
|
||||
(data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
|
||||
|
||||
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
41
board/netstal/common/nm_bsp.c
Normal file
41
board/netstal/common/nm_bsp.c
Normal file
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
*(C) Copyright 2005-2007 Netstal Maschinen AG
|
||||
* Niklaus Giger (Niklaus.Giger@netstal.com)
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
|
||||
#ifdef CONFIG_CMD_BSP
|
||||
/*
|
||||
* Command nm_bsp: Netstal Maschinen BSP specific command
|
||||
*/
|
||||
int nm_bsp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
printf("%s: flag %d, argc %d, argv[0] %s\n", __FUNCTION__,
|
||||
flag, argc, argv[0]);
|
||||
printf("Netstal Maschinen BSP specific command. None at the moment.\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
nm_bsp, 1, 1, nm_bsp,
|
||||
"nm_bsp - Netstal Maschinen BSP specific command. \n",
|
||||
"Help for Netstal Maschinen BSP specific command.\n"
|
||||
);
|
||||
#endif
|
49
board/netstal/hcu4/Makefile
Normal file
49
board/netstal/hcu4/Makefile
Normal file
|
@ -0,0 +1,49 @@
|
|||
#
|
||||
# (C) Copyright 2007 Netstal Maschinen AG
|
||||
# Niklaus Giger (ng@netstal.com)
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
vpath flash.c ../common
|
||||
COBJS = $(BOARD).o flash.o
|
||||
SOBJS =
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
59
board/netstal/hcu4/README.txt
Normal file
59
board/netstal/hcu4/README.txt
Normal file
|
@ -0,0 +1,59 @@
|
|||
HCU4 Configuration Details
|
||||
|
||||
Memory Bank 0 -- Flash chip
|
||||
---------------------------
|
||||
|
||||
0xfff00000 - 0xffffffff
|
||||
|
||||
The flash chip is really only 512Kbytes, but the high address bit of
|
||||
the 1Meg region is ignored, so the flash is replicated through the
|
||||
region. Thus, this is consistent with a flash base address 0xfff80000.
|
||||
|
||||
The placement at the end is to be consistent with reset behavior,
|
||||
where the processor itself initially uses this bus to load the branch
|
||||
vector and start running.
|
||||
|
||||
On-Chip Memory
|
||||
--------------
|
||||
|
||||
0xf4000000 - 0xf4000fff
|
||||
|
||||
The 405GPr includes a 4K on-chip memory that can be placed however
|
||||
software chooses. I choose to place the memory at this address, to
|
||||
keep it out of the cachable areas.
|
||||
|
||||
|
||||
Internal Peripherals
|
||||
--------------------
|
||||
|
||||
0xef600300 - 0xef6008ff
|
||||
|
||||
These are scattered various peripherals internal to the PPC405GPr
|
||||
chip.
|
||||
|
||||
Chip-Select 2: Flash Memory
|
||||
---------------------------
|
||||
|
||||
0x70000000
|
||||
|
||||
Chip-Select 3: CAN Interface
|
||||
----------------------------
|
||||
0x7800000
|
||||
|
||||
|
||||
Chip-Select 4: IMC-bus standard
|
||||
-------------------------------
|
||||
|
||||
Our IO-Bus (slow version)
|
||||
|
||||
|
||||
Chip-Select 5: IMC-bus fast (inactive)
|
||||
--------------------------------------
|
||||
|
||||
Our IO-Bus (fast, but not yet use)
|
||||
|
||||
|
||||
Memory Bank 1 -- SDRAM
|
||||
-------------------------------------
|
||||
|
||||
0x00000000 - 0x1ffffff # Default 32 MB
|
28
board/netstal/hcu4/config.mk
Normal file
28
board/netstal/hcu4/config.mk
Normal file
|
@ -0,0 +1,28 @@
|
|||
#
|
||||
# (C) Copyright 2005 Netstal Maschinen AG
|
||||
# Niklaus Giger (ng@netstal.com)
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# Netstal Maschinen AG: HCU4 boards
|
||||
#
|
||||
|
||||
TEXT_BASE = 0xFFFa0000
|
||||
|
||||
ifeq ($(debug),1)
|
||||
PLATFORM_CPPFLAGS += -DDEBUG -g
|
||||
endif
|
400
board/netstal/hcu4/hcu4.c
Normal file
400
board/netstal/hcu4/hcu4.c
Normal file
|
@ -0,0 +1,400 @@
|
|||
/*
|
||||
*(C) Copyright 2005-2007 Netstal Maschinen AG
|
||||
* Niklaus Giger (Niklaus.Giger@netstal.com)
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <ppc4xx.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm-ppc/u-boot.h>
|
||||
#include "../common/nm_bsp.c"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define HCU_MACH_VERSIONS_REGISTER (0x7C000000 + 0xF00000)
|
||||
|
||||
#define SDRAM_LEN 32*1024*1024 /* 32 MB -RAM */
|
||||
|
||||
#define DO_UGLY_SDRAM_WORKAROUND
|
||||
|
||||
enum {
|
||||
/* HW_GENERATION_HCU wird nicht mehr unterstuetzt */
|
||||
HW_GENERATION_HCU2 = 0x10,
|
||||
HW_GENERATION_HCU3 = 0x10,
|
||||
HW_GENERATION_HCU4 = 0x20,
|
||||
HW_GENERATION_MCU = 0x08,
|
||||
HW_GENERATION_MCU20 = 0x0a,
|
||||
HW_GENERATION_MCU25 = 0x09,
|
||||
};
|
||||
|
||||
void sysLedSet(u32 value);
|
||||
long int spd_sdram(int(read_spd)(uint addr));
|
||||
|
||||
#ifdef CONFIG_SPD_EEPROM
|
||||
#define DEBUG
|
||||
#endif
|
||||
|
||||
#if defined(DEBUG)
|
||||
void show_sdram_registers(void);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This function is run very early, out of flash, and before devices are
|
||||
* initialized. It is called by lib_ppc/board.c:board_init_f by virtue
|
||||
* of being in the init_sequence array.
|
||||
*
|
||||
* The SDRAM has been initialized already -- start.S:start called
|
||||
* init.S:init_sdram early on -- but it is not yet being used for
|
||||
* anything, not even stack. So be careful.
|
||||
*/
|
||||
|
||||
#define CPC0_CR0 0xb1 /* Chip control register 0 */
|
||||
#define CPC0_CR1 0xb2 /* Chip control register 1 */
|
||||
/* Attention: If you want 1 microsecs times from the external oscillator
|
||||
* use 0x00804051. But this causes problems with u-boot and linux!
|
||||
*/
|
||||
#define CPC0_CR1_VALUE 0x00004051
|
||||
#define CPC0_ECR 0xaa /* Edge condition register */
|
||||
#define EBC0_CFG 0x23 /* External Peripheral Control Register */
|
||||
#define CPC0_EIRR 0xb6 /* External Interrupt Register */
|
||||
|
||||
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
/*-------------------------------------------------------------------+
|
||||
| Interrupt controller setup for the HCU4 board.
|
||||
| Note: IRQ 0-15 405GP internally generated; high; level sensitive
|
||||
| IRQ 16 405GP internally generated; low; level sensitive
|
||||
| IRQ 17-24 RESERVED/UNUSED
|
||||
| IRQ 31 (EXT IRQ 6) (unused)
|
||||
+-------------------------------------------------------------------*/
|
||||
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
|
||||
mtdcr (uicer, 0x00000000); /* disable all ints */
|
||||
mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
|
||||
mtdcr (uicpr, 0xFFFFFF87); /* set int polarities */
|
||||
mtdcr (uictr, 0x10000000); /* set int trigger levels */
|
||||
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
|
||||
|
||||
mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
|
||||
mtdcr(CPC0_ECR, 0x60606000);
|
||||
mtdcr(CPC0_EIRR, 0x7c000000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_BOARD_PRE_INIT
|
||||
int board_pre_init (void)
|
||||
{
|
||||
return board_early_init_f ();
|
||||
}
|
||||
#endif
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
unsigned int j;
|
||||
u16 *boardVersReg = (u16 *) HCU_MACH_VERSIONS_REGISTER;
|
||||
u16 generation = *boardVersReg & 0xf0;
|
||||
u16 index = *boardVersReg & 0x0f;
|
||||
|
||||
/* Force /RTS to active. The board it not wired quite
|
||||
correctly to use cts/rtc flow control, so just force the
|
||||
/RST active and forget about it. */
|
||||
writeb (readb (0xef600404) | 0x03, 0xef600404);
|
||||
printf ("\nNetstal Maschinen AG ");
|
||||
if (generation == HW_GENERATION_HCU3)
|
||||
printf ("HCU3: index %d\n\n", index);
|
||||
else if (generation == HW_GENERATION_HCU4)
|
||||
printf ("HCU4: index %d\n\n", index);
|
||||
/* GPIO here noch nicht richtig initialisert !!! */
|
||||
sysLedSet(0);
|
||||
for (j = 0; j < 7; j++) {
|
||||
sysLedSet(1 << j);
|
||||
udelay(50 * 1000);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 sysLedGet(void)
|
||||
{
|
||||
return (~((*(u32 *)GPIO0_OR)) >> 23) & 0xff;
|
||||
}
|
||||
|
||||
void sysLedSet(u32 value /* value to place in LEDs */)
|
||||
{
|
||||
u32 tmp = ~value;
|
||||
u32 *ledReg;
|
||||
|
||||
tmp = (tmp << 23) | 0x7FFFFF;
|
||||
ledReg = (u32 *)GPIO0_OR;
|
||||
*ledReg = tmp;
|
||||
}
|
||||
|
||||
/*
|
||||
* sdram_init - Dummy implementation for start.S, spd_sdram or initdram
|
||||
* used for HCUx
|
||||
*/
|
||||
void sdram_init(void)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
#if defined(DEBUG)
|
||||
void show_sdram_registers(void)
|
||||
{
|
||||
u32 value;
|
||||
|
||||
printf ("SDRAM Controller Registers --\n");
|
||||
mfsdram(mem_mcopt1, value);
|
||||
printf (" SDRAM0_CFG : 0x%08x\n", value);
|
||||
mfsdram(mem_status, value);
|
||||
printf (" SDRAM0_STATUS: 0x%08x\n", value);
|
||||
mfsdram(mem_mb0cf, value);
|
||||
printf (" SDRAM0_B0CR : 0x%08x\n", value);
|
||||
mfsdram(mem_mb1cf, value);
|
||||
printf (" SDRAM0_B1CR : 0x%08x\n", value);
|
||||
mfsdram(mem_sdtr1, value);
|
||||
printf (" SDRAM0_TR : 0x%08x\n", value);
|
||||
mfsdram(mem_rtr, value);
|
||||
printf (" SDRAM0_RTR : 0x%08x\n", value);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* this is even after checkboard. It returns the size of the SDRAM
|
||||
* that we have installed. This function is called by board_init_f
|
||||
* in lib_ppc/board.c to initialize the memory and return what I
|
||||
* found. These are default value, which will be overridden later.
|
||||
*/
|
||||
|
||||
long int fixed_hcu4_sdram (int board_type)
|
||||
{
|
||||
#ifdef DEBUG
|
||||
printf (__FUNCTION__);
|
||||
#endif
|
||||
/* disable memory controller */
|
||||
mtdcr (memcfga, mem_mcopt1);
|
||||
mtdcr (memcfgd, 0x00000000);
|
||||
|
||||
udelay (500);
|
||||
|
||||
/* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
|
||||
mtdcr (memcfga, mem_besra);
|
||||
mtdcr (memcfgd, 0xffffffff);
|
||||
|
||||
/* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
|
||||
mtdcr (memcfga, mem_besrb);
|
||||
mtdcr (memcfgd, 0xffffffff);
|
||||
|
||||
/* Clear SDRAM0_ECCCFG (disable ECC) */
|
||||
mtdcr (memcfga, mem_ecccf);
|
||||
mtdcr (memcfgd, 0x00000000);
|
||||
|
||||
/* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
|
||||
mtdcr (memcfga, mem_eccerr);
|
||||
mtdcr (memcfgd, 0xffffffff);
|
||||
|
||||
/* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2
|
||||
* TODO ngngng
|
||||
*/
|
||||
mtdcr (memcfga, mem_sdtr1);
|
||||
mtdcr (memcfgd, 0x008a4015);
|
||||
|
||||
/* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1
|
||||
* TODO ngngng
|
||||
*/
|
||||
mtdcr (memcfga, mem_mb0cf);
|
||||
mtdcr (memcfgd, 0x00062001);
|
||||
|
||||
/* refresh timer = 0x400 */
|
||||
mtdcr (memcfga, mem_rtr);
|
||||
mtdcr (memcfgd, 0x04000000);
|
||||
|
||||
/* Power management idle timer set to the default. */
|
||||
mtdcr (memcfga, mem_pmit);
|
||||
mtdcr (memcfgd, 0x07c00000);
|
||||
|
||||
udelay (500);
|
||||
|
||||
/* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) TODO */
|
||||
mtdcr (memcfga, mem_mcopt1);
|
||||
mtdcr (memcfgd, 0x90800000);
|
||||
|
||||
#ifdef DEBUG
|
||||
printf ("%s: done\n", __FUNCTION__);
|
||||
#endif
|
||||
return SDRAM_LEN;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------+
|
||||
* getSerialNr
|
||||
*---------------------------------------------------------------------------*/
|
||||
static u32 getSerialNr(void)
|
||||
{
|
||||
u32 *serial = (u32 *)CFG_FLASH_BASE;
|
||||
|
||||
if (*serial == 0xffffffff)
|
||||
return get_ticks();
|
||||
|
||||
return *serial;
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------+
|
||||
* misc_init_r.
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
char *s = getenv("ethaddr");
|
||||
char *e;
|
||||
int i;
|
||||
u32 serial = getSerialNr();
|
||||
|
||||
for (i = 0; i < 6; ++i) {
|
||||
gd->bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0;
|
||||
if (s)
|
||||
s = (*e) ? e + 1 : e;
|
||||
}
|
||||
|
||||
if (gd->bd->bi_enetaddr[3] == 0 &&
|
||||
gd->bd->bi_enetaddr[4] == 0 &&
|
||||
gd->bd->bi_enetaddr[5] == 0) {
|
||||
char ethaddr[22];
|
||||
/* [0..3] Must be in sync with CONFIG_ETHADDR */
|
||||
gd->bd->bi_enetaddr[0] = 0x00;
|
||||
gd->bd->bi_enetaddr[1] = 0x60;
|
||||
gd->bd->bi_enetaddr[2] = 0x13;
|
||||
gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff;
|
||||
gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff;
|
||||
gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xff;
|
||||
sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0",
|
||||
gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1],
|
||||
gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3],
|
||||
gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ;
|
||||
printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__,
|
||||
ethaddr, serial);
|
||||
setenv ("ethaddr", ethaddr);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef DO_UGLY_SDRAM_WORKAROUND
|
||||
#include "i2c.h"
|
||||
|
||||
void set_spd_default_value(unsigned int spd_addr,uchar def_val)
|
||||
{
|
||||
uchar value;
|
||||
int res = i2c_read(SPD_EEPROM_ADDRESS, spd_addr, 1, &value, 1) ;
|
||||
|
||||
if (res == 0 && value == 0xff) {
|
||||
res = i2c_write(SPD_EEPROM_ADDRESS,
|
||||
spd_addr, 1, &def_val, 1) ;
|
||||
#ifdef DEBUG
|
||||
printf("%s: Setting spd offset %3d to %3d res %d\n",
|
||||
__FUNCTION__, spd_addr, def_val, res);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
long int initdram(int board_type)
|
||||
{
|
||||
long dram_size = 0;
|
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM)
|
||||
dram_size = fixed_hcu4_sdram();
|
||||
#else
|
||||
#ifdef DO_UGLY_SDRAM_WORKAROUND
|
||||
/* Workaround if you have no working I2C-EEPROM-SPD-configuration */
|
||||
i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
|
||||
set_spd_default_value(2, 4); /* SDRAM Type */
|
||||
set_spd_default_value(7, 0); /* module width, high byte */
|
||||
set_spd_default_value(12, 1); /* Refresh or 0x81 */
|
||||
|
||||
/* Only correct for HCU3 with 32 MB RAM*/
|
||||
/* Number of bytes used by module manufacturer */
|
||||
set_spd_default_value( 0, 128);
|
||||
set_spd_default_value( 1, 11 ); /* Total SPD memory size */
|
||||
set_spd_default_value( 2, 4 ); /* Memory type */
|
||||
set_spd_default_value( 3, 12 ); /* Number of row address bits */
|
||||
set_spd_default_value( 4, 9 ); /* Number of column address bits */
|
||||
set_spd_default_value( 5, 1 ); /* Number of module rows */
|
||||
set_spd_default_value( 6, 32 ); /* Module data width, LSB */
|
||||
set_spd_default_value( 7, 0 ); /* Module data width, MSB */
|
||||
set_spd_default_value( 8, 1 ); /* Module interface signal levels */
|
||||
/* SDRAM cycle time for highest CL (Tclk) */
|
||||
set_spd_default_value( 9, 112);
|
||||
/* SDRAM access time from clock for highest CL (Tac) */
|
||||
set_spd_default_value(10, 84 );
|
||||
set_spd_default_value(11, 2 ); /* Module configuration type */
|
||||
set_spd_default_value(12, 128); /* Refresh rate/type */
|
||||
set_spd_default_value(13, 16 ); /* Primary SDRAM width */
|
||||
set_spd_default_value(14, 8 ); /* Error Checking SDRAM width */
|
||||
/* SDRAM device attributes, min clock delay for back to back */
|
||||
/*random column addresses (Tccd) */
|
||||
set_spd_default_value(15, 1 );
|
||||
/* SDRAM device attributes, burst lengths supported */
|
||||
set_spd_default_value(16, 143);
|
||||
/* SDRAM device attributes, number of banks on SDRAM device */
|
||||
set_spd_default_value(17, 4 );
|
||||
/* SDRAM device attributes, CAS latency */
|
||||
set_spd_default_value(18, 6 );
|
||||
/* SDRAM device attributes, CS latency */
|
||||
set_spd_default_value(19, 1 );
|
||||
/* SDRAM device attributes, WE latency */
|
||||
set_spd_default_value(20, 1 );
|
||||
set_spd_default_value(21, 0 ); /* SDRAM module attributes */
|
||||
/* SDRAM device attributes, general */
|
||||
set_spd_default_value(22, 14 );
|
||||
/* SDRAM cycle time for 2nd highest CL (Tclk) */
|
||||
set_spd_default_value(23, 117);
|
||||
/* SDRAM access time from clock for2nd highest CL (Tac) */
|
||||
set_spd_default_value(24, 84 );
|
||||
/* SDRAM cycle time for 3rd highest CL (Tclk) */
|
||||
set_spd_default_value(25, 0 );
|
||||
/* SDRAM access time from clock for3rd highest CL (Tac) */
|
||||
set_spd_default_value(26, 0 );
|
||||
set_spd_default_value(27, 15 ); /* Minimum row precharge time (Trp) */
|
||||
/* Minimum row active to row active delay (Trrd) */
|
||||
set_spd_default_value(28, 14 );
|
||||
set_spd_default_value(29, 15 ); /* Minimum CAS to RAS delay (Trcd) */
|
||||
set_spd_default_value(30, 37 ); /* Minimum RAS pulse width (Tras) */
|
||||
set_spd_default_value(31, 8 ); /* Module bank density */
|
||||
/* Command and Address signal input setup time */
|
||||
set_spd_default_value(32, 21 );
|
||||
/* Command and Address signal input hold time */
|
||||
set_spd_default_value(33, 8 );
|
||||
set_spd_default_value(34, 21 ); /* Data signal input setup time */
|
||||
set_spd_default_value(35, 8 ); /* Data signal input hold time */
|
||||
#endif /* DO_UGLY_SDRAM_WORKAROUND */
|
||||
dram_size = spd_sdram(0);
|
||||
#endif
|
||||
|
||||
#ifdef DEBUG
|
||||
show_sdram_registers();
|
||||
#endif
|
||||
|
||||
#if defined(CFG_DRAM_TEST)
|
||||
bcu4_testdram(dram_size);
|
||||
printf("%s %d MB of SDRAM\n", __FUNCTION__, dram_size/(1024*1024));
|
||||
#endif
|
||||
|
||||
return dram_size;
|
||||
}
|
140
board/netstal/hcu4/u-boot.lds
Normal file
140
board/netstal/hcu4/u-boot.lds
Normal file
|
@ -0,0 +1,140 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
.resetvec 0xFFFFFFFC :
|
||||
{
|
||||
*(.resetvec)
|
||||
} = 0xffff
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text : {
|
||||
/* The start.o file includes the initial jump vector that
|
||||
must be located in the beginning. It is the basic run-
|
||||
time function that calls all other functions. */
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
|
||||
/* . = env_offset;*/
|
||||
/* common/environment.o(.text)*/
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
*(.eh_frame)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
49
board/netstal/hcu5/Makefile
Normal file
49
board/netstal/hcu5/Makefile
Normal file
|
@ -0,0 +1,49 @@
|
|||
#
|
||||
# (C) Copyright 2007 Netstal Maschinen AG
|
||||
# Niklaus Giger (ng@netstal.com)
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
vpath flash.c ../common
|
||||
COBJS = $(BOARD).o sdram.o flash.o
|
||||
SOBJS = init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
174
board/netstal/hcu5/README.txt
Normal file
174
board/netstal/hcu5/README.txt
Normal file
|
@ -0,0 +1,174 @@
|
|||
HCU5 configuration details and startup sequence
|
||||
|
||||
(C) Copyright 2007 Netstal Maschinen AG
|
||||
Niklaus Giger (Niklaus.Giger@netstal.com)
|
||||
|
||||
TODO:
|
||||
-----
|
||||
- Fix error: Waiting for PHY auto negotiation to complete..... TIMEOUT !
|
||||
- Does not occur if both EMAC are connected
|
||||
- Fix RTS/CTS problem (HW?)
|
||||
CONFIG_SERIAL_MULTI/CONFIG_SERIAL_SOFTWARE_FIFO hangs after
|
||||
Switching to interrupt driven serial input mode
|
||||
- Make vxWorks start from u-boot. Possible reasons
|
||||
- Does vxWorks need an entry for the Machine Check interrupt like this
|
||||
tlbentry( 0x40000000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) ?
|
||||
|
||||
Caveats:
|
||||
--------
|
||||
Errata CHIP_8: Incorrect Write to DDR SDRAM. (was not applied to sequoia.c)
|
||||
see hcu5.c.
|
||||
|
||||
|
||||
Memory Bank 0 -- Flash chip
|
||||
---------------------------
|
||||
|
||||
0xfff00000 - 0xffffffff
|
||||
|
||||
The flash chip is really only 512Kbytes, but the high address bit of
|
||||
the 1Meg region is ignored, so the flash is replicated through the
|
||||
region. Thus, this is consistent with a flash base address 0xfff80000.
|
||||
|
||||
The placement at the end is to be consistent with reset behavior,
|
||||
where the processor itself initially uses this bus to load the branch
|
||||
vector and start running.
|
||||
|
||||
On-Chip Memory
|
||||
--------------
|
||||
|
||||
0xe0010000- 0xe0013fff CFG_OCM_BASE
|
||||
The 440EPx includes a 16K on-chip memory that can be placed however
|
||||
software chooses.
|
||||
|
||||
Internal Peripherals
|
||||
--------------------
|
||||
|
||||
0xef600300 - 0xef6008ff
|
||||
|
||||
These are scattered various peripherals internal to the PPC440EPX
|
||||
chip.
|
||||
|
||||
Chip-Select 2: Flash Memory
|
||||
---------------------------
|
||||
|
||||
Not used
|
||||
|
||||
Chip-Select 3: CAN Interface
|
||||
----------------------------
|
||||
0xc800000: 2 Intel 82527 CAN-Controller
|
||||
|
||||
|
||||
Chip-Select 4: IMC-bus standard
|
||||
-------------------------------
|
||||
|
||||
0xcc00000: Netstal specific IO-Bus
|
||||
|
||||
|
||||
Chip-Select 5: IMC-bus fast (inactive)
|
||||
--------------------------------------
|
||||
|
||||
0xce00000: Netstal specific IO-Bus (fast, but not yet used)
|
||||
|
||||
|
||||
Memory Bank 1 -- DDR2
|
||||
-------------------------------------
|
||||
|
||||
0x00000000 - 0xfffffff # Default 256 MB
|
||||
|
||||
PCI ??
|
||||
|
||||
USB ??
|
||||
Only USB_STORAGE is enabled to load vxWorks
|
||||
from a memory stick.
|
||||
|
||||
System-LEDs ??? (Analog zu HCU4 ???)
|
||||
|
||||
Startup sequence
|
||||
----------------
|
||||
|
||||
(cpu/ppc4xx/resetvec.S)
|
||||
depending on configs option
|
||||
call _start_440 _start_pci oder _start
|
||||
|
||||
(cpu/ppc4xx/start.S)
|
||||
|
||||
_start_440:
|
||||
initialize register like
|
||||
CCR0
|
||||
debug
|
||||
setup interrupt vectors
|
||||
configure cache regions
|
||||
clear and setup TLB
|
||||
enable internal RAM
|
||||
jump start_ram
|
||||
which in turn will jump to start
|
||||
_start:
|
||||
Clear and set up some registers.
|
||||
Debug setup
|
||||
Setup the internal SRAM
|
||||
Setup the stack in internal SRAM
|
||||
setup stack pointer (r1)
|
||||
setup GOT
|
||||
call cpu_init_f /* run low-level CPU init code (from Flash) */
|
||||
|
||||
call cpu_init_f
|
||||
board_init_f: (lib_ppc\board.c)
|
||||
init_sequence defines a list of function to be called
|
||||
board_early_init_f: (board/netstal/hcu5/hcu5.c)
|
||||
We are using Bootstrap-Option A
|
||||
if CPR0_ICFG_RLI_MASK == 0 then set some registers and reboot
|
||||
Setup the GPIO pins
|
||||
Setup the interrupt controller polarities, triggers, etc.
|
||||
Ethernet, PCI, USB enable
|
||||
setup BOOT FLASH (Chip timing)
|
||||
init_baudrate,
|
||||
serial_init
|
||||
checkcpu
|
||||
misc_init_f #ifdef
|
||||
init_func_i2c #ifdef
|
||||
post_init_f #ifdef
|
||||
init_func_ram -> calls init_dram board/netstal/hcu5/sdram.c
|
||||
(EYE function removed!!)
|
||||
test_dram call
|
||||
|
||||
* Reserve memory at end of RAM for (top down in that order):
|
||||
* - kernel log buffer
|
||||
* - protected RAM
|
||||
* - LCD framebuffer
|
||||
* - monitor code
|
||||
* - board info struct
|
||||
Save local variables to board info struct
|
||||
call relocate_code() does not return
|
||||
relocate_code: (cpu/ppc4xx/start.S)
|
||||
-------------------------------------------------------
|
||||
From now on our copy is in RAM and we will run from there,
|
||||
starting with board_init_r
|
||||
-------------------------------------------------------
|
||||
board_init_r: (lib_ppc\board.c)
|
||||
setup bd function pointers
|
||||
trap_init
|
||||
flash_init: (board/netstal/hcu5/flash.c)
|
||||
/* setup for u-boot erase, update */
|
||||
setup bd flash info
|
||||
cpu_init_r: (cpu/ppc4xx/cpu_init.c)
|
||||
peripheral chip select in using defines like
|
||||
CFG_EBC_PB0A, CFG_EBC_PB0C from hcu5.h
|
||||
mem_malloc_init
|
||||
malloc_bin_reloc
|
||||
spi_init (r or f)??? (CFG_ENV_IS_IN_EEPROM)
|
||||
env_relocated
|
||||
misc_init_r(bd): (board/netstal/hcu5.c)
|
||||
ethaddr mit serial number ergänzen
|
||||
Then we will somehow go into the command loop
|
||||
|
||||
Most of the HW specific code for the HCU5 may be found in
|
||||
include/configs/hcu5.h
|
||||
board/netstal/hcu5/*
|
||||
cpu/ppc4xx/*
|
||||
lib_ppc/*
|
||||
include/ppc440.h
|
||||
|
||||
Drivers for serial etc are found under drivers/
|
||||
|
||||
Don't ask question if you did not look at the README !!
|
||||
Most CFG_* and CONFIG_* switches are mentioned/explained there.
|
30
board/netstal/hcu5/config.mk
Normal file
30
board/netstal/hcu5/config.mk
Normal file
|
@ -0,0 +1,30 @@
|
|||
#
|
||||
# (C) Copyright 2005 Netstal Maschinen AG
|
||||
# Niklaus Giger (ng@netstal.com)
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# Netstal Maschinen AG: HCU5 boards
|
||||
#
|
||||
|
||||
TEXT_BASE = 0xFFFa0000
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_440=1
|
||||
|
||||
ifeq ($(debug),1)
|
||||
PLATFORM_CPPFLAGS += -DDEBUG -g
|
||||
endif
|
525
board/netstal/hcu5/hcu5.c
Normal file
525
board/netstal/hcu5/hcu5.c
Normal file
|
@ -0,0 +1,525 @@
|
|||
/*
|
||||
*(C) Copyright 2005-2007 Netstal Maschinen AG
|
||||
* Niklaus Giger (Niklaus.Giger@netstal.com)
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <ppc440.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
void sysLedSet(u32 value);
|
||||
|
||||
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
|
||||
|
||||
#undef BOOTSTRAP_OPTION_A_ACTIVE
|
||||
|
||||
#define SDR0_CP440 0x0180
|
||||
|
||||
#define SYSTEM_RESET 0x30000000
|
||||
#define CHIP_RESET 0x20000000
|
||||
|
||||
#define SDR0_ECID0 0x0080
|
||||
#define SDR0_ECID1 0x0081
|
||||
#define SDR0_ECID2 0x0082
|
||||
#define SDR0_ECID3 0x0083
|
||||
|
||||
#define SYS_IO_ADDRESS 0xcce00000
|
||||
|
||||
#define DEFAULT_ETH_ADDR "ethaddr"
|
||||
/* ethaddr for first or etha1ddr for second ethernet */
|
||||
|
||||
enum {
|
||||
/* HW_GENERATION_HCU1 is no longer supported */
|
||||
HW_GENERATION_HCU2 = 0x10,
|
||||
HW_GENERATION_HCU3 = 0x10,
|
||||
HW_GENERATION_HCU4 = 0x20,
|
||||
HW_GENERATION_HCU5 = 0x30,
|
||||
HW_GENERATION_MCU = 0x08,
|
||||
HW_GENERATION_MCU20 = 0x0a,
|
||||
HW_GENERATION_MCU25 = 0x09,
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* This function is run very early, out of flash, and before devices are
|
||||
* initialized. It is called by lib_ppc/board.c:board_init_f by virtue
|
||||
* of being in the init_sequence array.
|
||||
*
|
||||
* The SDRAM has been initialized already -- start.S:start called
|
||||
* init.S:init_sdram early on -- but it is not yet being used for
|
||||
* anything, not even stack. So be careful.
|
||||
*/
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
#ifdef BOOTSTRAP_OPTION_A_ACTIVE
|
||||
/* Booting with Bootstrap Option A
|
||||
* First boot, with CPR0_ICFG_RLI_MASK == 0
|
||||
* no we setup varios boot strapping register,
|
||||
* then we do reset the PPC440 using a chip reset
|
||||
* Unfortunately, we cannot use this option, as Nto1 is not set
|
||||
* with Bootstrap Option A and cannot be changed later on by SW
|
||||
* There are no other possible boostrap options with a 8 bit ROM
|
||||
* See Errata (Version 1.04) CHIP_9
|
||||
*/
|
||||
|
||||
u32 cpr0icfg;
|
||||
u32 dbcr;
|
||||
|
||||
mfcpr(CPR0_ICFG, cpr0icfg);
|
||||
if (!(cpr0icfg & CPR0_ICFG_RLI_MASK)) {
|
||||
mtcpr(CPR0_MALD, 0x02000000);
|
||||
mtcpr(CPR0_OPBD, 0x02000000);
|
||||
mtcpr(CPR0_PERD, 0x05000000); /* 1:5 */
|
||||
mtcpr(CPR0_PLLC, 0x40000238);
|
||||
mtcpr(CPR0_PLLD, 0x01010414);
|
||||
mtcpr(CPR0_PRIMAD, 0x01000000);
|
||||
mtcpr(CPR0_PRIMBD, 0x01000000);
|
||||
mtcpr(CPR0_SPCID, 0x03000000);
|
||||
mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */
|
||||
mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
|
||||
mtcpr(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK);
|
||||
|
||||
/*
|
||||
* Initiate system reset in debug control register DBCR
|
||||
*/
|
||||
dbcr = mfspr(dbcr0);
|
||||
mtspr(dbcr0, dbcr | CHIP_RESET);
|
||||
}
|
||||
mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
|
||||
#endif
|
||||
mtdcr(ebccfga, xbcfg);
|
||||
mtdcr(ebccfgd, 0xb8400000);
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the GPIO pins
|
||||
*-------------------------------------------------------------------*/
|
||||
/* test-only: take GPIO init from pcs440ep ???? in config file */
|
||||
out32(GPIO0_OR, 0x00000000);
|
||||
out32(GPIO0_TCR, 0x7C2FF1CF);
|
||||
out32(GPIO0_OSRL, 0x40055000);
|
||||
out32(GPIO0_OSRH, 0x00000000);
|
||||
out32(GPIO0_TSRL, 0x40055000);
|
||||
out32(GPIO0_TSRH, 0x00000400);
|
||||
out32(GPIO0_ISR1L, 0x40000000);
|
||||
out32(GPIO0_ISR1H, 0x00000000);
|
||||
out32(GPIO0_ISR2L, 0x00000000);
|
||||
out32(GPIO0_ISR2H, 0x00000000);
|
||||
out32(GPIO0_ISR3L, 0x00000000);
|
||||
out32(GPIO0_ISR3H, 0x00000000);
|
||||
|
||||
out32(GPIO1_OR, 0x00000000);
|
||||
out32(GPIO1_TCR, 0xC6007FFF);
|
||||
out32(GPIO1_OSRL, 0x00140000);
|
||||
out32(GPIO1_OSRH, 0x00000000);
|
||||
out32(GPIO1_TSRL, 0x00000000);
|
||||
out32(GPIO1_TSRH, 0x00000000);
|
||||
out32(GPIO1_ISR1L, 0x05415555);
|
||||
out32(GPIO1_ISR1H, 0x40000000);
|
||||
out32(GPIO1_ISR2L, 0x00000000);
|
||||
out32(GPIO1_ISR2H, 0x00000000);
|
||||
out32(GPIO1_ISR3L, 0x00000000);
|
||||
out32(GPIO1_ISR3H, 0x00000000);
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the interrupt controller polarities, triggers, etc.
|
||||
*-------------------------------------------------------------------*/
|
||||
mtdcr(uic0sr, 0xffffffff); /* clear all */
|
||||
mtdcr(uic0er, 0x00000000); /* disable all */
|
||||
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
|
||||
mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
|
||||
mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
|
||||
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
|
||||
mtdcr(uic0sr, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr(uic1sr, 0xffffffff); /* clear all */
|
||||
mtdcr(uic1er, 0x00000000); /* disable all */
|
||||
mtdcr(uic1cr, 0x00000000); /* all non-critical */
|
||||
mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
|
||||
mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
|
||||
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
|
||||
mtdcr(uic1sr, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr(uic2sr, 0xffffffff); /* clear all */
|
||||
mtdcr(uic2er, 0x00000000); /* disable all */
|
||||
mtdcr(uic2cr, 0x00000000); /* all non-critical */
|
||||
mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
|
||||
mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
|
||||
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
|
||||
mtdcr(uic2sr, 0xffffffff); /* clear all */
|
||||
mtsdr(sdr_pfc0, 0x00003E00); /* Pin function: */
|
||||
mtsdr(sdr_pfc1, 0x00848000); /* Pin function: UART0 has 4 pins */
|
||||
|
||||
/* PCI arbiter enabled */
|
||||
mfsdr(sdr_pci0, reg);
|
||||
mtsdr(sdr_pci0, 0x80000000 | reg);
|
||||
|
||||
pci_pre_init(0);
|
||||
|
||||
/* setup BOOT FLASH */
|
||||
mtsdr(SDR0_CUST0, 0xC0082350);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_pre_init(void)
|
||||
{
|
||||
return board_early_init_f();
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
unsigned int j;
|
||||
u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER;
|
||||
u16 *boardVersReg = (u16 *) HCU_CPLD_VERSION_REGISTER;
|
||||
u16 generation = *boardVersReg & 0xf0;
|
||||
u16 index = *boardVersReg & 0x0f;
|
||||
u32 ecid0, ecid1, ecid2, ecid3;
|
||||
|
||||
printf("Netstal Maschinen AG: ");
|
||||
if (generation == HW_GENERATION_HCU3)
|
||||
printf("HCU3: index %d", index);
|
||||
else if (generation == HW_GENERATION_HCU4)
|
||||
printf("HCU4: index %d", index);
|
||||
else if (generation == HW_GENERATION_HCU5)
|
||||
printf("HCU5: index %d", index);
|
||||
printf(" HW 0x%02x\n", *hwVersReg & 0xff);
|
||||
mfsdr(SDR0_ECID0, ecid0);
|
||||
mfsdr(SDR0_ECID1, ecid1);
|
||||
mfsdr(SDR0_ECID2, ecid2);
|
||||
mfsdr(SDR0_ECID3, ecid3);
|
||||
|
||||
printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3);
|
||||
for (j = 0;j < 6; j++) {
|
||||
sysLedSet(1 << j);
|
||||
udelay(200 * 1000);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 sysLedGet(void)
|
||||
{
|
||||
return in16(SYS_IO_ADDRESS) & 0x3f;
|
||||
}
|
||||
|
||||
void sysLedSet(u32 value /* value to place in LEDs */)
|
||||
{
|
||||
out16(SYS_IO_ADDRESS, value);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------+
|
||||
* getSerialNr
|
||||
*---------------------------------------------------------------------------*/
|
||||
static u32 getSerialNr(void)
|
||||
{
|
||||
u32 *serial = (u32 *)CFG_FLASH_BASE;
|
||||
|
||||
if (*serial == 0xffffffff)
|
||||
return get_ticks();
|
||||
|
||||
return *serial;
|
||||
}
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------+
|
||||
* misc_init_r.
|
||||
*---------------------------------------------------------------------------*/
|
||||
int misc_init_r(void)
|
||||
{
|
||||
char *s = getenv(DEFAULT_ETH_ADDR);
|
||||
char *e;
|
||||
int i;
|
||||
u32 serial = getSerialNr();
|
||||
unsigned long usb2d0cr = 0;
|
||||
unsigned long usb2phy0cr, usb2h0cr = 0;
|
||||
unsigned long sdr0_pfc1;
|
||||
|
||||
for (i = 0; i < 6; ++i) {
|
||||
gd->bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0;
|
||||
if (s)
|
||||
s = (*e) ? e + 1 : e;
|
||||
}
|
||||
|
||||
if (gd->bd->bi_enetaddr[3] == 0 &&
|
||||
gd->bd->bi_enetaddr[4] == 0 &&
|
||||
gd->bd->bi_enetaddr[5] == 0) {
|
||||
char ethaddr[22];
|
||||
|
||||
/* Must be in sync with CONFIG_ETHADDR */
|
||||
gd->bd->bi_enetaddr[0] = 0x00;
|
||||
gd->bd->bi_enetaddr[1] = 0x60;
|
||||
gd->bd->bi_enetaddr[2] = 0x13;
|
||||
gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff;
|
||||
gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff;
|
||||
/* byte[5].bit 0 must be zero */
|
||||
gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xfe;
|
||||
sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0",
|
||||
gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1],
|
||||
gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3],
|
||||
gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ;
|
||||
printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__,
|
||||
ethaddr, serial);
|
||||
setenv(DEFAULT_ETH_ADDR, ethaddr);
|
||||
}
|
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH
|
||||
/* Monitor protection ON by default */
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
-CFG_MONITOR_LEN,
|
||||
0xffffffff,
|
||||
&flash_info[0]);
|
||||
|
||||
/* Env protection ON by default */
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
CFG_ENV_ADDR_REDUND,
|
||||
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
|
||||
&flash_info[0]);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* USB stuff...
|
||||
*/
|
||||
|
||||
/* SDR Setting */
|
||||
mfsdr(SDR0_PFC1, sdr0_pfc1);
|
||||
mfsdr(SDR0_USB2D0CR, usb2d0cr);
|
||||
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
||||
mfsdr(SDR0_USB2H0CR, usb2h0cr);
|
||||
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
|
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
|
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
|
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
|
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
|
||||
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
|
||||
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
|
||||
|
||||
/* An 8-bit/60MHz interface is the only possible alternative
|
||||
when connecting the Device to the PHY */
|
||||
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
|
||||
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
|
||||
|
||||
/* To enable the USB 2.0 Device function through the UTMI interface */
|
||||
usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
|
||||
usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/
|
||||
|
||||
sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
|
||||
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
|
||||
|
||||
mtsdr(SDR0_PFC1, sdr0_pfc1);
|
||||
mtsdr(SDR0_USB2D0CR, usb2d0cr);
|
||||
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
|
||||
mtsdr(SDR0_USB2H0CR, usb2h0cr);
|
||||
|
||||
/*clear resets*/
|
||||
udelay(1000);
|
||||
mtsdr(SDR0_SRST1, 0x00000000);
|
||||
udelay(1000);
|
||||
mtsdr(SDR0_SRST0, 0x00000000);
|
||||
|
||||
printf("USB: Host(int phy) Device(ext phy)\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*************************************************************************
|
||||
* pci_pre_init
|
||||
*
|
||||
* This routine is called just prior to registering the hose and gives
|
||||
* the board the opportunity to check things. Returning a value of zero
|
||||
* indicates that things are bad & PCI initialization should be aborted.
|
||||
*
|
||||
* Different boards may wish to customize the pci controller structure
|
||||
* (add regions, override default access routines, etc) or perform
|
||||
* certain pre-initialization actions.
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI)
|
||||
int pci_pre_init(struct pci_controller *hose)
|
||||
{
|
||||
unsigned long addr;
|
||||
|
||||
/*-------------------------------------------------------------------+
|
||||
* As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
|
||||
* Workaround: Disable write pipelining to DDR SDRAM by setting
|
||||
* PLB0_ACR[WRP] = 0.
|
||||
*-------------------------------------------------------------------*/
|
||||
|
||||
/*-------------------------------------------------------------------+
|
||||
| Set priority for all PLB3 devices to 0.
|
||||
| Set PLB3 arbiter to fair mode.
|
||||
+-------------------------------------------------------------------*/
|
||||
mfsdr(sdr_amp1, addr);
|
||||
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
|
||||
addr = mfdcr(plb3_acr);
|
||||
/* mtdcr(plb3_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */
|
||||
mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */
|
||||
|
||||
/*-------------------------------------------------------------------+
|
||||
| Set priority for all PLB4 devices to 0.
|
||||
+-------------------------------------------------------------------*/
|
||||
mfsdr(sdr_amp0, addr);
|
||||
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
|
||||
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
|
||||
/* mtdcr(plb4_acr, addr & ~plb1_acr_wrp_mask); */ /* ngngng */
|
||||
mtdcr(plb4_acr, addr); /* Sequoia */
|
||||
|
||||
/*-------------------------------------------------------------------+
|
||||
| Set Nebula PLB4 arbiter to fair mode.
|
||||
+-------------------------------------------------------------------*/
|
||||
/* Segment0 */
|
||||
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
|
||||
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
|
||||
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
|
||||
/* addr = (addr & ~plb0_acr_wrp_mask); */ /* ngngng */
|
||||
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; /* Sequoia */
|
||||
|
||||
/* mtdcr(plb0_acr, addr); */ /* Sequoia */
|
||||
mtdcr(plb0_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */
|
||||
|
||||
/* Segment1 */
|
||||
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
|
||||
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
|
||||
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
|
||||
addr = (addr & ~plb1_acr_wrp_mask) ;
|
||||
/* mtdcr(plb1_acr, addr); */ /* Sequoia */
|
||||
mtdcr(plb1_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) */
|
||||
|
||||
/*************************************************************************
|
||||
* pci_target_init
|
||||
*
|
||||
* The bootstrap configuration provides default settings for the pci
|
||||
* inbound map (PIM). But the bootstrap config choices are limited and
|
||||
* may not be sufficient for a given board.
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
|
||||
void pci_target_init(struct pci_controller *hose)
|
||||
{
|
||||
/*-------------------------------------------------------------+
|
||||
* Set up Direct MMIO registers
|
||||
*-------------------------------------------------------------*/
|
||||
/*-------------------------------------------------------------+
|
||||
| PowerPC440EPX PCI Master configuration.
|
||||
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
|
||||
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address
|
||||
| 0xA0000000-0xDFFFFFFF
|
||||
| Use byte reversed out routines to handle endianess.
|
||||
| Make this region non-prefetchable.
|
||||
+-------------------------------------------------------------*/
|
||||
/* PMM0 Mask/Attribute - disabled b4 setting */
|
||||
out32r(PCIX0_PMM0MA, 0x00000000);
|
||||
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
|
||||
/* PMM0 PCI Low Address */
|
||||
out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);
|
||||
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
|
||||
/* 512M + No prefetching, and enable region */
|
||||
out32r(PCIX0_PMM0MA, 0xE0000001);
|
||||
|
||||
/* PMM0 Mask/Attribute - disabled b4 setting */
|
||||
out32r(PCIX0_PMM1MA, 0x00000000);
|
||||
out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
|
||||
/* PMM0 PCI Low Address */
|
||||
out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);
|
||||
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
|
||||
/* 512M + No prefetching, and enable region */
|
||||
out32r(PCIX0_PMM1MA, 0xE0000001);
|
||||
|
||||
out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
|
||||
out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
|
||||
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
|
||||
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
|
||||
|
||||
/*------------------------------------------------------------------+
|
||||
* Set up Configuration registers
|
||||
*------------------------------------------------------------------*/
|
||||
|
||||
/* Program the board's subsystem id/vendor id */
|
||||
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
|
||||
CFG_PCI_SUBSYS_VENDORID);
|
||||
pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
|
||||
|
||||
/* Configure command register as bus master */
|
||||
pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
|
||||
|
||||
/* 240nS PCI clock */
|
||||
pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
|
||||
|
||||
/* No error reporting */
|
||||
pci_write_config_word(0, PCI_ERREN, 0);
|
||||
|
||||
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
|
||||
|
||||
/*************************************************************************
|
||||
* pci_master_init
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
|
||||
void pci_master_init(struct pci_controller *hose)
|
||||
{
|
||||
unsigned short temp_short;
|
||||
|
||||
/*---------------------------------------------------------------+
|
||||
| Write the PowerPC440 EP PCI Configuration regs.
|
||||
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
|
||||
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
|
||||
+--------------------------------------------------------------*/
|
||||
pci_read_config_word(0, PCI_COMMAND, &temp_short);
|
||||
pci_write_config_word(0, PCI_COMMAND,
|
||||
temp_short | PCI_COMMAND_MASTER |
|
||||
PCI_COMMAND_MEMORY);
|
||||
}
|
||||
#endif
|
||||
/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
|
||||
|
||||
/*************************************************************************
|
||||
* is_pci_host
|
||||
*
|
||||
* This routine is called to determine if a pci scan should be
|
||||
* performed. With various hardware environments (especially cPCI and
|
||||
* PPMC) it's insufficient to depend on the state of the arbiter enable
|
||||
* bit in the strap register, or generic host/adapter assumptions.
|
||||
*
|
||||
* Rather than hard-code a bad assumption in the general 440 code, the
|
||||
* 440 pci code requires the board to decide at runtime.
|
||||
*
|
||||
* Return 0 for adapter mode, non-zero for host (monarch) mode.
|
||||
*
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI)
|
||||
int is_pci_host(struct pci_controller *hose)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) */
|
79
board/netstal/hcu5/init.S
Normal file
79
board/netstal/hcu5/init.S
Normal file
|
@ -0,0 +1,79 @@
|
|||
/*
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <config.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
/**************************************************************************
|
||||
* TLB TABLE
|
||||
*
|
||||
* This table is used by the cpu boot code to setup the initial tlb
|
||||
* entries. Rather than make broad assumptions in the cpu source tree,
|
||||
* this table lets each board set things up however they like.
|
||||
*
|
||||
* Pointer to the table is returned in r1
|
||||
*
|
||||
*************************************************************************/
|
||||
.section .bootpg,"ax"
|
||||
.globl tlbtab
|
||||
|
||||
tlbtab:
|
||||
tlbtab_start
|
||||
|
||||
/* vxWorks needs this entry for the Machine Check interrupt, */
|
||||
/* tlbentry( 0x40000000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) */
|
||||
|
||||
/*
|
||||
* BOOT_CS (FLASH) must be second. Before relocation SA_I can be off to use the
|
||||
* speed up boot process. It is patched after relocation to enable SA_I
|
||||
*/
|
||||
tlbentry( CFG_BOOT_BASE_ADDR, SZ_1M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
|
||||
|
||||
/* TLB-entry for PCI Memory */
|
||||
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
|
||||
/* TLB-entry for EBC (CFG_CPLD) */
|
||||
/* tlbentry( CFG_CPLD, SZ_1K, CFG_CPLD, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) */
|
||||
/* CAN */
|
||||
tlbentry( CFG_CS_1, SZ_16M, CFG_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
/* IMC + CPLD */
|
||||
tlbentry( CFG_CS_2, SZ_16M, CFG_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CFG_CS_2 + 0x1000000, SZ_16M, CFG_CS_2 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
/* IMC-Fast */
|
||||
tlbentry( CFG_CS_3, SZ_16M, CFG_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CFG_CS_3 + 0x1000000, SZ_16M, CFG_CS_3 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
|
||||
/* TLB-entry for Internal Registers & OCM */
|
||||
tlbentry( CFG_PCI_BASE, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
|
||||
|
||||
/*TLB-entry PCI registers*/
|
||||
tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
|
||||
/* TLB-entry for peripherals */
|
||||
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
|
||||
/* TLB for SDRAM will be added by initdram (sdram.c) */
|
||||
|
||||
tlbtab_end
|
302
board/netstal/hcu5/sdram.c
Normal file
302
board/netstal/hcu5/sdram.c
Normal file
|
@ -0,0 +1,302 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Niklaus Giger (Niklaus.Giger@netstal.com)
|
||||
* (C) Copyright 2006
|
||||
* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
|
||||
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
|
||||
* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
|
||||
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
|
||||
* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
|
||||
*
|
||||
* (C) Copyright 2006
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/* define DEBUG for debug output */
|
||||
#undef DEBUG
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <ppc440.h>
|
||||
|
||||
void sysLedSet(u32 value);
|
||||
void dcbz_area(u32 start_address, u32 num_bytes);
|
||||
void dflush(void);
|
||||
|
||||
#define DDR_DCR_BASE 0x10
|
||||
#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */
|
||||
#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */
|
||||
|
||||
#define DDR0_01_INT_MASK_MASK 0x000000FF
|
||||
#define DDR0_00_INT_ACK_ALL 0x7F000000
|
||||
#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
|
||||
#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
|
||||
|
||||
#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
|
||||
#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
|
||||
#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
|
||||
|
||||
#define DDR0_22 0x16
|
||||
/* ECC */
|
||||
#define DDR0_22_CTRL_RAW_MASK 0x03000000
|
||||
#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not enabled */
|
||||
#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC no correction */
|
||||
#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* Not a ECC RAM*/
|
||||
#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC correcting on */
|
||||
#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
|
||||
#ifdef CFG_ENABLE_SDRAM_CACHE
|
||||
#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on DDR2 */
|
||||
#else
|
||||
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on DDR2 */
|
||||
#endif
|
||||
|
||||
void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
|
||||
|
||||
#ifdef CONFIG_ADD_RAM_INFO
|
||||
void board_add_ram_info(int use_default)
|
||||
{
|
||||
PPC440_SYS_INFO board_cfg;
|
||||
u32 val;
|
||||
mfsdram(DDR0_22, val);
|
||||
val &= DDR0_22_CTRL_RAW_MASK;
|
||||
switch (val) {
|
||||
case DDR0_22_CTRL_RAW_ECC_DISABLE:
|
||||
puts(" (ECC disabled");
|
||||
break;
|
||||
case DDR0_22_CTRL_RAW_ECC_CHECK_ONLY:
|
||||
puts(" (ECC check only");
|
||||
break;
|
||||
case DDR0_22_CTRL_RAW_NO_ECC_RAM:
|
||||
puts(" (no ECC ram");
|
||||
break;
|
||||
case DDR0_22_CTRL_RAW_ECC_ENABLE:
|
||||
puts(" (ECC enabled");
|
||||
break;
|
||||
}
|
||||
|
||||
get_sys_info(&board_cfg);
|
||||
printf(", %d MHz", (board_cfg.freqPLB * 2) / 1000000);
|
||||
|
||||
mfsdram(DDR0_03, val);
|
||||
val = DDR0_03_CASLAT_DECODE(val);
|
||||
printf(", CL%d)", val);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* wait_for_dlllock.
|
||||
*--------------------------------------------------------------------*/
|
||||
static int wait_for_dlllock(void)
|
||||
{
|
||||
unsigned long val;
|
||||
int wait = 0;
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Wait for the DCC master delay line to finish calibration
|
||||
* ----------------------------------------------------------*/
|
||||
mtdcr(ddrcfga, DDR0_17);
|
||||
val = DDR0_17_DLLLOCKREG_UNLOCKED;
|
||||
|
||||
while (wait != 0xffff) {
|
||||
val = mfdcr(ddrcfgd);
|
||||
if ((val & DDR0_17_DLLLOCKREG_MASK) ==
|
||||
DDR0_17_DLLLOCKREG_LOCKED)
|
||||
/* dlllockreg bit on */
|
||||
return 0;
|
||||
else
|
||||
wait++;
|
||||
}
|
||||
debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
|
||||
debug("Waiting for dlllockreg bit to raise\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/***********************************************************************
|
||||
*
|
||||
* sdram_panic -- Panic if we cannot configure the sdram correctly
|
||||
*
|
||||
************************************************************************/
|
||||
void sdram_panic(const char *reason)
|
||||
{
|
||||
printf("\n%s: reason %s", __FUNCTION__, reason);
|
||||
sysLedSet(0xff);
|
||||
while (1) {
|
||||
}
|
||||
/* Never return */
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
static void blank_string(int size)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i=0; i<size; i++)
|
||||
putc('\b');
|
||||
for (i=0; i<size; i++)
|
||||
putc(' ');
|
||||
for (i=0; i<size; i++)
|
||||
putc('\b');
|
||||
}
|
||||
/*---------------------------------------------------------------------------+
|
||||
* program_ecc.
|
||||
*---------------------------------------------------------------------------*/
|
||||
static void program_ecc(unsigned long start_address, unsigned long num_bytes,
|
||||
unsigned long tlb_word2_i_value)
|
||||
{
|
||||
unsigned long current_address= start_address;
|
||||
int loopi = 0;
|
||||
u32 val;
|
||||
|
||||
char str[] = "ECC generation -";
|
||||
char slash[] = "\\|/-\\|/-";
|
||||
|
||||
sync();
|
||||
eieio();
|
||||
|
||||
puts(str);
|
||||
|
||||
if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
|
||||
/* ECC bit set method for non-cached memory */
|
||||
/* This takes various seconds */
|
||||
for(current_address = 0; current_address < num_bytes;
|
||||
current_address += sizeof(u32)) {
|
||||
*(u32 *)current_address = 0;
|
||||
if ((current_address % (2 << 20)) == 0) {
|
||||
putc('\b');
|
||||
putc(slash[loopi++ % 8]);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
/* ECC bit set method for cached memory */
|
||||
/* Fast method, no noticeable delay */
|
||||
dcbz_area(start_address, num_bytes);
|
||||
dflush();
|
||||
}
|
||||
blank_string(strlen(str));
|
||||
|
||||
/* Clear error status */
|
||||
mfsdram(DDR0_00, val);
|
||||
mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
|
||||
|
||||
/* Set 'int_mask' parameter to functionnal value */
|
||||
mfsdram(DDR0_01, val);
|
||||
mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) |
|
||||
DDR0_01_INT_MASK_ALL_OFF));
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/***********************************************************************
|
||||
*
|
||||
* initdram -- 440EPx's DDR controller is a DENALI Core
|
||||
*
|
||||
************************************************************************/
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
#define HCU_HW_SDRAM_CONFIG_MASK 0x7
|
||||
#define INVALID_HW_CONFIG "Invalid HW-Config"
|
||||
u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER;
|
||||
unsigned int dram_size = 0;
|
||||
|
||||
mtsdram(DDR0_02, 0x00000000);
|
||||
|
||||
/* Values must be kept in sync with Excel-table <<A0001492.>> ! */
|
||||
mtsdram(DDR0_00, 0x0000190A);
|
||||
mtsdram(DDR0_01, 0x01000000);
|
||||
mtsdram(DDR0_03, 0x02030602);
|
||||
mtsdram(DDR0_04, 0x0A020200);
|
||||
mtsdram(DDR0_05, 0x02020307);
|
||||
switch (*hwVersReg & HCU_HW_SDRAM_CONFIG_MASK) {
|
||||
case 0:
|
||||
dram_size = 128 * 1024 * 1024 ;
|
||||
mtsdram(DDR0_06, 0x0102C80D); /* 128MB RAM */
|
||||
mtsdram(DDR0_11, 0x000FC800); /* 128MB RAM */
|
||||
mtsdram(DDR0_43, 0x030A0300); /* 128MB RAM */
|
||||
break;
|
||||
case 1:
|
||||
dram_size = 256 * 1024 * 1024 ;
|
||||
mtsdram(DDR0_06, 0x0102C812); /* 256MB RAM */
|
||||
mtsdram(DDR0_11, 0x0014C800); /* 256MB RAM */
|
||||
mtsdram(DDR0_43, 0x030A0200); /* 256MB RAM */
|
||||
break;
|
||||
default:
|
||||
sdram_panic(INVALID_HW_CONFIG);
|
||||
break;
|
||||
}
|
||||
dram_size -= 16 * 1024 * 1024;
|
||||
mtsdram(DDR0_07, 0x00090100);
|
||||
/*
|
||||
* TCPD=200 cycles of clock input is required to lock the DLL.
|
||||
* CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001);
|
||||
*/
|
||||
mtsdram(DDR0_08, 0x02C80001);
|
||||
mtsdram(DDR0_09, 0x00011D5F);
|
||||
mtsdram(DDR0_10, 0x00000100);
|
||||
mtsdram(DDR0_12, 0x00000003);
|
||||
mtsdram(DDR0_14, 0x00000000);
|
||||
mtsdram(DDR0_17, 0x1D000000);
|
||||
mtsdram(DDR0_18, 0x1D1D1D1D);
|
||||
mtsdram(DDR0_19, 0x1D1D1D1D);
|
||||
mtsdram(DDR0_20, 0x0B0B0B0B);
|
||||
mtsdram(DDR0_21, 0x0B0B0B0B);
|
||||
#define ECC_RAM 0x03267F0B
|
||||
#define NO_ECC_RAM 0x00267F0B
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
mtsdram(DDR0_22, ECC_RAM);
|
||||
#else
|
||||
mtsdram(DDR0_22, NO_ECC_RAM);
|
||||
#endif
|
||||
|
||||
mtsdram(DDR0_23, 0x00000000);
|
||||
mtsdram(DDR0_24, 0x01020001);
|
||||
mtsdram(DDR0_26, 0x2D930517);
|
||||
mtsdram(DDR0_27, 0x00008236);
|
||||
mtsdram(DDR0_28, 0x00000000);
|
||||
mtsdram(DDR0_31, 0x00000000);
|
||||
mtsdram(DDR0_42, 0x01000006);
|
||||
mtsdram(DDR0_44, 0x00000003);
|
||||
mtsdram(DDR0_02, 0x00000001);
|
||||
wait_for_dlllock();
|
||||
mtsdram(DDR0_00, 0x40000000); /* Zero init bit */
|
||||
|
||||
/*
|
||||
* Program tlb entries for this size (dynamic)
|
||||
*/
|
||||
program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
|
||||
|
||||
/*
|
||||
* Setup 2nd TLB with same physical address but different virtual
|
||||
* address with cache enabled. This is done for fast ECC generation.
|
||||
*/
|
||||
program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0);
|
||||
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
/*
|
||||
* If ECC is enabled, initialize the parity bits.
|
||||
*/
|
||||
program_ecc(CFG_DDR_CACHED_ADDR, dram_size, 0);
|
||||
#endif
|
||||
|
||||
return (dram_size);
|
||||
}
|
144
board/netstal/hcu5/u-boot.lds
Normal file
144
board/netstal/hcu5/u-boot.lds
Normal file
|
@ -0,0 +1,144 @@
|
|||
/*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.resetvec 0xFFFFFFFC :
|
||||
{
|
||||
*(.resetvec)
|
||||
} = 0xffff
|
||||
|
||||
.bootpg 0xFFFFF000 :
|
||||
{
|
||||
cpu/ppc4xx/start.o (.bootpg)
|
||||
} = 0xffff
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
|
||||
ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
|
||||
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
|
@ -879,7 +879,7 @@ int ide_preinit (void)
|
|||
}
|
||||
#endif
|
||||
|
||||
#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
|
||||
#if defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET)
|
||||
void ide_set_reset (int idereset)
|
||||
{
|
||||
debug ("ide_reset(%d)\n", idereset);
|
||||
|
@ -890,4 +890,4 @@ void ide_set_reset (int idereset)
|
|||
}
|
||||
udelay (10000);
|
||||
}
|
||||
#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
|
||||
#endif /* defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
|
||||
|
|
52
board/sbc8641d/Makefile
Normal file
52
board/sbc8641d/Makefile
Normal file
|
@ -0,0 +1,52 @@
|
|||
#
|
||||
# (C) Copyright 2001
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := $(BOARD).o
|
||||
SOBJS := init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(OBJS) $(SOBJS)
|
||||
|
||||
.PHONY: distclean
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude ($obj).depend
|
||||
|
||||
#########################################################################
|
30
board/sbc8641d/config.mk
Normal file
30
board/sbc8641d/config.mk
Normal file
|
@ -0,0 +1,30 @@
|
|||
# Copyright 2004 Freescale Semiconductor.
|
||||
# Modified by Jeff Brown
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# sbc8641 board
|
||||
# default CCSRBAR is at 0xff700000
|
||||
#
|
||||
TEXT_BASE = 0xfff00000
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float
|
192
board/sbc8641d/init.S
Normal file
192
board/sbc8641d/init.S
Normal file
|
@ -0,0 +1,192 @@
|
|||
/*
|
||||
* Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
|
||||
* Copyright 2007 Embedded Specialties, Inc.
|
||||
* Joe Hamman joe.hamman@embeddedspecialties.com
|
||||
*
|
||||
* Copyright 2004 Freescale Semiconductor.
|
||||
* Jeff Brown
|
||||
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <ppc_defs.h>
|
||||
#include <asm/cache.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <config.h>
|
||||
#include <mpc86xx.h>
|
||||
|
||||
/*
|
||||
* LAW(Local Access Window) configuration:
|
||||
*
|
||||
* 0x0000_0000 0x0fff_ffff DDR1 256M
|
||||
* 0x1000_0000 0x1fff_ffff DDR2 256M
|
||||
* 0xe000_0000 0xffff_ffff LBC 512M
|
||||
*
|
||||
* Notes:
|
||||
* CCSRBAR doesn't need a configured Local Access Window.
|
||||
* If flash is 8M at default position (last 8M), no LAW needed.
|
||||
*/
|
||||
|
||||
# DDR Bank 1
|
||||
# #define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
|
||||
# #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
|
||||
|
||||
# DDR Bank 2
|
||||
# #define LAWBAR2 ((CFG_DDR_SDRAM_BASE2>>12) & 0xffffff)
|
||||
# #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
|
||||
|
||||
# LBC
|
||||
# #define LAWBAR3 ((0xe0000000>>12) & 0xffffff)
|
||||
# #define LAWAR3 (LAWAR_EN & (LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_512M)))
|
||||
|
||||
/*
|
||||
* LAW (Local Access Window) configuration:
|
||||
*
|
||||
* 0x0000_0000 DDR 256M
|
||||
* 0x1000_0000 DDR2 256M
|
||||
* 0x8000_0000 PCI1 MEM 512M
|
||||
* 0xa000_0000 PCI2 MEM 512M
|
||||
* 0xc000_0000 RapidIO 512M
|
||||
* 0xe200_0000 PCI1 IO 16M
|
||||
* 0xe300_0000 PCI2 IO 16M
|
||||
* 0xf800_0000 CCSRBAR 2M
|
||||
* 0xfe00_0000 FLASH (boot bank) 32M
|
||||
*
|
||||
*/
|
||||
|
||||
#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
|
||||
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
|
||||
|
||||
#define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff)
|
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
|
||||
|
||||
#define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff)
|
||||
#define LAWAR3 (~LAWAR_EN & (LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)))
|
||||
|
||||
#define LAWBAR4 ((0xf8000000>>12) & 0xffffff)
|
||||
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M))
|
||||
|
||||
#define LAWBAR5 ((CFG_PCI1_IO_BASE>>12) & 0xffffff)
|
||||
#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
|
||||
|
||||
#define LAWBAR6 ((CFG_PCI2_IO_BASE>>12) & 0xffffff)
|
||||
#define LAWAR6 (~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)))
|
||||
|
||||
#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff)
|
||||
#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
|
||||
|
||||
#define LAWBAR8 ((CFG_DDR_SDRAM_BASE2>>12) & 0xffffff)
|
||||
#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
|
||||
|
||||
#define LAWBAR9 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
|
||||
#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
|
||||
|
||||
.section .bootpg, "ax"
|
||||
.globl law_entry
|
||||
law_entry:
|
||||
lis r7,CFG_CCSRBAR@h
|
||||
ori r7,r7,CFG_CCSRBAR@l
|
||||
|
||||
addi r4,r7,0
|
||||
addi r5,r7,0
|
||||
|
||||
/* Skip LAWAR0, start at LAWAR1 */
|
||||
lis r6,LAWBAR1@h
|
||||
ori r6,r6,LAWBAR1@l
|
||||
stwu r6, 0xc28(r4)
|
||||
|
||||
lis r6,LAWAR1@h
|
||||
ori r6,r6,LAWAR1@l
|
||||
stwu r6, 0xc30(r5)
|
||||
|
||||
/* LAWBAR2, LAWAR2 */
|
||||
lis r6,LAWBAR2@h
|
||||
ori r6,r6,LAWBAR2@l
|
||||
stwu r6, 0x20(r4)
|
||||
|
||||
lis r6,LAWAR2@h
|
||||
ori r6,r6,LAWAR2@l
|
||||
stwu r6, 0x20(r5)
|
||||
|
||||
/* LAWBAR3, LAWAR3 */
|
||||
lis r6,LAWBAR3@h
|
||||
ori r6,r6,LAWBAR3@l
|
||||
stwu r6, 0x20(r4)
|
||||
|
||||
lis r6,LAWAR3@h
|
||||
ori r6,r6,LAWAR3@l
|
||||
stwu r6, 0x20(r5)
|
||||
|
||||
/* LAWBAR4, LAWAR4 */
|
||||
lis r6,LAWBAR4@h
|
||||
ori r6,r6,LAWBAR4@l
|
||||
stwu r6, 0x20(r4)
|
||||
|
||||
lis r6,LAWAR4@h
|
||||
ori r6,r6,LAWAR4@l
|
||||
stwu r6, 0x20(r5)
|
||||
|
||||
/* LAWBAR5, LAWAR5 */
|
||||
lis r6,LAWBAR5@h
|
||||
ori r6,r6,LAWBAR5@l
|
||||
stwu r6, 0x20(r4)
|
||||
|
||||
lis r6,LAWAR5@h
|
||||
ori r6,r6,LAWAR5@l
|
||||
stwu r6, 0x20(r5)
|
||||
|
||||
/* LAWBAR6, LAWAR6 */
|
||||
lis r6,LAWBAR6@h
|
||||
ori r6,r6,LAWBAR6@l
|
||||
stwu r6, 0x20(r4)
|
||||
|
||||
lis r6,LAWAR6@h
|
||||
ori r6,r6,LAWAR6@l
|
||||
stwu r6, 0x20(r5)
|
||||
|
||||
/* LAWBAR7, LAWAR7 */
|
||||
lis r6,LAWBAR7@h
|
||||
ori r6,r6,LAWBAR7@l
|
||||
stwu r6, 0x20(r4)
|
||||
|
||||
lis r6,LAWAR7@h
|
||||
ori r6,r6,LAWAR7@l
|
||||
stwu r6, 0x20(r5)
|
||||
|
||||
/* LAWBAR8, LAWAR8 */
|
||||
lis r6,LAWBAR8@h
|
||||
ori r6,r6,LAWBAR8@l
|
||||
stwu r6, 0x20(r4)
|
||||
|
||||
lis r6,LAWAR8@h
|
||||
ori r6,r6,LAWAR8@l
|
||||
stwu r6, 0x20(r5)
|
||||
|
||||
/* LAWBAR9, LAWAR9 */
|
||||
lis r6,LAWBAR9@h
|
||||
ori r6,r6,LAWBAR9@l
|
||||
stwu r6, 0x20(r4)
|
||||
|
||||
lis r6,LAWAR9@h
|
||||
ori r6,r6,LAWAR9@l
|
||||
stwu r6, 0x20(r5)
|
||||
|
||||
blr
|
406
board/sbc8641d/sbc8641d.c
Normal file
406
board/sbc8641d/sbc8641d.c
Normal file
|
@ -0,0 +1,406 @@
|
|||
/*
|
||||
* Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
|
||||
* Copyright 2007 Embedded Specialties, Inc.
|
||||
* Joe Hamman joe.hamman@embeddedspecialties.com
|
||||
*
|
||||
* Copyright 2004 Freescale Semiconductor.
|
||||
* Jeff Brown
|
||||
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
|
||||
*
|
||||
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <pci.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/immap_86xx.h>
|
||||
#include <asm/immap_fsl_pci.h>
|
||||
#include <spd.h>
|
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
#include <ft_build.h>
|
||||
extern void ft_cpu_setup (void *blob, bd_t * bd);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
||||
extern void ddr_enable_ecc (unsigned int dram_size);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPD_EEPROM)
|
||||
#include "spd_sdram.h"
|
||||
#endif
|
||||
|
||||
void sdram_init (void);
|
||||
long int fixed_sdram (void);
|
||||
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
puts ("Board: Wind River SBC8641D\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
long dram_size = 0;
|
||||
|
||||
#if defined(CONFIG_SPD_EEPROM)
|
||||
dram_size = spd_sdram ();
|
||||
#else
|
||||
dram_size = fixed_sdram ();
|
||||
#endif
|
||||
|
||||
#if defined(CFG_RAMBOOT)
|
||||
puts (" DDR: ");
|
||||
return dram_size;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
||||
/*
|
||||
* Initialize and enable DDR ECC.
|
||||
*/
|
||||
ddr_enable_ecc (dram_size);
|
||||
#endif
|
||||
|
||||
puts (" DDR: ");
|
||||
return dram_size;
|
||||
}
|
||||
|
||||
#if defined(CFG_DRAM_TEST)
|
||||
int testdram (void)
|
||||
{
|
||||
uint *pstart = (uint *) CFG_MEMTEST_START;
|
||||
uint *pend = (uint *) CFG_MEMTEST_END;
|
||||
uint *p;
|
||||
|
||||
puts ("SDRAM test phase 1:\n");
|
||||
for (p = pstart; p < pend; p++)
|
||||
*p = 0xaaaaaaaa;
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0xaaaaaaaa) {
|
||||
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
puts ("SDRAM test phase 2:\n");
|
||||
for (p = pstart; p < pend; p++)
|
||||
*p = 0x55555555;
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0x55555555) {
|
||||
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
puts ("SDRAM test passed.\n");
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM)
|
||||
/*
|
||||
* Fixed sdram init -- doesn't use serial presence detect.
|
||||
*/
|
||||
long int fixed_sdram (void)
|
||||
{
|
||||
#if !defined(CFG_RAMBOOT)
|
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||
volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
|
||||
|
||||
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
|
||||
ddr->cs1_bnds = CFG_DDR_CS1_BNDS;
|
||||
ddr->cs2_bnds = CFG_DDR_CS2_BNDS;
|
||||
ddr->cs3_bnds = CFG_DDR_CS3_BNDS;
|
||||
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
|
||||
ddr->cs1_config = CFG_DDR_CS1_CONFIG;
|
||||
ddr->cs2_config = CFG_DDR_CS2_CONFIG;
|
||||
ddr->cs3_config = CFG_DDR_CS3_CONFIG;
|
||||
ddr->ext_refrec = CFG_DDR_EXT_REFRESH;
|
||||
ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
|
||||
ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
|
||||
ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
|
||||
ddr->sdram_cfg_1 = CFG_DDR_CFG_1A;
|
||||
ddr->sdram_cfg_2 = CFG_DDR_CFG_2;
|
||||
ddr->sdram_mode_1 = CFG_DDR_MODE_1;
|
||||
ddr->sdram_mode_2 = CFG_DDR_MODE_2;
|
||||
ddr->sdram_mode_cntl = CFG_DDR_MODE_CTL;
|
||||
ddr->sdram_interval = CFG_DDR_INTERVAL;
|
||||
ddr->sdram_data_init = CFG_DDR_DATA_INIT;
|
||||
ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
|
||||
|
||||
asm ("sync;isync");
|
||||
|
||||
udelay (500);
|
||||
|
||||
ddr->sdram_cfg_1 = CFG_DDR_CFG_1B;
|
||||
asm ("sync; isync");
|
||||
|
||||
udelay (500);
|
||||
ddr = &immap->im_ddr2;
|
||||
|
||||
ddr->cs0_bnds = CFG_DDR2_CS0_BNDS;
|
||||
ddr->cs1_bnds = CFG_DDR2_CS1_BNDS;
|
||||
ddr->cs2_bnds = CFG_DDR2_CS2_BNDS;
|
||||
ddr->cs3_bnds = CFG_DDR2_CS3_BNDS;
|
||||
ddr->cs0_config = CFG_DDR2_CS0_CONFIG;
|
||||
ddr->cs1_config = CFG_DDR2_CS1_CONFIG;
|
||||
ddr->cs2_config = CFG_DDR2_CS2_CONFIG;
|
||||
ddr->cs3_config = CFG_DDR2_CS3_CONFIG;
|
||||
ddr->ext_refrec = CFG_DDR2_EXT_REFRESH;
|
||||
ddr->timing_cfg_0 = CFG_DDR2_TIMING_0;
|
||||
ddr->timing_cfg_1 = CFG_DDR2_TIMING_1;
|
||||
ddr->timing_cfg_2 = CFG_DDR2_TIMING_2;
|
||||
ddr->sdram_cfg_1 = CFG_DDR2_CFG_1A;
|
||||
ddr->sdram_cfg_2 = CFG_DDR2_CFG_2;
|
||||
ddr->sdram_mode_1 = CFG_DDR2_MODE_1;
|
||||
ddr->sdram_mode_2 = CFG_DDR2_MODE_2;
|
||||
ddr->sdram_mode_cntl = CFG_DDR2_MODE_CTL;
|
||||
ddr->sdram_interval = CFG_DDR2_INTERVAL;
|
||||
ddr->sdram_data_init = CFG_DDR2_DATA_INIT;
|
||||
ddr->sdram_clk_cntl = CFG_DDR2_CLK_CTRL;
|
||||
|
||||
asm ("sync;isync");
|
||||
|
||||
udelay (500);
|
||||
|
||||
ddr->sdram_cfg_1 = CFG_DDR2_CFG_1B;
|
||||
asm ("sync; isync");
|
||||
|
||||
udelay (500);
|
||||
#endif
|
||||
return CFG_SDRAM_SIZE * 1024 * 1024;
|
||||
}
|
||||
#endif /* !defined(CONFIG_SPD_EEPROM) */
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
/*
|
||||
* Initialize PCI Devices, report devices found.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_PCI_PNP
|
||||
static struct pci_config_table pci_fsl86xxads_config_table[] = {
|
||||
{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
|
||||
PCI_IDSEL_NUMBER, PCI_ANY_ID,
|
||||
pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
|
||||
PCI_ENET0_MEMADDR,
|
||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
|
||||
{}
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct pci_controller pci1_hose = {
|
||||
#ifndef CONFIG_PCI_PNP
|
||||
config_table:pci_mpc86xxcts_config_table
|
||||
#endif
|
||||
};
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#ifdef CONFIG_PCI2
|
||||
static struct pci_controller pci2_hose;
|
||||
#endif /* CONFIG_PCI2 */
|
||||
|
||||
int first_free_busno = 0;
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
|
||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
||||
uint devdisr = gur->devdisr;
|
||||
uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16;
|
||||
|
||||
#ifdef CONFIG_PCI1
|
||||
{
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pci1_hose;
|
||||
#ifdef DEBUG
|
||||
uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17;
|
||||
uint pex1_agent = (host1_agent == 0) || (host1_agent == 1);
|
||||
#endif
|
||||
if ((io_sel == 2 || io_sel == 3 || io_sel == 5
|
||||
|| io_sel == 6 || io_sel == 7 || io_sel == 0xF)
|
||||
&& !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
|
||||
debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host");
|
||||
debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det);
|
||||
if (pci->pme_msg_det) {
|
||||
pci->pme_msg_det = 0xffffffff;
|
||||
debug(" with errors. Clearing. Now 0x%08x",
|
||||
pci->pme_msg_det);
|
||||
}
|
||||
debug("\n");
|
||||
|
||||
/* inbound */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CFG_PCI_MEMORY_BUS,
|
||||
CFG_PCI_MEMORY_PHYS,
|
||||
CFG_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 1,
|
||||
CFG_PCI1_MEM_BASE,
|
||||
CFG_PCI1_MEM_PHYS,
|
||||
CFG_PCI1_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(hose->regions + 2,
|
||||
CFG_PCI1_IO_BASE,
|
||||
CFG_PCI1_IO_PHYS,
|
||||
CFG_PCI1_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 3;
|
||||
|
||||
hose->first_busno=first_free_busno;
|
||||
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
|
||||
|
||||
fsl_pci_init(hose);
|
||||
|
||||
first_free_busno=hose->last_busno+1;
|
||||
printf (" PCI-EXPRESS 1 on bus %02x - %02x\n",
|
||||
hose->first_busno,hose->last_busno);
|
||||
|
||||
} else {
|
||||
puts("PCI-EXPRESS 1: Disabled\n");
|
||||
}
|
||||
}
|
||||
#else
|
||||
puts("PCI-EXPRESS1: Disabled\n");
|
||||
#endif /* CONFIG_PCI1 */
|
||||
|
||||
#ifdef CONFIG_PCI2
|
||||
{
|
||||
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR;
|
||||
extern void fsl_pci_init(struct pci_controller *hose);
|
||||
struct pci_controller *hose = &pci2_hose;
|
||||
|
||||
|
||||
/* inbound */
|
||||
pci_set_region(hose->regions + 0,
|
||||
CFG_PCI_MEMORY_BUS,
|
||||
CFG_PCI_MEMORY_PHYS,
|
||||
CFG_PCI_MEMORY_SIZE,
|
||||
PCI_REGION_MEM | PCI_REGION_MEMORY);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(hose->regions + 1,
|
||||
CFG_PCI2_MEM_BASE,
|
||||
CFG_PCI2_MEM_PHYS,
|
||||
CFG_PCI2_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(hose->regions + 2,
|
||||
CFG_PCI2_IO_BASE,
|
||||
CFG_PCI2_IO_PHYS,
|
||||
CFG_PCI2_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = 3;
|
||||
|
||||
hose->first_busno=first_free_busno;
|
||||
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
|
||||
|
||||
fsl_pci_init(hose);
|
||||
|
||||
first_free_busno=hose->last_busno+1;
|
||||
printf (" PCI-EXPRESS 2 on bus %02x - %02x\n",
|
||||
hose->first_busno,hose->last_busno);
|
||||
}
|
||||
#else
|
||||
puts("PCI-EXPRESS 2: Disabled\n");
|
||||
#endif /* CONFIG_PCI2 */
|
||||
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
void ft_board_setup (void *blob, bd_t * bd)
|
||||
{
|
||||
u32 *p;
|
||||
int len;
|
||||
|
||||
ft_cpu_setup (blob, bd);
|
||||
|
||||
p = ft_get_prop (blob, "/memory/reg", &len);
|
||||
if (p != NULL) {
|
||||
*p++ = cpu_to_be32 (bd->bi_memstart);
|
||||
*p = cpu_to_be32 (bd->bi_memsize);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
void sbc8641d_reset_board (void)
|
||||
{
|
||||
puts ("Resetting board....\n");
|
||||
}
|
||||
|
||||
/*
|
||||
* get_board_sys_clk
|
||||
* Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
|
||||
*/
|
||||
|
||||
unsigned long get_board_sys_clk (ulong dummy)
|
||||
{
|
||||
int i;
|
||||
ulong val = 0;
|
||||
|
||||
i = 5;
|
||||
i &= 0x07;
|
||||
|
||||
switch (i) {
|
||||
case 0:
|
||||
val = 33000000;
|
||||
break;
|
||||
case 1:
|
||||
val = 40000000;
|
||||
break;
|
||||
case 2:
|
||||
val = 50000000;
|
||||
break;
|
||||
case 3:
|
||||
val = 66000000;
|
||||
break;
|
||||
case 4:
|
||||
val = 83000000;
|
||||
break;
|
||||
case 5:
|
||||
val = 100000000;
|
||||
break;
|
||||
case 6:
|
||||
val = 134000000;
|
||||
break;
|
||||
case 7:
|
||||
val = 166000000;
|
||||
break;
|
||||
}
|
||||
|
||||
return val;
|
||||
}
|
135
board/sbc8641d/u-boot.lds
Normal file
135
board/sbc8641d/u-boot.lds
Normal file
|
@ -0,0 +1,135 @@
|
|||
/*
|
||||
* Copyright 2006, 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
cpu/mpc86xx/start.o (.text)
|
||||
board/sbc8641d/init.o (.bootpg)
|
||||
cpu/mpc86xx/traps.o (.text)
|
||||
cpu/mpc86xx/interrupts.o (.text)
|
||||
cpu/mpc86xx/cpu_init.o (.text)
|
||||
cpu/mpc86xx/cpu.o (.text)
|
||||
cpu/mpc86xx/speed.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
*(.eh_frame)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
|
@ -34,7 +34,7 @@
|
|||
|
||||
#ifdef CONFIG_AUTO_UPDATE
|
||||
|
||||
#ifndef CONFIG_USB_OHCI
|
||||
#ifndef CONFIG_USB_OHCI_NEW
|
||||
#error "must define CONFIG_USB_OHCI"
|
||||
#endif
|
||||
|
||||
|
@ -450,7 +450,7 @@ do_auto_update(void)
|
|||
{
|
||||
block_dev_desc_t *stor_dev;
|
||||
long sz;
|
||||
int i, res, bitmap_first, cnt, old_ctrlc, got_ctrlc;
|
||||
int i, res = 0, bitmap_first, cnt, old_ctrlc, got_ctrlc;
|
||||
char *env;
|
||||
long start, end;
|
||||
|
||||
|
@ -477,18 +477,21 @@ do_auto_update(void)
|
|||
au_usb_stor_curr_dev = usb_stor_scan(0);
|
||||
if (au_usb_stor_curr_dev == -1) {
|
||||
debug ("No device found. Not initialized?\n");
|
||||
return -1;
|
||||
res = -1;
|
||||
goto xit;
|
||||
}
|
||||
/* check whether it has a partition table */
|
||||
stor_dev = get_dev("usb", 0);
|
||||
if (stor_dev == NULL) {
|
||||
debug ("uknown device type\n");
|
||||
return -1;
|
||||
res = -1;
|
||||
goto xit;
|
||||
}
|
||||
if (fat_register_device(stor_dev, 1) != 0) {
|
||||
debug ("Unable to use USB %d:%d for fatls\n",
|
||||
au_usb_stor_curr_dev, 1);
|
||||
return -1;
|
||||
res = -1;
|
||||
goto xit;
|
||||
}
|
||||
if (file_fat_detectfs() != 0) {
|
||||
debug ("file_fat_detectfs failed\n");
|
||||
|
@ -648,9 +651,10 @@ do_auto_update(void)
|
|||
/* enable the power switch */
|
||||
*CPLD_VFD_BK &= ~POWER_OFF;
|
||||
}
|
||||
usb_stop();
|
||||
/* restore the old state */
|
||||
disable_ctrlc(old_ctrlc);
|
||||
return 0;
|
||||
xit:
|
||||
usb_stop();
|
||||
return res;
|
||||
}
|
||||
#endif /* CONFIG_AUTO_UPDATE */
|
||||
|
|
51
board/zeus/Makefile
Normal file
51
board/zeus/Makefile
Normal file
|
@ -0,0 +1,51 @@
|
|||
#
|
||||
# (C) Copyright 2007
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o update.o
|
||||
SOBJS =
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
24
board/zeus/config.mk
Normal file
24
board/zeus/config.mk
Normal file
|
@ -0,0 +1,24 @@
|
|||
#
|
||||
# (C) Copyright 2000
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
TEXT_BASE = 0xFFFC0000
|
133
board/zeus/u-boot.lds
Normal file
133
board/zeus/u-boot.lds
Normal file
|
@ -0,0 +1,133 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
.resetvec 0xFFFFFFFC :
|
||||
{
|
||||
*(.resetvec)
|
||||
} = 0xffff
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
105
board/zeus/update.c
Normal file
105
board/zeus/update.c
Normal file
|
@ -0,0 +1,105 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <i2c.h>
|
||||
|
||||
#if defined(CONFIG_ZEUS)
|
||||
|
||||
u8 buf_zeus_ce[] = {
|
||||
/*00 01 02 03 04 05 06 07 */
|
||||
0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/*08 09 0a 0b 0c 0d 0e 0f */
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/*10 11 12 13 14 15 16 17 */
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/*18 19 1a 1b 1c 1d 1e 1f */
|
||||
0x00, 0xc0, 0x50, 0x12, 0x72, 0x3e, 0x00, 0x00 };
|
||||
|
||||
u8 buf_zeus_pe[] = {
|
||||
|
||||
/* CPU_CLOCK_DIV 1 = 00
|
||||
CPU_PLB_FREQ_DIV 3 = 10
|
||||
OPB_PLB_FREQ_DIV 2 = 01
|
||||
EBC_PLB_FREQ_DIV 2 = 00
|
||||
MAL_PLB_FREQ_DIV 1 = 00
|
||||
PCI_PLB_FRQ_DIV 3 = 10
|
||||
PLL_PLLOUTA = IS SET
|
||||
PLL_OPERATING = IS NOT SET
|
||||
PLL_FDB_MUL 10 = 1010
|
||||
PLL_FWD_DIV_A 3 = 101
|
||||
PLL_FWD_DIV_B 3 = 101
|
||||
TUNE = 0x2be */
|
||||
/*00 01 02 03 04 05 06 07 */
|
||||
0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/*08 09 0a 0b 0c 0d 0e 0f */
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/*10 11 12 13 14 15 16 17 */
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
/*18 19 1a 1b 1c 1d 1e 1f */
|
||||
0x00, 0x60, 0x68, 0x2d, 0x42, 0xbe, 0x00, 0x00 };
|
||||
|
||||
static int update_boot_eeprom(void)
|
||||
{
|
||||
u32 len = 0x20;
|
||||
u8 chip = CFG_I2C_EEPROM_ADDR;
|
||||
u8 *pbuf;
|
||||
u8 base;
|
||||
int i;
|
||||
|
||||
if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_ZEUS_PE)) {
|
||||
pbuf = buf_zeus_pe;
|
||||
base = 0x40;
|
||||
} else {
|
||||
pbuf = buf_zeus_ce;
|
||||
base = 0x00;
|
||||
}
|
||||
|
||||
for (i = 0; i < len; i++, base++) {
|
||||
if (i2c_write(chip, base, 1, &pbuf[i], 1) != 0) {
|
||||
printf("i2c_write fail\n");
|
||||
return 1;
|
||||
}
|
||||
udelay(11000);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int do_update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[])
|
||||
{
|
||||
return update_boot_eeprom();
|
||||
}
|
||||
|
||||
U_BOOT_CMD (
|
||||
update_boot_eeprom, 1, 1, do_update_boot_eeprom,
|
||||
"update_boot_eeprom - update boot eeprom content\n",
|
||||
NULL
|
||||
);
|
||||
|
||||
#endif
|
511
board/zeus/zeus.c
Normal file
511
board/zeus/zeus.c
Normal file
|
@ -0,0 +1,511 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <malloc.h>
|
||||
#include <environment.h>
|
||||
#include <logbuff.h>
|
||||
#include <post.h>
|
||||
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/gpio.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define REBOOT_MAGIC 0x07081967
|
||||
#define REBOOT_NOP 0x00000000
|
||||
#define REBOOT_DO_POST 0x00000001
|
||||
|
||||
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
extern env_t *env_ptr;
|
||||
extern uchar default_environment[];
|
||||
|
||||
ulong flash_get_size(ulong base, int banknum);
|
||||
void env_crc_update(void);
|
||||
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
|
||||
|
||||
static u32 start_time;
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
|
||||
mtdcr(uicer, 0x00000000); /* disable all ints */
|
||||
mtdcr(uiccr, 0x00000000);
|
||||
mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */
|
||||
mtdcr(uictr, 0x00000000); /* set int trigger levels */
|
||||
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
|
||||
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
|
||||
|
||||
/*
|
||||
* Configure CPC0_PCI to enable PerWE as output
|
||||
*/
|
||||
mtdcr(cpc0_pci, CPC0_PCI_SPE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
u32 pbcr;
|
||||
int size_val = 0;
|
||||
u32 post_magic;
|
||||
u32 post_val;
|
||||
|
||||
post_magic = in_be32((void *)CFG_POST_MAGIC);
|
||||
post_val = in_be32((void *)CFG_POST_VAL);
|
||||
if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST)) {
|
||||
/*
|
||||
* Set special bootline bootparameter to pass this POST boot
|
||||
* mode to Linux to reset the username/password
|
||||
*/
|
||||
setenv("addmisc", "setenv bootargs \\${bootargs} factory_reset=yes");
|
||||
|
||||
/*
|
||||
* Normally don't run POST tests, only when enabled
|
||||
* via the sw-reset button. So disable further tests
|
||||
* upon next bootup here.
|
||||
*/
|
||||
out_be32((void *)CFG_POST_VAL, REBOOT_NOP);
|
||||
} else {
|
||||
/*
|
||||
* Only run POST when initiated via the sw-reset button mechanism
|
||||
*/
|
||||
post_word_store(0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Get current time
|
||||
*/
|
||||
start_time = get_timer(0);
|
||||
|
||||
/*
|
||||
* FLASH stuff...
|
||||
*/
|
||||
|
||||
/* Re-do sizing to get full correct info */
|
||||
|
||||
/* adjust flash start and offset */
|
||||
mfebc(pb0cr, pbcr);
|
||||
switch (gd->bd->bi_flashsize) {
|
||||
case 1 << 20:
|
||||
size_val = 0;
|
||||
break;
|
||||
case 2 << 20:
|
||||
size_val = 1;
|
||||
break;
|
||||
case 4 << 20:
|
||||
size_val = 2;
|
||||
break;
|
||||
case 8 << 20:
|
||||
size_val = 3;
|
||||
break;
|
||||
case 16 << 20:
|
||||
size_val = 4;
|
||||
break;
|
||||
case 32 << 20:
|
||||
size_val = 5;
|
||||
break;
|
||||
case 64 << 20:
|
||||
size_val = 6;
|
||||
break;
|
||||
case 128 << 20:
|
||||
size_val = 7;
|
||||
break;
|
||||
}
|
||||
pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
|
||||
mtebc(pb0cr, pbcr);
|
||||
|
||||
/*
|
||||
* Re-check to get correct base address
|
||||
*/
|
||||
flash_get_size(gd->bd->bi_flashstart, 0);
|
||||
|
||||
/* Monitor protection ON by default */
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
-CFG_MONITOR_LEN,
|
||||
0xffffffff,
|
||||
&flash_info[0]);
|
||||
|
||||
/* Env protection ON by default */
|
||||
(void)flash_protect(FLAG_PROTECT_SET,
|
||||
CFG_ENV_ADDR_REDUND,
|
||||
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
|
||||
&flash_info[0]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
int checkboard(void)
|
||||
{
|
||||
char *s = getenv("serial#");
|
||||
|
||||
puts("Board: Zeus-");
|
||||
|
||||
if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_ZEUS_PE))
|
||||
puts("PE");
|
||||
else
|
||||
puts("CE");
|
||||
|
||||
puts(" of BulletEndPoint");
|
||||
|
||||
if (s != NULL) {
|
||||
puts(", serial# ");
|
||||
puts(s);
|
||||
}
|
||||
putc('\n');
|
||||
|
||||
/* both LED's off */
|
||||
gpio_write_bit(CFG_GPIO_LED_RED, 0);
|
||||
gpio_write_bit(CFG_GPIO_LED_GREEN, 0);
|
||||
udelay(10000);
|
||||
/* and on again */
|
||||
gpio_write_bit(CFG_GPIO_LED_RED, 1);
|
||||
gpio_write_bit(CFG_GPIO_LED_GREEN, 1);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static u32 detect_sdram_size(void)
|
||||
{
|
||||
u32 val;
|
||||
u32 size;
|
||||
|
||||
mfsdram(mem_mb0cf, val);
|
||||
size = (4 << 20) << ((val & 0x000e0000) >> 17);
|
||||
|
||||
/*
|
||||
* Check if 2nd bank is enabled too
|
||||
*/
|
||||
mfsdram(mem_mb1cf, val);
|
||||
if (val & 1)
|
||||
size += (4 << 20) << ((val & 0x000e0000) >> 17);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
return detect_sdram_size();
|
||||
}
|
||||
|
||||
#if defined(CFG_DRAM_TEST)
|
||||
int testdram(void)
|
||||
{
|
||||
unsigned long *mem = (unsigned long *)0;
|
||||
const unsigned long kend = (1024 / sizeof(unsigned long));
|
||||
unsigned long k, n;
|
||||
unsigned long msr;
|
||||
unsigned long total_kbytes;
|
||||
|
||||
total_kbytes = detect_sdram_size();
|
||||
|
||||
msr = mfmsr();
|
||||
mtmsr(msr & ~(MSR_EE));
|
||||
|
||||
for (k = 0; k < total_kbytes ;
|
||||
++k, mem += (1024 / sizeof(unsigned long))) {
|
||||
if ((k & 1023) == 0) {
|
||||
printf("%3d MB\r", k / 1024);
|
||||
}
|
||||
|
||||
memset(mem, 0xaaaaaaaa, 1024);
|
||||
for (n = 0; n < kend; ++n) {
|
||||
if (mem[n] != 0xaaaaaaaa) {
|
||||
printf("SDRAM test fails at: %08x\n",
|
||||
(uint) & mem[n]);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
memset(mem, 0x55555555, 1024);
|
||||
for (n = 0; n < kend; ++n) {
|
||||
if (mem[n] != 0x55555555) {
|
||||
printf("SDRAM test fails at: %08x\n",
|
||||
(uint) & mem[n]);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
printf("SDRAM test passes\n");
|
||||
mtmsr(msr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int default_env_var(char *buf, char *var)
|
||||
{
|
||||
char *ptr;
|
||||
char *val;
|
||||
|
||||
/*
|
||||
* Find env variable
|
||||
*/
|
||||
ptr = strstr(buf + 4, var);
|
||||
if (ptr == NULL) {
|
||||
printf("ERROR: %s not found!\n", var);
|
||||
return -1;
|
||||
}
|
||||
ptr += strlen(var) + 1;
|
||||
|
||||
/*
|
||||
* Now the ethaddr needs to be updated in the "normal"
|
||||
* environment storage -> redundant flash.
|
||||
*/
|
||||
val = ptr;
|
||||
setenv(var, val);
|
||||
printf("Updated %s from eeprom to %s!\n", var, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int restore_default(void)
|
||||
{
|
||||
char *buf;
|
||||
char *buf_save;
|
||||
u32 crc;
|
||||
|
||||
/*
|
||||
* Unprotect and erase environment area
|
||||
*/
|
||||
flash_protect(FLAG_PROTECT_CLEAR,
|
||||
CFG_ENV_ADDR_REDUND,
|
||||
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
|
||||
&flash_info[0]);
|
||||
|
||||
flash_sect_erase(CFG_ENV_ADDR_REDUND,
|
||||
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1);
|
||||
|
||||
/*
|
||||
* Now restore default environment from U-Boot image
|
||||
* -> ipaddr, serverip...
|
||||
*/
|
||||
memset(env_ptr, 0, sizeof(env_t));
|
||||
memcpy(env_ptr->data, default_environment, ENV_SIZE);
|
||||
#ifdef CFG_REDUNDAND_ENVIRONMENT
|
||||
env_ptr->flags = 0xFF;
|
||||
#endif
|
||||
env_crc_update();
|
||||
gd->env_valid = 1;
|
||||
|
||||
/*
|
||||
* Read board specific values from I2C EEPROM
|
||||
* and set env variables accordingly
|
||||
* -> ethaddr, eth1addr, serial#
|
||||
*/
|
||||
buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE);
|
||||
if (eeprom_read(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS,
|
||||
(u8 *)buf, FACTORY_RESET_ENV_SIZE)) {
|
||||
puts("\nError reading EEPROM!\n");
|
||||
} else {
|
||||
crc = crc32(0, (u8 *)(buf + 4), FACTORY_RESET_ENV_SIZE - 4);
|
||||
if (crc != *(u32 *)buf) {
|
||||
printf("ERROR: crc mismatch %08lx %08lx\n", crc, *(u32 *)buf);
|
||||
return -1;
|
||||
}
|
||||
|
||||
default_env_var(buf, "ethaddr");
|
||||
buf += 8 + 18;
|
||||
default_env_var(buf, "eth1addr");
|
||||
buf += 9 + 18;
|
||||
default_env_var(buf, "serial#");
|
||||
}
|
||||
|
||||
/*
|
||||
* Finally save updated env variables back to flash
|
||||
*/
|
||||
saveenv();
|
||||
|
||||
free(buf_save);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int do_set_default(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
char *buf;
|
||||
char *buf_save;
|
||||
char str[32];
|
||||
u32 crc;
|
||||
char var[32];
|
||||
|
||||
if (argc < 4) {
|
||||
puts("ERROR!\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE);
|
||||
memset(buf, 0, FACTORY_RESET_ENV_SIZE);
|
||||
|
||||
strcpy(var, "ethaddr");
|
||||
printf("Setting %s to %s\n", var, argv[1]);
|
||||
sprintf(str, "%s=%s", var, argv[1]);
|
||||
strcpy(buf + 4, str);
|
||||
buf += strlen(str) + 1;
|
||||
|
||||
strcpy(var, "eth1addr");
|
||||
printf("Setting %s to %s\n", var, argv[2]);
|
||||
sprintf(str, "%s=%s", var, argv[2]);
|
||||
strcpy(buf + 4, str);
|
||||
buf += strlen(str) + 1;
|
||||
|
||||
strcpy(var, "serial#");
|
||||
printf("Setting %s to %s\n", var, argv[3]);
|
||||
sprintf(str, "%s=%s", var, argv[3]);
|
||||
strcpy(buf + 4, str);
|
||||
|
||||
crc = crc32(0, (u8 *)(buf_save + 4), FACTORY_RESET_ENV_SIZE - 4);
|
||||
*(u32 *)buf_save = crc;
|
||||
|
||||
if (eeprom_write(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS,
|
||||
(u8 *)buf_save, FACTORY_RESET_ENV_SIZE)) {
|
||||
puts("\nError writing EEPROM!\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
free(buf_save);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
setdef, 4, 1, do_set_default,
|
||||
"setdef - write board-specific values to EEPROM (ethaddr...)\n",
|
||||
"ethaddr eth1addr serial#\n - write board-specific values to EEPROM\n"
|
||||
);
|
||||
|
||||
static inline int sw_reset_pressed(void)
|
||||
{
|
||||
return !(in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_SW_RESET));
|
||||
}
|
||||
|
||||
int do_chkreset(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[])
|
||||
{
|
||||
int delta;
|
||||
int count = 0;
|
||||
int post = 0;
|
||||
int factory_reset = 0;
|
||||
|
||||
if (!sw_reset_pressed()) {
|
||||
printf("SW-Reset already high (Button released)\n");
|
||||
printf("-> No action taken!\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
printf("Waiting for SW-Reset button to be released.");
|
||||
|
||||
while (1) {
|
||||
delta = get_timer(start_time);
|
||||
if (!sw_reset_pressed())
|
||||
break;
|
||||
|
||||
if ((delta > CFG_TIME_POST) && !post) {
|
||||
printf("\nWhen released now, POST tests will be started.");
|
||||
gpio_write_bit(CFG_GPIO_LED_GREEN, 0);
|
||||
post = 1;
|
||||
}
|
||||
|
||||
if ((delta > CFG_TIME_FACTORY_RESET) && !factory_reset) {
|
||||
printf("\nWhen released now, factory default values"
|
||||
" will be restored.");
|
||||
gpio_write_bit(CFG_GPIO_LED_RED, 0);
|
||||
factory_reset = 1;
|
||||
}
|
||||
|
||||
udelay(1000);
|
||||
if (!(count++ % 1000))
|
||||
printf(".");
|
||||
}
|
||||
|
||||
|
||||
printf("\nSW-Reset Button released after %d milli-seconds!\n", delta);
|
||||
|
||||
if (delta > CFG_TIME_FACTORY_RESET) {
|
||||
printf("Starting factory reset value restoration...\n");
|
||||
|
||||
/*
|
||||
* Restore default setting
|
||||
*/
|
||||
restore_default();
|
||||
|
||||
/*
|
||||
* Reset the board for default to become valid
|
||||
*/
|
||||
do_reset(NULL, 0, 0, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (delta > CFG_TIME_POST) {
|
||||
printf("Starting POST configuration...\n");
|
||||
|
||||
/*
|
||||
* Enable POST upon next bootup
|
||||
*/
|
||||
out_be32((void *)CFG_POST_MAGIC, REBOOT_MAGIC);
|
||||
out_be32((void *)CFG_POST_VAL, REBOOT_DO_POST);
|
||||
post_bootmode_init();
|
||||
|
||||
/*
|
||||
* Reset the logbuffer for a clean start
|
||||
*/
|
||||
logbuff_reset();
|
||||
|
||||
do_reset(NULL, 0, 0, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD (
|
||||
chkreset, 1, 1, do_chkreset,
|
||||
"chkreset- Check for status of SW-reset button and act accordingly\n",
|
||||
NULL
|
||||
);
|
||||
|
||||
#if defined(CONFIG_POST)
|
||||
/*
|
||||
* Returns 1 if keys pressed to start the power-on long-running tests
|
||||
* Called from board_init_f().
|
||||
*/
|
||||
int post_hotkeys_pressed(void)
|
||||
{
|
||||
u32 post_magic;
|
||||
u32 post_val;
|
||||
|
||||
post_magic = in_be32((void *)CFG_POST_MAGIC);
|
||||
post_val = in_be32((void *)CFG_POST_VAL);
|
||||
|
||||
if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST))
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_POST */
|
|
@ -45,8 +45,8 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*cmd_boot.c*/
|
||||
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
|
||||
/*cmd_boot.c*/
|
||||
extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
|
||||
|
||||
#if defined(CONFIG_TIMESTAMP) || defined(CONFIG_CMD_DATE)
|
||||
#include <rtc.h>
|
||||
|
@ -362,7 +362,6 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
if (i != BZ_OK) {
|
||||
printf ("BUNZIP2 ERROR %d - must RESET board to recover\n", i);
|
||||
show_boot_progress (-6);
|
||||
udelay(100000);
|
||||
do_reset (cmdtp, flag, argc, argv);
|
||||
}
|
||||
break;
|
||||
|
@ -741,59 +740,65 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
|
|||
if(argc > 3) {
|
||||
of_flat_tree = (char *) simple_strtoul(argv[3], NULL, 16);
|
||||
hdr = (image_header_t *)of_flat_tree;
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
if (fdt_check_header(of_flat_tree) == 0) {
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
if (*((ulong *)(of_flat_tree + sizeof(image_header_t))) != OF_DT_HEADER) {
|
||||
#else
|
||||
if (*(ulong *)of_flat_tree == OF_DT_HEADER) {
|
||||
if (fdt_check_header(of_flat_tree + sizeof(image_header_t)) != 0) {
|
||||
#endif
|
||||
#ifndef CFG_NO_FLASH
|
||||
if (addr2info((ulong)of_flat_tree) != NULL)
|
||||
of_data = (ulong)of_flat_tree;
|
||||
#endif
|
||||
} else if (ntohl(hdr->ih_magic) == IH_MAGIC) {
|
||||
printf("## Flat Device Tree Image at %08lX\n", hdr);
|
||||
printf("## Flat Device Tree at %08lX\n", hdr);
|
||||
print_image_hdr(hdr);
|
||||
|
||||
if ((ntohl(hdr->ih_load) < ((unsigned long)hdr + ntohl(hdr->ih_size) + sizeof(hdr))) &&
|
||||
((ntohl(hdr->ih_load) + ntohl(hdr->ih_size)) > (unsigned long)hdr)) {
|
||||
printf ("ERROR: Load address overwrites Flat Device Tree uImage\n");
|
||||
return;
|
||||
puts ("ERROR: fdt overwritten - "
|
||||
"must RESET the board to recover.\n");
|
||||
do_reset (cmdtp, flag, argc, argv);
|
||||
}
|
||||
|
||||
printf(" Verifying Checksum ... ");
|
||||
puts (" Verifying Checksum ... ");
|
||||
memmove (&header, (char *)hdr, sizeof(image_header_t));
|
||||
checksum = ntohl(header.ih_hcrc);
|
||||
header.ih_hcrc = 0;
|
||||
|
||||
if(checksum != crc32(0, (uchar *)&header, sizeof(image_header_t))) {
|
||||
printf("ERROR: Flat Device Tree header checksum is invalid\n");
|
||||
return;
|
||||
puts ("ERROR: fdt header checksum invalid - "
|
||||
"must RESET the board to recover.\n");
|
||||
do_reset (cmdtp, flag, argc, argv);
|
||||
}
|
||||
|
||||
checksum = ntohl(hdr->ih_dcrc);
|
||||
addr = (ulong)((uchar *)(hdr) + sizeof(image_header_t));
|
||||
|
||||
if(checksum != crc32(0, (uchar *)addr, ntohl(hdr->ih_size))) {
|
||||
printf("ERROR: Flat Device Tree checksum is invalid\n");
|
||||
return;
|
||||
puts ("ERROR: fdt checksum invalid - "
|
||||
"must RESET the board to recover.\n");
|
||||
do_reset (cmdtp, flag, argc, argv);
|
||||
}
|
||||
printf("OK\n");
|
||||
puts ("OK\n");
|
||||
|
||||
if (ntohl(hdr->ih_type) != IH_TYPE_FLATDT) {
|
||||
printf ("ERROR: uImage not Flat Device Tree type\n");
|
||||
return;
|
||||
puts ("ERROR: uImage is not a fdt - "
|
||||
"must RESET the board to recover.\n");
|
||||
do_reset (cmdtp, flag, argc, argv);
|
||||
}
|
||||
if (ntohl(hdr->ih_comp) != IH_COMP_NONE) {
|
||||
printf("ERROR: uImage is not uncompressed\n");
|
||||
return;
|
||||
puts ("ERROR: uImage is compressed - "
|
||||
"must RESET the board to recover.\n");
|
||||
do_reset (cmdtp, flag, argc, argv);
|
||||
}
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
if (fdt_check_header(of_flat_tree + sizeof(image_header_t)) == 0) {
|
||||
#else
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
if (*((ulong *)(of_flat_tree + sizeof(image_header_t))) != OF_DT_HEADER) {
|
||||
#else
|
||||
if (fdt_check_header(of_flat_tree + sizeof(image_header_t)) != 0) {
|
||||
#endif
|
||||
printf ("ERROR: uImage data is not a flat device tree\n");
|
||||
return;
|
||||
puts ("ERROR: uImage data is not a fdt - "
|
||||
"must RESET the board to recover.\n");
|
||||
do_reset (cmdtp, flag, argc, argv);
|
||||
}
|
||||
|
||||
memmove((void *)ntohl(hdr->ih_load),
|
||||
|
@ -801,10 +806,11 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
|
|||
ntohl(hdr->ih_size));
|
||||
of_flat_tree = (char *)ntohl(hdr->ih_load);
|
||||
} else {
|
||||
printf ("Did not find a flat flat device tree at address %08lX\n", of_flat_tree);
|
||||
return;
|
||||
puts ("Did not find a flat Flat Device Tree.\n"
|
||||
"Must RESET the board to recover.\n");
|
||||
do_reset (cmdtp, flag, argc, argv);
|
||||
}
|
||||
printf (" Booting using flat device tree at 0x%x\n",
|
||||
printf (" Booting using the fdt at 0x%x\n",
|
||||
of_flat_tree);
|
||||
} else if ((hdr->ih_type==IH_TYPE_MULTI) && (len_ptr[1]) && (len_ptr[2])) {
|
||||
u_long tail = ntohl(len_ptr[0]) % 4;
|
||||
|
@ -828,22 +834,24 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
|
|||
of_data += 4 - tail;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
if (fdt_check_header((void *)of_data) != 0) {
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
if (*((ulong *)(of_flat_tree + sizeof(image_header_t))) != OF_DT_HEADER) {
|
||||
#else
|
||||
if (((struct boot_param_header *)of_data)->magic != OF_DT_HEADER) {
|
||||
if (fdt_check_header(of_flat_tree + sizeof(image_header_t)) != 0) {
|
||||
#endif
|
||||
printf ("ERROR: image is not a flat device tree\n");
|
||||
return;
|
||||
puts ("ERROR: image is not a fdt - "
|
||||
"must RESET the board to recover.\n");
|
||||
do_reset (cmdtp, flag, argc, argv);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
if (be32_to_cpu(fdt_totalsize(of_data)) != ntohl(len_ptr[2])) {
|
||||
#else
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
if (((struct boot_param_header *)of_data)->totalsize != ntohl(len_ptr[2])) {
|
||||
#else
|
||||
if (be32_to_cpu(fdt_totalsize(of_data)) != ntohl(len_ptr[2])) {
|
||||
#endif
|
||||
printf ("ERROR: flat device tree size does not agree with image\n");
|
||||
return;
|
||||
puts ("ERROR: fdt size != image size - "
|
||||
"must RESET the board to recover.\n");
|
||||
do_reset (cmdtp, flag, argc, argv);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
@ -916,27 +924,26 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
|
|||
initrd_end = 0;
|
||||
}
|
||||
|
||||
debug ("## Transferring control to Linux (at address %08lx) ...\n",
|
||||
(ulong)kernel);
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
|
||||
show_boot_progress (15);
|
||||
|
||||
#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500)
|
||||
unlock_ram_in_cache();
|
||||
#ifdef CFG_BOOTMAPSZ
|
||||
/*
|
||||
* The blob must be within CFG_BOOTMAPSZ,
|
||||
* so we flag it to be copied if it is not.
|
||||
*/
|
||||
if (of_flat_tree >= (char *)CFG_BOOTMAPSZ)
|
||||
of_data = of_flat_tree;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
/* move of_flat_tree if needed */
|
||||
if (of_data) {
|
||||
int err;
|
||||
ulong of_start, of_len;
|
||||
|
||||
of_len = be32_to_cpu(fdt_totalsize(of_data));
|
||||
/* position on a 4K boundary before the initrd/kbd */
|
||||
if (initrd_start)
|
||||
of_start = initrd_start - of_len;
|
||||
else
|
||||
of_start = (ulong)kbd - of_len;
|
||||
|
||||
/* position on a 4K boundary before the kbd */
|
||||
of_start = (ulong)kbd - of_len;
|
||||
of_start &= ~(4096 - 1); /* align on page */
|
||||
debug ("## device tree at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n",
|
||||
of_data, of_data + of_len - 1, of_len, of_len);
|
||||
|
@ -944,42 +951,49 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
|
|||
of_flat_tree = (char *)of_start;
|
||||
printf (" Loading Device Tree to %08lx, end %08lx ... ",
|
||||
of_start, of_start + of_len - 1);
|
||||
err = fdt_open_into((void *)of_start, (void *)of_data, of_len);
|
||||
err = fdt_open_into((void *)of_data, (void *)of_start, of_len);
|
||||
if (err != 0) {
|
||||
printf ("libfdt: %s " __FILE__ " %d\n", fdt_strerror(err), __LINE__);
|
||||
}
|
||||
/*
|
||||
* Add the chosen node if it doesn't exist, add the env and bd_t
|
||||
* if the user wants it (the logic is in the subroutines).
|
||||
*/
|
||||
if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) {
|
||||
printf("Failed creating the /chosen node (0x%08X), aborting.\n", of_flat_tree);
|
||||
return;
|
||||
puts ("ERROR: fdt move failed - "
|
||||
"must RESET the board to recover.\n");
|
||||
do_reset (cmdtp, flag, argc, argv);
|
||||
}
|
||||
}
|
||||
/*
|
||||
* Add the chosen node if it doesn't exist, add the env and bd_t
|
||||
* if the user wants it (the logic is in the subroutines).
|
||||
*/
|
||||
if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) {
|
||||
puts ("ERROR: /chosen node create failed - "
|
||||
"must RESET the board to recover.\n");
|
||||
do_reset (cmdtp, flag, argc, argv);
|
||||
}
|
||||
#ifdef CONFIG_OF_HAS_UBOOT_ENV
|
||||
if (fdt_env(of_flat_tree) < 0) {
|
||||
printf("Failed creating the /u-boot-env node, aborting.\n");
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_OF_HAS_BD_T
|
||||
if (fdt_bd_t(of_flat_tree) < 0) {
|
||||
printf("Failed creating the /bd_t node, aborting.\n");
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
if (fdt_env(of_flat_tree) < 0) {
|
||||
puts ("ERROR: /u-boot-env node create failed - "
|
||||
"must RESET the board to recover.\n");
|
||||
do_reset (cmdtp, flag, argc, argv);
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_OF_HAS_BD_T
|
||||
if (fdt_bd_t(of_flat_tree) < 0) {
|
||||
puts ("ERROR: /bd_t node create failed - "
|
||||
"must RESET the board to recover.\n");
|
||||
do_reset (cmdtp, flag, argc, argv);
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_OF_BOARD_SETUP
|
||||
/* Call the board-specific fixup routine */
|
||||
ft_board_setup(of_flat_tree, gd->bd);
|
||||
#endif
|
||||
#endif /* CONFIG_OF_LIBFDT */
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
/* move of_flat_tree if needed */
|
||||
if (of_data) {
|
||||
ulong of_start, of_len;
|
||||
of_len = ((struct boot_param_header *)of_data)->totalsize;
|
||||
|
||||
/* provide extra 8k pad */
|
||||
if (initrd_start)
|
||||
of_start = initrd_start - of_len - 8192;
|
||||
else
|
||||
of_start = (ulong)kbd - of_len - 8192;
|
||||
of_start = (ulong)kbd - of_len - 8192;
|
||||
of_start &= ~(4096 - 1); /* align on page */
|
||||
debug ("## device tree at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n",
|
||||
of_data, of_data + of_len - 1, of_len, of_len);
|
||||
|
@ -989,8 +1003,36 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
|
|||
of_start, of_start + of_len - 1);
|
||||
memmove ((void *)of_start, (void *)of_data, of_len);
|
||||
}
|
||||
/*
|
||||
* Create the /chosen node and modify the blob with board specific
|
||||
* values as needed.
|
||||
*/
|
||||
ft_setup(of_flat_tree, kbd, initrd_start, initrd_end);
|
||||
/* ft_dump_blob(of_flat_tree); */
|
||||
#endif
|
||||
debug ("## Transferring control to Linux (at address %08lx) ...\n",
|
||||
(ulong)kernel);
|
||||
|
||||
show_boot_progress (15);
|
||||
|
||||
#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500)
|
||||
unlock_ram_in_cache();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)
|
||||
if (of_flat_tree) { /* device tree; boot new style */
|
||||
/*
|
||||
* Linux Kernel Parameters (passing device tree):
|
||||
* r3: pointer to the fdt, followed by the board info data
|
||||
* r4: physical pointer to the kernel itself
|
||||
* r5: NULL
|
||||
* r6: NULL
|
||||
* r7: NULL
|
||||
*/
|
||||
(*kernel) ((bd_t *)of_flat_tree, (ulong)kernel, 0, 0, 0);
|
||||
/* does not return */
|
||||
}
|
||||
#endif
|
||||
/*
|
||||
* Linux Kernel Parameters (passing board info data):
|
||||
* r3: ptr to board info data
|
||||
|
@ -999,46 +1041,8 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
|
|||
* r6: Start of command line string
|
||||
* r7: End of command line string
|
||||
*/
|
||||
#if defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)
|
||||
if (!of_flat_tree) /* no device tree; boot old style */
|
||||
#endif
|
||||
(*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end);
|
||||
/* does not return */
|
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)
|
||||
/*
|
||||
* Linux Kernel Parameters (passing device tree):
|
||||
* r3: ptr to OF flat tree, followed by the board info data
|
||||
* r4: physical pointer to the kernel itself
|
||||
* r5: NULL
|
||||
* r6: NULL
|
||||
* r7: NULL
|
||||
*/
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
ft_setup(of_flat_tree, kbd, initrd_start, initrd_end);
|
||||
/* ft_dump_blob(of_flat_tree); */
|
||||
#endif
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) {
|
||||
printf("Failed creating the /chosen node (0x%08X), aborting.\n", of_flat_tree);
|
||||
return;
|
||||
}
|
||||
#ifdef CONFIG_OF_HAS_UBOOT_ENV
|
||||
if (fdt_env(of_flat_tree) < 0) {
|
||||
printf("Failed creating the /u-boot-env node, aborting.\n");
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_OF_HAS_BD_T
|
||||
if (fdt_bd_t(of_flat_tree) < 0) {
|
||||
printf("Failed creating the /bd_t node, aborting.\n");
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
#endif /* if defined(CONFIG_OF_LIBFDT) */
|
||||
|
||||
(*kernel) ((bd_t *)of_flat_tree, (ulong)kernel, 0, 0, 0);
|
||||
#endif
|
||||
(*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end);
|
||||
/* does not return */
|
||||
}
|
||||
#endif /* CONFIG_PPC */
|
||||
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue