Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
This commit is contained in:
commit
1a1e6bf12b
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2007-2009 Freescale Semiconductor, Inc.
|
||||
* Copyright 2007-2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* (C) Copyright 2003 Motorola Inc.
|
||||
* Modified by Xianghua Xiao, X.Xiao@motorola.com
|
||||
|
@ -30,9 +30,11 @@
|
|||
#include <watchdog.h>
|
||||
#include <asm/processor.h>
|
||||
#include <ioports.h>
|
||||
#include <sata.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
#include "mp.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
@ -418,3 +420,13 @@ void arch_preboot_os(void)
|
|||
|
||||
setup_ivors();
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
|
||||
int sata_initialize(void)
|
||||
{
|
||||
if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
|
||||
return __sata_initialize();
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -1,17 +1,31 @@
|
|||
/*
|
||||
* Copyright (C) 2008 Freescale Semicondutor, Inc.
|
||||
* Copyright 2008,2010 Freescale Semiconductor, Inc.
|
||||
* Dave Liu <daveliu@freescale.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/immap_85xx.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
|
||||
/* PORDEVSR register */
|
||||
#define GUTS_PORDEVSR_OFFS 0xc
|
||||
|
@ -52,6 +66,61 @@
|
|||
#define FSL_SRDSCR3_LANEE_SGMII 0x00000000
|
||||
#define FSL_SRDSCR3_LANEE_SATA 0x00150005
|
||||
|
||||
|
||||
#define SRDS1_MAX_LANES 8
|
||||
#define SRDS2_MAX_LANES 2
|
||||
|
||||
static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
|
||||
[0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
|
||||
[0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
|
||||
[0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
|
||||
[0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE3, PCIE3},
|
||||
};
|
||||
|
||||
static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
|
||||
[0x1] = {SATA1, SATA2},
|
||||
[0x3] = {SATA1, NONE},
|
||||
[0x4] = {SGMII_TSEC1, SGMII_TSEC3},
|
||||
[0x6] = {SGMII_TSEC1, NONE},
|
||||
};
|
||||
|
||||
int is_serdes_configured(enum srds_prtcl device)
|
||||
{
|
||||
int i;
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
u32 pordevsr = in_be32(&gur->pordevsr);
|
||||
u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
|
||||
MPC85xx_PORDEVSR_IO_SEL_SHIFT;
|
||||
|
||||
u32 srds2_cfg = (pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >>
|
||||
GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT;
|
||||
|
||||
debug("%s: dev = %d\n", __FUNCTION__, device);
|
||||
debug("PORDEVSR[IO_SEL] = %x\n", srds1_cfg);
|
||||
debug("PORDEVSR[SRDS2_IO_SEL] = %x\n", srds2_cfg);
|
||||
|
||||
if (srds1_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
|
||||
printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds1_cfg);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (srds2_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
|
||||
printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_cfg);
|
||||
return 0;
|
||||
}
|
||||
|
||||
for (i = 0; i < SRDS1_MAX_LANES; i++) {
|
||||
if (serdes1_cfg_tbl[srds1_cfg][i] == device)
|
||||
return 1;
|
||||
}
|
||||
for (i = 0; i < SRDS2_MAX_LANES; i++) {
|
||||
if (serdes2_cfg_tbl[srds2_cfg][i] == device)
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void fsl_serdes_init(void)
|
||||
{
|
||||
void *guts = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
|
|
|
@ -175,8 +175,8 @@ determine_refresh_rate_ps(const unsigned int spd_refresh)
|
|||
* ordinal 2, ddr2_speed_bins[1] contains tCK for CL=3
|
||||
* Not certain if any good value exists for CL=2
|
||||
*/
|
||||
/* CL2 CL3 CL4 CL5 CL6 */
|
||||
unsigned short ddr2_speed_bins[] = { 0, 5000, 3750, 3000, 2500 };
|
||||
/* CL2 CL3 CL4 CL5 CL6 CL7*/
|
||||
unsigned short ddr2_speed_bins[] = { 0, 5000, 3750, 3000, 2500, 1875 };
|
||||
|
||||
unsigned int
|
||||
compute_derated_DDR2_CAS_latency(unsigned int mclk_ps)
|
||||
|
|
|
@ -56,18 +56,6 @@ static struct pci_info pci_config_info[] =
|
|||
#elif defined(CONFIG_MPC8536)
|
||||
static struct pci_info pci_config_info[] =
|
||||
{
|
||||
[LAW_TRGT_IF_PCI] = {
|
||||
.cfg = 0,
|
||||
},
|
||||
[LAW_TRGT_IF_PCIE_1] = {
|
||||
.cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 7),
|
||||
},
|
||||
[LAW_TRGT_IF_PCIE_2] = {
|
||||
.cfg = (1 << 5) | (1 << 7),
|
||||
},
|
||||
[LAW_TRGT_IF_PCIE_3] = {
|
||||
.cfg = (1 << 7),
|
||||
},
|
||||
};
|
||||
#elif defined(CONFIG_MPC8544)
|
||||
static struct pci_info pci_config_info[] =
|
||||
|
|
|
@ -1,21 +1,48 @@
|
|||
/*
|
||||
* Copyright 2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __FSL_SERDES_H
|
||||
#define __FSL_SERDES_H
|
||||
|
||||
#include <config.h>
|
||||
|
||||
#define FSL_SERDES_CLK_100 (0 << 28)
|
||||
#define FSL_SERDES_CLK_125 (1 << 28)
|
||||
#define FSL_SERDES_CLK_150 (3 << 28)
|
||||
#define FSL_SERDES_PROTO_SATA 0
|
||||
#define FSL_SERDES_PROTO_PEX 1
|
||||
#define FSL_SERDES_PROTO_PEX_X2 2
|
||||
#define FSL_SERDES_PROTO_SGMII 3
|
||||
#define FSL_SERDES_VDD_1V 1
|
||||
enum srds_prtcl {
|
||||
NONE = 0,
|
||||
PCIE1,
|
||||
PCIE2,
|
||||
PCIE3,
|
||||
PCIE4,
|
||||
SATA1,
|
||||
SATA2,
|
||||
SRIO1,
|
||||
SRIO2,
|
||||
SGMII_FM1,
|
||||
SGMII_FM2,
|
||||
SGMII_TSEC1,
|
||||
SGMII_TSEC2,
|
||||
SGMII_TSEC3,
|
||||
SGMII_TSEC4,
|
||||
XAUI_FM1,
|
||||
XAUI_FM2,
|
||||
AURORA,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_FSL_SERDES
|
||||
extern void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd);
|
||||
#else
|
||||
static void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd) {}
|
||||
#endif /* CONFIG_FSL_SERDES */
|
||||
int is_serdes_configured(enum srds_prtcl device);
|
||||
|
||||
#endif /* __FSL_SERDES_H */
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2007 Freescale Semiconductor, Inc.
|
||||
* Copyright 2007, 2010 Freescale Semiconductor, Inc.
|
||||
* York Sun <yorksun@freescale.com>
|
||||
*
|
||||
* FSL DIU Framebuffer driver
|
||||
|
@ -26,6 +26,7 @@
|
|||
#include <common.h>
|
||||
#include <i2c.h>
|
||||
#include <malloc.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#include "fsl_diu_fb.h"
|
||||
|
||||
|
@ -267,9 +268,9 @@ int fsl_diu_init(int xres,
|
|||
|
||||
memset(info->screen_base, 0, info->smem_len);
|
||||
|
||||
dr.diu_reg->desc[0] = (unsigned int) &dummy_ad;
|
||||
dr.diu_reg->desc[1] = (unsigned int) &dummy_ad;
|
||||
dr.diu_reg->desc[2] = (unsigned int) &dummy_ad;
|
||||
out_be32(&dr.diu_reg->desc[0], &dummy_ad);
|
||||
out_be32(&dr.diu_reg->desc[1], &dummy_ad);
|
||||
out_be32(&dr.diu_reg->desc[2], &dummy_ad);
|
||||
debug("dummy dr.diu_reg->desc[0] = 0x%x\n", dr.diu_reg->desc[0]);
|
||||
debug("dummy desc[0] = 0x%x\n", hw->desc[0]);
|
||||
|
||||
|
@ -331,26 +332,26 @@ int fsl_diu_init(int xres,
|
|||
|
||||
/* Program DIU registers */
|
||||
|
||||
hw->gamma = (unsigned int) gamma.paddr;
|
||||
hw->cursor= (unsigned int) cursor.paddr;
|
||||
hw->bgnd = 0x007F7F7F; /* BGND */
|
||||
hw->bgnd_wb = 0; /* BGND_WB */
|
||||
hw->disp_size = var->yres << 16 | var->xres; /* DISP SIZE */
|
||||
hw->wb_size = 0; /* WB SIZE */
|
||||
hw->wb_mem_addr = 0; /* WB MEM ADDR */
|
||||
hw->hsyn_para = var->left_margin << 22 | /* BP_H */
|
||||
out_be32(&hw->gamma, gamma.paddr);
|
||||
out_be32(&hw->cursor, cursor.paddr);
|
||||
out_be32(&hw->bgnd, 0x007F7F7F);
|
||||
out_be32(&hw->bgnd_wb, 0); /* BGND_WB */
|
||||
out_be32(&hw->disp_size, var->yres << 16 | var->xres); /* DISP SIZE */
|
||||
out_be32(&hw->wb_size, 0); /* WB SIZE */
|
||||
out_be32(&hw->wb_mem_addr, 0); /* WB MEM ADDR */
|
||||
out_be32(&hw->hsyn_para, var->left_margin << 22 | /* BP_H */
|
||||
var->hsync_len << 11 | /* PW_H */
|
||||
var->right_margin; /* FP_H */
|
||||
hw->vsyn_para = var->upper_margin << 22 | /* BP_V */
|
||||
var->right_margin); /* FP_H */
|
||||
|
||||
out_be32(&hw->vsyn_para, var->upper_margin << 22 | /* BP_V */
|
||||
var->vsync_len << 11 | /* PW_V */
|
||||
var->lower_margin; /* FP_V */
|
||||
|
||||
hw->syn_pol = 0; /* SYNC SIGNALS POLARITY */
|
||||
hw->thresholds = 0x00037800; /* The Thresholds */
|
||||
hw->int_status = 0; /* INTERRUPT STATUS */
|
||||
hw->int_mask = 0; /* INT MASK */
|
||||
hw->plut = 0x01F5F666;
|
||||
var->lower_margin); /* FP_V */
|
||||
|
||||
out_be32(&hw->syn_pol, 0); /* SYNC SIGNALS POLARITY */
|
||||
out_be32(&hw->thresholds, 0x00037800); /* The Thresholds */
|
||||
out_be32(&hw->int_status, 0); /* INTERRUPT STATUS */
|
||||
out_be32(&hw->int_mask, 0); /* INT MASK */
|
||||
out_be32(&hw->plut, 0x01F5F666);
|
||||
/* Pixel Clock configuration */
|
||||
debug("DIU pixclock in ps - %d\n", var->pixclock);
|
||||
diu_set_pixel_clock(var->pixclock);
|
||||
|
@ -390,8 +391,8 @@ static int fsl_diu_enable_panel(struct fb_info *info)
|
|||
struct diu_ad *ad = &fsl_diu_fb_ad;
|
||||
|
||||
debug("Entered: enable_panel\n");
|
||||
if (hw->desc[0] != (unsigned int)ad)
|
||||
hw->desc[0] = (unsigned int)ad;
|
||||
if (in_be32(&hw->desc[0]) != (u32)ad)
|
||||
out_be32(&hw->desc[0], ad);
|
||||
debug("desc[0] = 0x%x\n", hw->desc[0]);
|
||||
return 0;
|
||||
}
|
||||
|
@ -401,8 +402,8 @@ static int fsl_diu_disable_panel(struct fb_info *info)
|
|||
struct diu *hw = dr.diu_reg;
|
||||
|
||||
debug("Entered: disable_panel\n");
|
||||
if (hw->desc[0] != (unsigned int)&dummy_ad)
|
||||
hw->desc[0] = (unsigned int)&dummy_ad;
|
||||
if (in_be32(&hw->desc[0]) != (u32)&dummy_ad)
|
||||
out_be32(&hw->desc[0], &dummy_ad);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -443,7 +444,7 @@ static void enable_lcdc(void)
|
|||
|
||||
debug("Entered: enable_lcdc, fb_enabled = %d\n", fb_enabled);
|
||||
if (!fb_enabled) {
|
||||
hw->diu_mode = dr.mode;
|
||||
out_be32(&hw->diu_mode, dr.mode);
|
||||
fb_enabled++;
|
||||
}
|
||||
debug("diu_mode = %d\n", hw->diu_mode);
|
||||
|
@ -455,7 +456,7 @@ static void disable_lcdc(void)
|
|||
|
||||
debug("Entered: disable_lcdc, fb_enabled = %d\n", fb_enabled);
|
||||
if (fb_enabled) {
|
||||
hw->diu_mode = 0;
|
||||
out_be32(&hw->diu_mode, 0);
|
||||
fb_enabled = 0;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -28,15 +28,7 @@
|
|||
#include <asm/mmu.h>
|
||||
|
||||
struct law_entry law_table[] = {
|
||||
SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
|
||||
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
|
||||
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
|
||||
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_1),
|
||||
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
|
||||
SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_2),
|
||||
SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
|
||||
SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3),
|
||||
SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
|
||||
SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
|
||||
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
|
||||
};
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2008-2009 Freescale Semiconductor, Inc.
|
||||
* Copyright 2008-2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
@ -30,6 +30,7 @@
|
|||
#include <asm/fsl_pci.h>
|
||||
#include <asm/fsl_ddr_sdram.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
#include <spd.h>
|
||||
#include <miiphy.h>
|
||||
#include <libfdt.h>
|
||||
|
@ -219,9 +220,13 @@ void pci_init_board(void)
|
|||
|
||||
puts("\n");
|
||||
#ifdef CONFIG_PCIE3
|
||||
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
|
||||
pcie_configured = is_serdes_configured(PCIE3);
|
||||
|
||||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
|
||||
set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M,
|
||||
LAW_TRGT_IF_PCIE_3);
|
||||
set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K,
|
||||
LAW_TRGT_IF_PCIE_3);
|
||||
SET_STD_PCIE_INFO(pci_info[num], 3);
|
||||
pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
|
||||
printf (" PCIE3 connected to Slot3 as %s (base address %lx)\n",
|
||||
|
@ -239,9 +244,13 @@ void pci_init_board(void)
|
|||
#endif
|
||||
|
||||
#ifdef CONFIG_PCIE1
|
||||
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
|
||||
pcie_configured = is_serdes_configured(PCIE1);
|
||||
|
||||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
|
||||
set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M,
|
||||
LAW_TRGT_IF_PCIE_1);
|
||||
set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K,
|
||||
LAW_TRGT_IF_PCIE_1);
|
||||
SET_STD_PCIE_INFO(pci_info[num], 1);
|
||||
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
|
||||
printf (" PCIE1 connected to Slot1 as %s (base address %lx)\n",
|
||||
|
@ -259,9 +268,13 @@ void pci_init_board(void)
|
|||
#endif
|
||||
|
||||
#ifdef CONFIG_PCIE2
|
||||
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
|
||||
pcie_configured = is_serdes_configured(PCIE2);
|
||||
|
||||
if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
|
||||
set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M,
|
||||
LAW_TRGT_IF_PCIE_2);
|
||||
set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K,
|
||||
LAW_TRGT_IF_PCIE_2);
|
||||
SET_STD_PCIE_INFO(pci_info[num], 2);
|
||||
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
|
||||
printf (" PCIE2 connected to Slot 2 as %s (base address %lx)\n",
|
||||
|
@ -285,6 +298,10 @@ void pci_init_board(void)
|
|||
pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
|
||||
|
||||
if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
|
||||
set_next_law(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M,
|
||||
LAW_TRGT_IF_PCI);
|
||||
set_next_law(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K,
|
||||
LAW_TRGT_IF_PCI);
|
||||
SET_STD_PCI_INFO(pci_info[num], 1);
|
||||
pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
|
||||
printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
|
||||
|
@ -481,17 +498,6 @@ get_board_ddr_clk(ulong dummy)
|
|||
}
|
||||
#endif
|
||||
|
||||
int sata_initialize(void)
|
||||
{
|
||||
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
uint sdrs2_io_sel =
|
||||
(gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
|
||||
if (sdrs2_io_sel & 0x04)
|
||||
return 1;
|
||||
|
||||
return __sata_initialize();
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
#ifdef CONFIG_TSEC_ENET
|
||||
|
@ -540,15 +546,23 @@ void ft_board_setup(void *blob, bd_t *bd)
|
|||
|
||||
#ifdef CONFIG_PCI1
|
||||
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
|
||||
#else
|
||||
ft_fsl_pci_setup(blob, "pci0", NULL);
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE2
|
||||
ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
|
||||
#else
|
||||
ft_fsl_pci_setup(blob, "pci1", NULL);
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE2
|
||||
ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
|
||||
#else
|
||||
ft_fsl_pci_setup(blob, "pci2", NULL);
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE1
|
||||
ft_fsl_pci_setup(blob, "pci3", &pcie3_hose);
|
||||
#else
|
||||
ft_fsl_pci_setup(blob, "pci3", NULL);
|
||||
#endif
|
||||
#ifdef CONFIG_FSL_SGMII_RISER
|
||||
fsl_sgmii_riser_fdt_fixup(blob);
|
||||
|
|
|
@ -20,11 +20,15 @@ spd_check(const u8 *buf, u8 spd_rev, u8 spd_cksum)
|
|||
* Check SPD revision supported
|
||||
* Rev 1.2 or less supported by this code
|
||||
*/
|
||||
if (spd_rev > 0x12) {
|
||||
if (spd_rev >= 0x20) {
|
||||
printf("SPD revision %02X not supported by this code\n",
|
||||
spd_rev);
|
||||
return 1;
|
||||
}
|
||||
if (spd_rev > 0x13) {
|
||||
printf("SPD revision %02X not verified by this code\n",
|
||||
spd_rev);
|
||||
}
|
||||
|
||||
/*
|
||||
* Calculate checksum
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (C) 2008 Freescale Semiconductor, Inc.
|
||||
* Copyright (C) 2008,2010 Freescale Semiconductor, Inc.
|
||||
* Dave Liu <daveliu@freescale.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
|
@ -22,6 +22,7 @@
|
|||
#include <command.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
#include <malloc.h>
|
||||
#include <libata.h>
|
||||
#include <fis.h>
|
||||
|
@ -129,6 +130,17 @@ int init_sata(int dev)
|
|||
return -1;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MPC85xx
|
||||
if ((dev == 0) && (!is_serdes_configured(SATA1))) {
|
||||
printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
|
||||
return -1;
|
||||
}
|
||||
if ((dev == 1) && (!is_serdes_configured(SATA2))) {
|
||||
printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Allocate SATA device driver struct */
|
||||
sata = (fsl_sata_t *)malloc(sizeof(fsl_sata_t));
|
||||
if (!sata) {
|
||||
|
|
Loading…
Reference in a new issue