MLK-18460-5 mx7d_19x19_arm2: Add LPDDR3, LPDDR2 and DDR3 ARM2 support
Porting the iMX7D 19x19 LPDDR2, LPDDR3 and DDR3 ARM2 board codes from v2017.03. Signed-off-by: Ye Li <ye.li@nxp.com>zero-sugar
parent
44ab0cb416
commit
1c0e03df6d
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@ -48,6 +48,27 @@ config TARGET_MX7D_12X12_DDR3_ARM2
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select DM
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select DM_THERMAL
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config TARGET_MX7D_19X19_DDR3_ARM2
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bool "Support mx7d_19x19_ddr3_arm2"
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select BOARD_LATE_INIT
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select MX7D
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select DM
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select DM_THERMAL
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config TARGET_MX7D_19X19_LPDDR3_ARM2
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bool "Support mx7d_19x19_lpddr3_arm2"
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select BOARD_LATE_INIT
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select MX7D
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select DM
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select DM_THERMAL
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config TARGET_MX7D_19X19_LPDDR2_ARM2
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bool "Support mx7d_19x19_lpddr2_arm2"
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select BOARD_LATE_INIT
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select MX7D
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select DM
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select DM_THERMAL
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config TARGET_PICO_IMX7D
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bool "pico-imx7d"
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select BOARD_LATE_INIT
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@ -78,6 +99,8 @@ source "board/compulab/cl-som-imx7/Kconfig"
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source "board/freescale/mx7dsabresd/Kconfig"
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source "board/freescale/mx7d_12x12_lpddr3_arm2/Kconfig"
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source "board/freescale/mx7d_12x12_ddr3_arm2/Kconfig"
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source "board/freescale/mx7d_19x19_ddr3_arm2/Kconfig"
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source "board/freescale/mx7d_19x19_lpddr3_arm2/Kconfig"
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source "board/technexion/pico-imx7d/Kconfig"
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source "board/toradex/colibri_imx7/Kconfig"
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source "board/warp7/Kconfig"
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@ -0,0 +1,14 @@
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if TARGET_MX7D_19X19_DDR3_ARM2
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config SYS_BOARD
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default "mx7d_19x19_ddr3_arm2"
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config SYS_VENDOR
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default "freescale"
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config SYS_CONFIG_NAME
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default "mx7d_19x19_ddr3_arm2"
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config SYS_TEXT_BASE
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default 0x87800000
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endif
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@ -0,0 +1,6 @@
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# (C) Copyright 2014 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := mx7d_19x19_ddr3_arm2.o
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@ -0,0 +1,105 @@
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/*
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* Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Refer docs/README.imxmage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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#define __ASSEMBLY__
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#include <config.h>
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/* image version */
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IMAGE_VERSION 2
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BOOT_FROM sd
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#ifdef CONFIG_USE_IMXIMG_PLUGIN
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/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
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PLUGIN board/freescale/mx7d_19x19_ddr3_arm2/plugin.bin 0x00910000
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#else
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#ifdef CONFIG_SECURE_BOOT
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CSF CONFIG_CSF_SIZE
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#endif
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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DATA 4 0x30340004 0x4F400005
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/* Clear then set bit30 to ensure exit from DDR retention */
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DATA 4 0x30360388 0x40000000
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DATA 4 0x30360384 0x40000000
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DATA 4 0x30391000 0x00000002
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DATA 4 0x307a0000 0x01040001
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DATA 4 0x307a01a0 0x80400003
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DATA 4 0x307a01a4 0x00100020
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DATA 4 0x307a01a8 0x80100004
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DATA 4 0x307a0064 0x00400046
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DATA 4 0x307a0490 0x00000001
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DATA 4 0x307a00d0 0x00020083
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DATA 4 0x307a00d4 0x00690000
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DATA 4 0x307a00dc 0x09300004
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DATA 4 0x307a00e0 0x04080000
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DATA 4 0x307a00e4 0x00100004
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DATA 4 0x307a00f4 0x0000033f
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DATA 4 0x307a0100 0x09081109
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DATA 4 0x307a0104 0x0007020d
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DATA 4 0x307a0108 0x03040407
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DATA 4 0x307a010c 0x00002006
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DATA 4 0x307a0110 0x04020205
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DATA 4 0x307a0114 0x03030202
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DATA 4 0x307a0120 0x00000803
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DATA 4 0x307a0180 0x00800020
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DATA 4 0x307a0184 0x02000100
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DATA 4 0x307a0190 0x02098204
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DATA 4 0x307a0194 0x00030303
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DATA 4 0x307a0200 0x00000016
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DATA 4 0x307a0204 0x00080808
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DATA 4 0x307a0210 0x00000f0f
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DATA 4 0x307a0214 0x07070707
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DATA 4 0x307a0218 0x0f070707
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DATA 4 0x307a0240 0x06000604
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DATA 4 0x307a0244 0x00000001
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DATA 4 0x30391000 0x00000000
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DATA 4 0x30790000 0x17420f40
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DATA 4 0x30790004 0x10210100
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DATA 4 0x30790010 0x00060807
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DATA 4 0x307900b0 0x1010007e
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DATA 4 0x3079009c 0x00000b24
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DATA 4 0x30790020 0x08080808
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DATA 4 0x30790030 0x08080808
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DATA 4 0x30790050 0x01000010
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DATA 4 0x30790050 0x00000010
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DATA 4 0x307900c0 0x0e407304
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DATA 4 0x307900c0 0x0e447304
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DATA 4 0x307900c0 0x0e447306
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CHECK_BITS_SET 4 0x307900c4 0x1
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DATA 4 0x307900c0 0x0e407304
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DATA 4 0x30384130 0x00000000
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DATA 4 0x30340020 0x00000178
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DATA 4 0x30384130 0x00000002
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DATA 4 0x30790018 0x0000000f
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CHECK_BITS_SET 4 0x307a0004 0x1
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#endif
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@ -0,0 +1,121 @@
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/*
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* Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Refer docs/README.imxmage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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#define __ASSEMBLY__
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#include <config.h>
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi/sd/nand/onenand, qspi/nor
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*/
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BOOT_FROM sd
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#ifdef CONFIG_USE_IMXIMG_PLUGIN
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/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
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PLUGIN board/freescale/mx7d_19x19_ddr3_arm2/plugin.bin 0x00910000
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#else
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#ifdef CONFIG_SECURE_BOOT
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CSF CONFIG_CSF_SIZE
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#endif
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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DATA 4 0x30360070 0x00703021
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DATA 4 0x30360090 0x0
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DATA 4 0x30360070 0x00603021
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CHECK_BITS_SET 4 0x30360070 0x80000000
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DATA 4 0x30389880 0x1
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DATA 4 0x30340004 0x4F400005
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/* Clear then set bit30 to ensure exit from DDR retention */
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DATA 4 0x30360388 0x40000000
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DATA 4 0x30360384 0x40000000
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DATA 4 0x30391000 0x00000002
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DATA 4 0x307a0000 0x01040001
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DATA 4 0x307a01a0 0x80400003
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DATA 4 0x307a01a4 0x00100020
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DATA 4 0x307a01a8 0x80100004
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DATA 4 0x307a0064 0x00400046
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DATA 4 0x307a0490 0x00000001
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DATA 4 0x307a00d0 0x00020083
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DATA 4 0x307a00d4 0x00690000
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DATA 4 0x307a00dc 0x09300004
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DATA 4 0x307a00e0 0x04080000
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DATA 4 0x307a00e4 0x00100004
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DATA 4 0x307a00f4 0x0000033f
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DATA 4 0x307a0100 0x09081109
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DATA 4 0x307a0104 0x0007020d
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DATA 4 0x307a0108 0x03040407
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DATA 4 0x307a010c 0x00002006
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DATA 4 0x307a0110 0x04020205
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DATA 4 0x307a0114 0x03030202
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DATA 4 0x307a0120 0x00000803
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DATA 4 0x307a0180 0x00800020
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DATA 4 0x307a0184 0x02000100
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DATA 4 0x307a0190 0x02098204
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DATA 4 0x307a0194 0x00030303
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DATA 4 0x307a0200 0x00000016
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DATA 4 0x307a0204 0x00080808
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DATA 4 0x307a0210 0x00000f0f
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DATA 4 0x307a0214 0x07070707
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DATA 4 0x307a0218 0x0f070707
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DATA 4 0x307a0240 0x06000604
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DATA 4 0x307a0244 0x00000001
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DATA 4 0x30391000 0x00000000
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DATA 4 0x30790000 0x17420f40
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DATA 4 0x30790004 0x10210100
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DATA 4 0x30790010 0x00060807
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DATA 4 0x307900b0 0x1010007e
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DATA 4 0x3079009c 0x00000dee
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DATA 4 0x3079007c 0x18181818
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DATA 4 0x30790080 0x18181818
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DATA 4 0x30790084 0x40401818
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DATA 4 0x30790088 0x00000040
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DATA 4 0x3079006c 0x40404040
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DATA 4 0x30790020 0x08080808
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DATA 4 0x30790030 0x08080808
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DATA 4 0x30790050 0x01000010
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DATA 4 0x30790050 0x00000010
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DATA 4 0x307900c0 0x0e407304
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DATA 4 0x307900c0 0x0e447304
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DATA 4 0x307900c0 0x0e447306
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CHECK_BITS_SET 4 0x307900c4 0x1
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DATA 4 0x307900c0 0x0e407304
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DATA 4 0x30384130 0x00000000
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DATA 4 0x30340020 0x00000178
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DATA 4 0x30384130 0x00000002
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DATA 4 0x30790018 0x0000000f
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CHECK_BITS_SET 4 0x307a0004 0x1
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#endif
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@ -0,0 +1,645 @@
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/*
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* Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx7-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/io.h>
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#include <linux/sizes.h>
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#include <common.h>
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#include <fsl_esdhc.h>
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#include <mmc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <power/pmic.h>
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#include <power/pfuze3000_pmic.h>
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#include "../common/pfuze.h"
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#ifdef CONFIG_SYS_I2C_MXC
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#include <i2c.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#endif
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#include <asm/arch/crm_regs.h>
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#include <asm/mach-imx/video.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
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PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
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PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
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#define ENET_PAD_CTRL_MII (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
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#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
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#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
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PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
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#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
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PAD_CTL_DSE_3P3V_49OHM)
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#define QSPI_PAD_CTRL \
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(PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
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#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
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#ifdef CONFIG_SYS_I2C
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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/* I2C1 for PMIC */
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struct i2c_pads_info i2c_pad_info1 = {
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.scl = {
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.i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
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.gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
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.gp = IMX_GPIO_NR(4, 8),
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},
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.sda = {
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.i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
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.gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
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.gp = IMX_GPIO_NR(4, 9),
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},
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};
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/* I2C2 */
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struct i2c_pads_info i2c_pad_info2 = {
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.scl = {
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.i2c_mode = MX7D_PAD_I2C2_SCL__I2C2_SCL | PC,
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.gpio_mode = MX7D_PAD_I2C2_SCL__GPIO4_IO10 | PC,
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.gp = IMX_GPIO_NR(4, 10),
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},
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.sda = {
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.i2c_mode = MX7D_PAD_I2C2_SDA__I2C2_SDA | PC,
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.gpio_mode = MX7D_PAD_I2C2_SDA__GPIO4_IO11 | PC,
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.gp = IMX_GPIO_NR(4, 11),
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},
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};
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#endif
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int dram_init(void)
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{
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gd->ram_size = PHYS_SDRAM_SIZE;
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return 0;
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}
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const usdhc1_emmc_pads[] = {
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MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_ECSPI2_MISO__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_ECSPI2_SS0__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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};
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static iomux_v3_cfg_t const usdhc2_pads[] = {
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MX7D_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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MX7D_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
|
||||
MX7D_PAD_GPIO1_IO12__SD2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
|
||||
MX7D_PAD_SD2_CD_B__GPIO5_IO9 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD2_RESET_B__GPIO5_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const usdhc3_pads[] = {
|
||||
MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
|
||||
MX7D_PAD_GPIO1_IO13__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
|
||||
MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
|
||||
#ifdef CONFIG_VIDEO_MXS
|
||||
static iomux_v3_cfg_t const lcd_pads[] = {
|
||||
MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
|
||||
MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const pwm_pads[] = {
|
||||
/* Use GPIO for Brightness adjustment, duty cycle = period */
|
||||
MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
void do_enable_parallel_lcd(struct display_info_t const *dev)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
|
||||
|
||||
/* Power up the LCD */
|
||||
gpio_request(IMX_GPIO_NR(3, 4), "lcd_pwr");
|
||||
gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
|
||||
|
||||
/* Set Brightness to high */
|
||||
gpio_request(IMX_GPIO_NR(1, 1), "lcd_backlight");
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 1) , 1);
|
||||
}
|
||||
|
||||
struct display_info_t const displays[] = {{
|
||||
.bus = ELCDIF1_IPS_BASE_ADDR,
|
||||
.addr = 0,
|
||||
.pixfmt = 24,
|
||||
.detect = NULL,
|
||||
.enable = do_enable_parallel_lcd,
|
||||
.mode = {
|
||||
.name = "MCIMX28LCD",
|
||||
.xres = 800,
|
||||
.yres = 480,
|
||||
.pixclock = 29850,
|
||||
.left_margin = 89,
|
||||
.right_margin = 164,
|
||||
.upper_margin = 23,
|
||||
.lower_margin = 10,
|
||||
.hsync_len = 10,
|
||||
.vsync_len = 10,
|
||||
.sync = 0,
|
||||
.vmode = FB_VMODE_NONINTERLACED
|
||||
} } };
|
||||
size_t display_count = ARRAY_SIZE(displays);
|
||||
#endif
|
||||
|
||||
static iomux_v3_cfg_t const per_rst_pads[] = {
|
||||
MX7D_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const wdog_pads[] = {
|
||||
MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
static iomux_v3_cfg_t const fec2_pads[] = {
|
||||
MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_fec2(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
|
||||
}
|
||||
#endif
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_QSPI
|
||||
|
||||
static iomux_v3_cfg_t const quadspi_pads[] = {
|
||||
MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA04__QSPI_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
|
||||
MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA12__QSPI_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
|
||||
};
|
||||
|
||||
int board_qspi_init(void)
|
||||
{
|
||||
/* Set the iomux */
|
||||
imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
|
||||
|
||||
/* Set the clock */
|
||||
set_clk_qspi();
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
|
||||
#define USDHC2_CD_GPIO IMX_GPIO_NR(5, 9)
|
||||
#define USDHC3_CD_GPIO IMX_GPIO_NR(1, 14)
|
||||
|
||||
#define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2)
|
||||
#define USDHC2_PWR_GPIO IMX_GPIO_NR(5, 11)
|
||||
#define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11)
|
||||
|
||||
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[3] = {
|
||||
{USDHC1_BASE_ADDR},
|
||||
{USDHC2_BASE_ADDR, 0, 4},
|
||||
{USDHC3_BASE_ADDR},
|
||||
};
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret = 0;
|
||||
|
||||
switch (cfg->esdhc_base) {
|
||||
case USDHC1_BASE_ADDR:
|
||||
ret = 1; /* Assume uSDHC1 emmc is always present */
|
||||
break;
|
||||
case USDHC2_BASE_ADDR:
|
||||
ret = !gpio_get_value(USDHC2_CD_GPIO);
|
||||
break;
|
||||
case USDHC3_BASE_ADDR:
|
||||
ret = !gpio_get_value(USDHC3_CD_GPIO);
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
int i;
|
||||
/*
|
||||
* According to the board_mmc_init() the following map is done:
|
||||
* (U-boot device node) (Physical Port)
|
||||
* mmc0 USDHC1 (eMMC)
|
||||
* mmc1 USDHC2
|
||||
* mmc2 USDHC3
|
||||
*/
|
||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc1_emmc_pads, ARRAY_SIZE(usdhc1_emmc_pads));
|
||||
gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr");
|
||||
gpio_direction_output(USDHC1_PWR_GPIO, 1);
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
break;
|
||||
case 1:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
|
||||
gpio_request(USDHC2_PWR_GPIO, "usdhc2_pwr");
|
||||
gpio_request(USDHC2_CD_GPIO, "usdhc2_cd");
|
||||
gpio_direction_input(USDHC2_CD_GPIO);
|
||||
gpio_direction_output(USDHC2_PWR_GPIO, 1);
|
||||
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
|
||||
break;
|
||||
case 2:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
|
||||
gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr");
|
||||
gpio_request(USDHC3_CD_GPIO, "usdhc3_cd");
|
||||
gpio_direction_input(USDHC3_CD_GPIO);
|
||||
gpio_direction_output(USDHC3_PWR_GPIO, 1);
|
||||
usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
break;
|
||||
default:
|
||||
printf("Warning: you configured more USDHC controllers"
|
||||
"(%d) than supported by the board\n", i + 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
|
||||
printf("Warning: failed to initialize mmc dev %d\n", i);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int ret;
|
||||
|
||||
setup_iomux_fec2();
|
||||
|
||||
ret = fecmxc_initialize_multi(bis, 0,
|
||||
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
|
||||
if (ret)
|
||||
printf("FEC1 MXC: %s:failed\n", __func__);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int setup_fec(void)
|
||||
{
|
||||
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
|
||||
= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
|
||||
int ret;
|
||||
|
||||
/* Use 125M anatop REF_CLK for ENET2, clear gpr1[14], gpr1[18]*/
|
||||
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
|
||||
(IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK |
|
||||
IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0);
|
||||
|
||||
ret = set_clk_enet(ENET_125MHZ);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
/* Enable 1.8V(SEL_1P5_1P8_POS_REG) on
|
||||
Phy control debug reg 0 */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
|
||||
|
||||
/* rgmii tx clock delay enable */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
|
||||
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MXC_SPI
|
||||
iomux_v3_cfg_t const ecspi1_pads[] = {
|
||||
MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
|
||||
/* CS0 */
|
||||
MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
void setup_spinor(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
|
||||
ARRAY_SIZE(ecspi1_pads));
|
||||
gpio_request(IMX_GPIO_NR(4, 19), "ecspi1_cs");
|
||||
gpio_direction_output(IMX_GPIO_NR(4, 19), 0);
|
||||
}
|
||||
|
||||
int board_spi_cs_gpio(unsigned bus, unsigned cs)
|
||||
{
|
||||
return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 19)) : -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX7
|
||||
#ifndef CONFIG_DM_USB
|
||||
iomux_v3_cfg_t const usb_otg1_pads[] = {
|
||||
MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t const usb_otg2_pads[] = {
|
||||
MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_usb(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, ARRAY_SIZE(usb_otg1_pads));
|
||||
imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, ARRAY_SIZE(usb_otg2_pads));
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_uart();
|
||||
|
||||
#ifdef CONFIG_SYS_I2C
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
||||
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX7
|
||||
#ifndef CONFIG_DM_USB
|
||||
setup_usb();
|
||||
#endif
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
/* Reset peripherals */
|
||||
imx_iomux_v3_setup_multiple_pads(per_rst_pads, ARRAY_SIZE(per_rst_pads));
|
||||
|
||||
gpio_request(IMX_GPIO_NR(1, 3), "per_rst");
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 3), 0);
|
||||
udelay(500);
|
||||
gpio_set_value(IMX_GPIO_NR(1, 3), 1);
|
||||
|
||||
#ifdef CONFIG_MXC_SPI
|
||||
setup_spinor();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
setup_fec();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_QSPI
|
||||
board_qspi_init();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
static const struct boot_mode board_boot_modes[] = {
|
||||
/* 4 bit bus width */
|
||||
{"emmc", MAKE_CFGVAL(0x10, 0x22, 0x00, 0x00)},
|
||||
{"sd2", MAKE_CFGVAL(0x10, 0x16, 0x00, 0x00)},
|
||||
{"sd3", MAKE_CFGVAL(0x10, 0x1a, 0x00, 0x00)},
|
||||
{"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)},
|
||||
{NULL, 0},
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_POWER
|
||||
#define I2C_PMIC 0
|
||||
int power_init_board(void)
|
||||
{
|
||||
struct pmic *p;
|
||||
int ret;
|
||||
unsigned int reg, rev_id;
|
||||
|
||||
ret = power_pfuze3000_init(I2C_PMIC);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
p = pmic_get("PFUZE3000");
|
||||
ret = pmic_probe(p);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
|
||||
pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
|
||||
printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
|
||||
|
||||
/* disable Low Power Mode during standby mode */
|
||||
pmic_reg_read(p, PFUZE3000_LDOGCTL, ®);
|
||||
reg |= 0x1;
|
||||
pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
|
||||
|
||||
/* SW1A/1B mode set to APS/APS */
|
||||
reg = 0x8;
|
||||
pmic_reg_write(p, PFUZE3000_SW1AMODE, reg);
|
||||
pmic_reg_write(p, PFUZE3000_SW1BMODE, reg);
|
||||
|
||||
/* SW1A/1B standby voltage set to 0.975V */
|
||||
reg = 0xb;
|
||||
pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
|
||||
pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
|
||||
|
||||
/* set SW1B normal voltage to 0.975V */
|
||||
pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®);
|
||||
reg &= ~0x1f;
|
||||
reg |= PFUZE3000_SW1AB_SETP(9750);
|
||||
pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#elif defined(CONFIG_DM_PMIC_PFUZE100)
|
||||
int power_init_board(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret, dev_id, rev_id, reg;
|
||||
|
||||
ret = pmic_get("pfuze3000", &dev);
|
||||
if (ret == -ENODEV)
|
||||
return 0;
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
|
||||
dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
|
||||
rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
|
||||
printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
|
||||
|
||||
/* disable Low Power Mode during standby mode */
|
||||
reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
|
||||
reg |= 0x1;
|
||||
pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
|
||||
|
||||
/* SW1A/1B mode set to APS/APS */
|
||||
reg = 0x8;
|
||||
pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg);
|
||||
pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg);
|
||||
|
||||
/* SW1A/1B standby voltage set to 0.975V */
|
||||
reg = 0xb;
|
||||
pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg);
|
||||
pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg);
|
||||
|
||||
/* set SW1B normal voltage to 0.975V */
|
||||
reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
|
||||
reg &= ~0x1f;
|
||||
reg |= PFUZE3000_SW1AB_SETP(9750);
|
||||
pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
add_board_boot_modes(board_boot_modes);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_MMC
|
||||
board_late_mmc_env_init();
|
||||
#endif
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
|
||||
|
||||
set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
return get_cpu_rev();
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: MX7D 19x19 DDR3 ARM2\n");
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,227 @@
|
|||
/*
|
||||
* Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
/* DDR script */
|
||||
.macro imx7d_ddrphy_latency_setting
|
||||
ldr r2, =ANATOP_BASE_ADDR
|
||||
ldr r3, [r2, #0x800]
|
||||
and r3, r3, #0xFF
|
||||
cmp r3, #0x11
|
||||
bne NO_DELAY
|
||||
|
||||
/*TO 1.1*/
|
||||
ldr r1, =0x00000dee
|
||||
str r1, [r0, #0x9c]
|
||||
ldr r1, =0x18181818
|
||||
str r1, [r0, #0x7c]
|
||||
ldr r1, =0x18181818
|
||||
str r1, [r0, #0x80]
|
||||
ldr r1, =0x40401818
|
||||
str r1, [r0, #0x84]
|
||||
ldr r1, =0x00000040
|
||||
str r1, [r0, #0x88]
|
||||
ldr r1, =0x40404040
|
||||
str r1, [r0, #0x6c]
|
||||
b TUNE_END
|
||||
|
||||
NO_DELAY:
|
||||
/*TO 1.0*/
|
||||
ldr r1, =0x00000b24
|
||||
str r1, [r0, #0x9c]
|
||||
|
||||
TUNE_END:
|
||||
.endm
|
||||
|
||||
.macro imx7d_ddr_freq_setting
|
||||
ldr r2, =ANATOP_BASE_ADDR
|
||||
ldr r3, [r2, #0x800]
|
||||
and r3, r3, #0xFF
|
||||
cmp r3, #0x11
|
||||
bne FREQ_DEFAULT_533
|
||||
|
||||
/* Change to 400Mhz for TO1.1 */
|
||||
ldr r0, =ANATOP_BASE_ADDR
|
||||
ldr r1, =0x70
|
||||
ldr r2, =0x00703021
|
||||
str r2, [r0, r1]
|
||||
ldr r1, =0x90
|
||||
ldr r2, =0x0
|
||||
str r2, [r0, r1]
|
||||
ldr r1, =0x70
|
||||
ldr r2, =0x00603021
|
||||
str r2, [r0, r1]
|
||||
|
||||
ldr r3, =0x80000000
|
||||
wait_lock:
|
||||
ldr r2, [r0, r1]
|
||||
and r2, r3
|
||||
cmp r2, r3
|
||||
bne wait_lock
|
||||
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
ldr r1, =0x9880
|
||||
ldr r2, =0x1
|
||||
str r2, [r0, r1]
|
||||
|
||||
FREQ_DEFAULT_533:
|
||||
.endm
|
||||
|
||||
.macro imx7d_19x19_ddr3_arm2_ddr_setting
|
||||
imx7d_ddr_freq_setting
|
||||
|
||||
/* Configure ocram_epdc */
|
||||
ldr r0, =IOMUXC_GPR_BASE_ADDR
|
||||
ldr r1, =0x4f400005
|
||||
str r1, [r0, #0x4]
|
||||
|
||||
/* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */
|
||||
ldr r0, =ANATOP_BASE_ADDR
|
||||
ldr r1, =(0x1 << 30)
|
||||
str r1, [r0, #0x388]
|
||||
str r1, [r0, #0x384]
|
||||
|
||||
ldr r0, =SRC_BASE_ADDR
|
||||
ldr r1, =0x2
|
||||
ldr r2, =0x1000
|
||||
str r1, [r0, r2]
|
||||
|
||||
ldr r0, =DDRC_IPS_BASE_ADDR
|
||||
ldr r1, =0x01040001
|
||||
str r1, [r0]
|
||||
ldr r1, =0x80400003
|
||||
str r1, [r0, #0x1a0]
|
||||
ldr r1, =0x00100020
|
||||
str r1, [r0, #0x1a4]
|
||||
ldr r1, =0x80100004
|
||||
str r1, [r0, #0x1a8]
|
||||
ldr r1, =0x00400046
|
||||
str r1, [r0, #0x64]
|
||||
ldr r1, =0x1
|
||||
str r1, [r0, #0x490]
|
||||
ldr r1, =0x00020001
|
||||
str r1, [r0, #0xd0]
|
||||
ldr r1, =0x00690000
|
||||
str r1, [r0, #0xd4]
|
||||
ldr r1, =0x09300004
|
||||
str r1, [r0, #0xdc]
|
||||
ldr r1, =0x04080000
|
||||
str r1, [r0, #0xe0]
|
||||
ldr r1, =0x00100004
|
||||
str r1, [r0, #0xe4]
|
||||
ldr r1, =0x33f
|
||||
str r1, [r0, #0xf4]
|
||||
ldr r1, =0x09081109
|
||||
str r1, [r0, #0x100]
|
||||
ldr r1, =0x0007020d
|
||||
str r1, [r0, #0x104]
|
||||
ldr r1, =0x03040407
|
||||
str r1, [r0, #0x108]
|
||||
ldr r1, =0x00002006
|
||||
str r1, [r0, #0x10c]
|
||||
ldr r1, =0x04020205
|
||||
str r1, [r0, #0x110]
|
||||
ldr r1, =0x03030202
|
||||
str r1, [r0, #0x114]
|
||||
ldr r1, =0x00000803
|
||||
str r1, [r0, #0x120]
|
||||
ldr r1, =0x00800020
|
||||
str r1, [r0, #0x180]
|
||||
ldr r1, =0x02000100
|
||||
str r1, [r0, #0x184]
|
||||
ldr r1, =0x02098204
|
||||
str r1, [r0, #0x190]
|
||||
ldr r1, =0x00030303
|
||||
str r1, [r0, #0x194]
|
||||
|
||||
ldr r1, =0x00000016
|
||||
str r1, [r0, #0x200]
|
||||
ldr r1, =0x00080808
|
||||
str r1, [r0, #0x204]
|
||||
ldr r1, =0x00000f0f
|
||||
str r1, [r0, #0x210]
|
||||
ldr r1, =0x07070707
|
||||
str r1, [r0, #0x214]
|
||||
ldr r1, =0x0f070707
|
||||
str r1, [r0, #0x218]
|
||||
|
||||
ldr r1, =0x06000604
|
||||
str r1, [r0, #0x240]
|
||||
ldr r1, =0x00000001
|
||||
str r1, [r0, #0x244]
|
||||
|
||||
ldr r0, =SRC_BASE_ADDR
|
||||
mov r1, #0x0
|
||||
ldr r2, =0x1000
|
||||
str r1, [r0, r2]
|
||||
|
||||
ldr r0, =DDRPHY_IPS_BASE_ADDR
|
||||
ldr r1, =0x17420f40
|
||||
str r1, [r0]
|
||||
ldr r1, =0x10210100
|
||||
str r1, [r0, #0x4]
|
||||
ldr r1, =0x00060807
|
||||
str r1, [r0, #0x10]
|
||||
ldr r1, =0x1010007e
|
||||
str r1, [r0, #0xb0]
|
||||
imx7d_ddrphy_latency_setting
|
||||
ldr r1, =0x08080808
|
||||
str r1, [r0, #0x20]
|
||||
ldr r1, =0x08080808
|
||||
str r1, [r0, #0x30]
|
||||
ldr r1, =0x01000010
|
||||
str r1, [r0, #0x50]
|
||||
|
||||
ldr r1, =0x0e407304
|
||||
str r1, [r0, #0xc0]
|
||||
ldr r1, =0x0e447304
|
||||
str r1, [r0, #0xc0]
|
||||
ldr r1, =0x0e447306
|
||||
str r1, [r0, #0xc0]
|
||||
|
||||
wait_zq:
|
||||
ldr r1, [r0, #0xc4]
|
||||
tst r1, #0x1
|
||||
beq wait_zq
|
||||
|
||||
ldr r1, =0x0e407304
|
||||
str r1, [r0, #0xc0]
|
||||
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
mov r1, #0x0
|
||||
ldr r2, =0x4130
|
||||
str r1, [r0, r2]
|
||||
ldr r0, =IOMUXC_GPR_BASE_ADDR
|
||||
mov r1, #0x178
|
||||
str r1, [r0, #0x20]
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
mov r1, #0x2
|
||||
ldr r2, =0x4130
|
||||
str r1, [r0, r2]
|
||||
ldr r0, =DDRPHY_IPS_BASE_ADDR
|
||||
ldr r1, =0x0000000f
|
||||
str r1, [r0, #0x18]
|
||||
|
||||
ldr r0, =DDRC_IPS_BASE_ADDR
|
||||
wait_stat:
|
||||
ldr r1, [r0, #0x4]
|
||||
tst r1, #0x1
|
||||
beq wait_stat
|
||||
.endm
|
||||
|
||||
.macro imx7_clock_gating
|
||||
.endm
|
||||
|
||||
.macro imx7_qos_setting
|
||||
.endm
|
||||
|
||||
.macro imx7_ddr_setting
|
||||
imx7d_19x19_ddr3_arm2_ddr_setting
|
||||
.endm
|
||||
|
||||
/* include the common plugin code here */
|
||||
#include <asm/arch/mx7_plugin.S>
|
|
@ -0,0 +1,20 @@
|
|||
if TARGET_MX7D_19X19_LPDDR3_ARM2 || TARGET_MX7D_19X19_LPDDR2_ARM2
|
||||
|
||||
config SYS_BOARD
|
||||
default "mx7d_19x19_lpddr3_arm2"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "freescale"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "mx7d_19x19_lpddr3_arm2"
|
||||
|
||||
config SYS_TEXT_BASE
|
||||
default 0x87800000
|
||||
|
||||
config NOR
|
||||
bool "Support for NOR flash"
|
||||
help
|
||||
The i.MX SoC supports having a NOR flash connected to the WEIM.
|
||||
Need to set this for NOR_BOOT.
|
||||
endif
|
|
@ -0,0 +1,6 @@
|
|||
# (C) Copyright 2015 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := mx7d_19x19_lpddr3_arm2.o
|
|
@ -0,0 +1,106 @@
|
|||
/*
|
||||
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Refer docs/README.imxmage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
|
||||
/* image version */
|
||||
|
||||
IMAGE_VERSION 2
|
||||
|
||||
BOOT_FROM sd
|
||||
|
||||
#ifdef CONFIG_USE_IMXIMG_PLUGIN
|
||||
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
|
||||
PLUGIN board/freescale/mx7d_19x19_lpddr3_arm2/plugin.bin 0x00910000
|
||||
#else
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT
|
||||
CSF CONFIG_CSF_SIZE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Device Configuration Data (DCD)
|
||||
*
|
||||
* Each entry must have the format:
|
||||
* Addr-type Address Value
|
||||
*
|
||||
* where:
|
||||
* Addr-type register length (1,2 or 4 bytes)
|
||||
* Address absolute address of the register
|
||||
* value value to be stored in the register
|
||||
*/
|
||||
|
||||
DATA 4 0x30340004 0x4F400005
|
||||
|
||||
DATA 4 0x30391000 0x00000002
|
||||
DATA 4 0x307a0000 0x03040008
|
||||
DATA 4 0x307a0064 0x00200038
|
||||
DATA 4 0x307a0490 0x00000001
|
||||
DATA 4 0x307a00d0 0x00350001
|
||||
DATA 4 0x307a00dc 0x00c3000a
|
||||
DATA 4 0x307a00e0 0x00010000
|
||||
DATA 4 0x307a00e4 0x00110006
|
||||
DATA 4 0x307a00f4 0x0000033f
|
||||
DATA 4 0x307a0100 0x0a0e110b
|
||||
DATA 4 0x307a0104 0x00020211
|
||||
DATA 4 0x307a0108 0x03060708
|
||||
DATA 4 0x307a010c 0x00a0500c
|
||||
DATA 4 0x307a0110 0x05020307
|
||||
DATA 4 0x307a0114 0x02020404
|
||||
DATA 4 0x307a0118 0x02020003
|
||||
DATA 4 0x307a011c 0x00000202
|
||||
DATA 4 0x307a0120 0x00000202
|
||||
|
||||
DATA 4 0x307a0180 0x00600018
|
||||
DATA 4 0x307a0184 0x00e00100
|
||||
DATA 4 0x307a0190 0x02098205
|
||||
DATA 4 0x307a0194 0x00060303
|
||||
DATA 4 0x307a01a0 0x80400003
|
||||
DATA 4 0x307a01a4 0x00100020
|
||||
DATA 4 0x307a01a8 0x80100004
|
||||
|
||||
DATA 4 0x307a0200 0x00000016
|
||||
DATA 4 0x307a0204 0x00090909
|
||||
DATA 4 0x307a0210 0x00000f00
|
||||
DATA 4 0x307a0214 0x08080808
|
||||
DATA 4 0x307a0218 0x0f0f0808
|
||||
|
||||
DATA 4 0x307a0240 0x06000600
|
||||
DATA 4 0x307a0244 0x00000000
|
||||
DATA 4 0x30391000 0x00000000
|
||||
DATA 4 0x30790000 0x17421e40
|
||||
DATA 4 0x30790004 0x10210100
|
||||
DATA 4 0x30790008 0x00010000
|
||||
DATA 4 0x30790010 0x0007080c
|
||||
DATA 4 0x307900b0 0x1010007e
|
||||
|
||||
DATA 4 0x3079001C 0x01010000
|
||||
DATA 4 0x3079009c 0x00000b24
|
||||
|
||||
DATA 4 0x30790030 0x06060606
|
||||
DATA 4 0x30790020 0x0a0a0a0a
|
||||
DATA 4 0x30790050 0x01000008
|
||||
DATA 4 0x30790050 0x00000008
|
||||
DATA 4 0x30790018 0x0000000f
|
||||
DATA 4 0x307900c0 0x0e487304
|
||||
DATA 4 0x307900c0 0x0e4c7304
|
||||
DATA 4 0x307900c0 0x0e4c7306
|
||||
CHECK_BITS_SET 4 0x307900c4 0x1
|
||||
|
||||
DATA 4 0x307900c0 0x0e487304
|
||||
|
||||
DATA 4 0x30384130 0x00000000
|
||||
DATA 4 0x30340020 0x00000178
|
||||
DATA 4 0x30384130 0x00000002
|
||||
|
||||
CHECK_BITS_SET 4 0x307a0004 0x1
|
||||
#endif
|
|
@ -0,0 +1,117 @@
|
|||
/*
|
||||
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Refer docs/README.imxmage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
|
||||
/* image version */
|
||||
|
||||
IMAGE_VERSION 2
|
||||
|
||||
/*
|
||||
* Boot Device : one of
|
||||
* spi/sd/nand/onenand, qspi/nor
|
||||
*/
|
||||
|
||||
BOOT_FROM sd
|
||||
|
||||
#ifdef CONFIG_USE_IMXIMG_PLUGIN
|
||||
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
|
||||
PLUGIN board/freescale/mx7d_19x19_lpddr3_arm2/plugin.bin 0x00910000
|
||||
#else
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT
|
||||
CSF CONFIG_CSF_SIZE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Device Configuration Data (DCD)
|
||||
*
|
||||
* Each entry must have the format:
|
||||
* Addr-type Address Value
|
||||
*
|
||||
* where:
|
||||
* Addr-type register length (1,2 or 4 bytes)
|
||||
* Address absolute address of the register
|
||||
* value value to be stored in the register
|
||||
*/
|
||||
|
||||
DATA 4 0x30340004 0x4F400005
|
||||
|
||||
DATA 4 0x30391000 0x00000002
|
||||
DATA 4 0x307a0000 0x03040008
|
||||
DATA 4 0x307a0064 0x00200038
|
||||
DATA 4 0x307a0490 0x00000001
|
||||
DATA 4 0x307a00d0 0x00350001
|
||||
DATA 4 0x307a00dc 0x00c3000a
|
||||
DATA 4 0x307a00e0 0x00010000
|
||||
DATA 4 0x307a00e4 0x00110006
|
||||
DATA 4 0x307a00f4 0x0000033f
|
||||
DATA 4 0x307a0100 0x0a0e110b
|
||||
DATA 4 0x307a0104 0x00020211
|
||||
DATA 4 0x307a0108 0x03060708
|
||||
DATA 4 0x307a010c 0x00a0500c
|
||||
DATA 4 0x307a0110 0x05020307
|
||||
DATA 4 0x307a0114 0x02020404
|
||||
DATA 4 0x307a0118 0x02020003
|
||||
DATA 4 0x307a011c 0x00000202
|
||||
DATA 4 0x307a0120 0x00000202
|
||||
|
||||
DATA 4 0x307a0180 0x00600018
|
||||
DATA 4 0x307a0184 0x00e00100
|
||||
DATA 4 0x307a0190 0x02098205
|
||||
DATA 4 0x307a0194 0x00060303
|
||||
DATA 4 0x307a01a0 0x80400003
|
||||
DATA 4 0x307a01a4 0x00100020
|
||||
DATA 4 0x307a01a8 0x80100004
|
||||
|
||||
DATA 4 0x307a0200 0x00000016
|
||||
DATA 4 0x307a0204 0x00090909
|
||||
DATA 4 0x307a0210 0x00000f00
|
||||
DATA 4 0x307a0214 0x08080808
|
||||
DATA 4 0x307a0218 0x0f0f0808
|
||||
|
||||
DATA 4 0x307a0240 0x06000601
|
||||
DATA 4 0x307a0244 0x00000000
|
||||
DATA 4 0x30391000 0x00000000
|
||||
DATA 4 0x30790000 0x17421e40
|
||||
DATA 4 0x30790004 0x10210100
|
||||
DATA 4 0x30790008 0x00010000
|
||||
DATA 4 0x30790010 0x0007080c
|
||||
DATA 4 0x3079007c 0x1c1c1c1c
|
||||
DATA 4 0x30790080 0x1c1c1c1c
|
||||
DATA 4 0x30790084 0x30301c1c
|
||||
DATA 4 0x30790088 0x00000030
|
||||
DATA 4 0x3079006c 0x30303030
|
||||
DATA 4 0x307900b0 0x1010007e
|
||||
|
||||
DATA 4 0x3079001C 0x01010000
|
||||
DATA 4 0x3079009c 0x0db60d6e
|
||||
|
||||
DATA 4 0x30790030 0x06060606
|
||||
DATA 4 0x30790020 0x0a0a0a0a
|
||||
DATA 4 0x30790050 0x01000008
|
||||
DATA 4 0x30790050 0x00000008
|
||||
DATA 4 0x30790018 0x0000000f
|
||||
DATA 4 0x307900c0 0x1e487304
|
||||
DATA 4 0x307900c0 0x1e487304
|
||||
DATA 4 0x307900c0 0x1e487306
|
||||
DATA 4 0x307900c0 0x1e4c7304
|
||||
CHECK_BITS_SET 4 0x307900c4 0x1
|
||||
|
||||
DATA 4 0x307900c0 0x1e487304
|
||||
|
||||
DATA 4 0x30384130 0x00000000
|
||||
DATA 4 0x30340020 0x00000178
|
||||
DATA 4 0x30384130 0x00000002
|
||||
|
||||
CHECK_BITS_SET 4 0x307a0004 0x1
|
||||
#endif
|
|
@ -0,0 +1,119 @@
|
|||
/*
|
||||
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Refer docs/README.imxmage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
|
||||
/* image version */
|
||||
|
||||
IMAGE_VERSION 2
|
||||
|
||||
/*
|
||||
* Boot Device : one of
|
||||
* spi/sd/nand/onenand, qspi/nor
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SYS_BOOT_QSPI
|
||||
BOOT_FROM qspi
|
||||
#elif defined(CONFIG_SYS_BOOT_EIMNOR)
|
||||
BOOT_FROM nor
|
||||
#else
|
||||
BOOT_FROM sd
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USE_PLUGIN
|
||||
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
|
||||
PLUGIN board/freescale/mx7d_19x19_lpddr3_arm2/plugin.bin 0x00910000
|
||||
#else
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT
|
||||
CSF CONFIG_CSF_SIZE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Device Configuration Data (DCD)
|
||||
*
|
||||
* Each entry must have the format:
|
||||
* Addr-type Address Value
|
||||
*
|
||||
* where:
|
||||
* Addr-type register length (1,2 or 4 bytes)
|
||||
* Address absolute address of the register
|
||||
* value value to be stored in the register
|
||||
*/
|
||||
|
||||
DATA 4 0x30340004 0x4F400005
|
||||
|
||||
DATA 4 0x30391000 0x00000002
|
||||
DATA 4 0x307a0000 0x03020004
|
||||
DATA 4 0x307a01a0 0x80400003
|
||||
DATA 4 0x307a01a4 0x00100020
|
||||
DATA 4 0x307a01a8 0x80100004
|
||||
DATA 4 0x307a0064 0x00200023
|
||||
DATA 4 0x307a0490 0x00000001
|
||||
DATA 4 0x307a00d0 0x00350001
|
||||
DATA 4 0x307a00d8 0x00001105
|
||||
DATA 4 0x307a00dc 0x00c20006
|
||||
DATA 4 0x307a00e0 0x00020000
|
||||
DATA 4 0x307a00e4 0x00110006
|
||||
DATA 4 0x307a00f4 0x0000033f
|
||||
DATA 4 0x307a0100 0x080e110b
|
||||
DATA 4 0x307a0104 0x00020211
|
||||
DATA 4 0x307a0108 0x02040706
|
||||
DATA 4 0x307a010c 0x00504000
|
||||
DATA 4 0x307a0110 0x05010307
|
||||
DATA 4 0x307a0114 0x02020404
|
||||
DATA 4 0x307a0118 0x02020003
|
||||
DATA 4 0x307a011c 0x00000202
|
||||
DATA 4 0x307a0120 0x00000202
|
||||
|
||||
DATA 4 0x307a0180 0x00600018
|
||||
DATA 4 0x307a0184 0x00e00100
|
||||
DATA 4 0x307a0190 0x02098203
|
||||
DATA 4 0x307a0194 0x00060303
|
||||
|
||||
DATA 4 0x307a0200 0x00000015
|
||||
DATA 4 0x307a0204 0x00161616
|
||||
DATA 4 0x307a0210 0x00000f0f
|
||||
DATA 4 0x307a0214 0x04040404
|
||||
DATA 4 0x307a0218 0x0f0f0404
|
||||
|
||||
DATA 4 0x307a0240 0x06000600
|
||||
DATA 4 0x307a0244 0x00000000
|
||||
DATA 4 0x30391000 0x00000000
|
||||
DATA 4 0x30790000 0x17421640
|
||||
DATA 4 0x30790004 0x10210100
|
||||
DATA 4 0x30790008 0x00010000
|
||||
DATA 4 0x30790010 0x00050408
|
||||
DATA 4 0x307900b0 0x1010007e
|
||||
|
||||
DATA 4 0x3079001C 0x01010000
|
||||
DATA 4 0x3079009C 0x00000d6e
|
||||
DATA 4 0x30790018 0x0000000f
|
||||
|
||||
DATA 4 0x30790030 0x06060606
|
||||
DATA 4 0x30790020 0x0a0a0a0a
|
||||
DATA 4 0x30790050 0x01000008
|
||||
DATA 4 0x30790050 0x00000008
|
||||
DATA 4 0x307900c0 0x0e487304
|
||||
DATA 4 0x307900c0 0x0e4c7304
|
||||
DATA 4 0x307900c0 0x0e4c7306
|
||||
CHECK_BITS_SET 4 0x307900c4 0x1
|
||||
|
||||
DATA 4 0x307900c0 0x0e4c7304
|
||||
DATA 4 0x307900c0 0x0e487304
|
||||
|
||||
DATA 4 0x30384130 0x00000000
|
||||
DATA 4 0x30340020 0x000001f8
|
||||
DATA 4 0x30384130 0x00000002
|
||||
|
||||
CHECK_BITS_SET 4 0x307a0004 0x1
|
||||
#endif
|
|
@ -0,0 +1,124 @@
|
|||
/*
|
||||
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
* Refer docs/README.imxmage for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
|
||||
/* image version */
|
||||
|
||||
IMAGE_VERSION 2
|
||||
|
||||
/*
|
||||
* Boot Device : one of
|
||||
* spi/sd/nand/onenand, qspi/nor
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SYS_BOOT_QSPI
|
||||
BOOT_FROM qspi
|
||||
#elif defined(CONFIG_SYS_BOOT_EIMNOR)
|
||||
BOOT_FROM nor
|
||||
#else
|
||||
BOOT_FROM sd
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USE_PLUGIN
|
||||
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
|
||||
PLUGIN board/freescale/mx7d_19x19_lpddr3_arm2/plugin.bin 0x00910000
|
||||
#else
|
||||
|
||||
#ifdef CONFIG_SECURE_BOOT
|
||||
CSF CONFIG_CSF_SIZE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Device Configuration Data (DCD)
|
||||
*
|
||||
* Each entry must have the format:
|
||||
* Addr-type Address Value
|
||||
*
|
||||
* where:
|
||||
* Addr-type register length (1,2 or 4 bytes)
|
||||
* Address absolute address of the register
|
||||
* value value to be stored in the register
|
||||
*/
|
||||
|
||||
DATA 4 0x30340004 0x4F400005
|
||||
|
||||
DATA 4 0x30391000 0x00000002
|
||||
DATA 4 0x307a0000 0x03020004
|
||||
DATA 4 0x307a01a0 0x80400003
|
||||
DATA 4 0x307a01a4 0x00100020
|
||||
DATA 4 0x307a01a8 0x80100004
|
||||
DATA 4 0x307a0064 0x00200023
|
||||
DATA 4 0x307a0490 0x00000001
|
||||
DATA 4 0x307a00d0 0x00350001
|
||||
DATA 4 0x307a00d8 0x00001105
|
||||
DATA 4 0x307a00dc 0x00c20006
|
||||
DATA 4 0x307a00e0 0x00020000
|
||||
DATA 4 0x307a00e4 0x00110006
|
||||
DATA 4 0x307a00f4 0x0000033f
|
||||
DATA 4 0x307a0100 0x080e110b
|
||||
DATA 4 0x307a0104 0x00020211
|
||||
DATA 4 0x307a0108 0x02040706
|
||||
DATA 4 0x307a010c 0x00504000
|
||||
DATA 4 0x307a0110 0x05010307
|
||||
DATA 4 0x307a0114 0x02020404
|
||||
DATA 4 0x307a0118 0x02020003
|
||||
DATA 4 0x307a011c 0x00000202
|
||||
DATA 4 0x307a0120 0x00000202
|
||||
|
||||
DATA 4 0x307a0180 0x00600018
|
||||
DATA 4 0x307a0184 0x00e00100
|
||||
DATA 4 0x307a0190 0x02098203
|
||||
DATA 4 0x307a0194 0x00060303
|
||||
|
||||
DATA 4 0x307a0200 0x00000015
|
||||
DATA 4 0x307a0204 0x00161616
|
||||
DATA 4 0x307a0210 0x00000f0f
|
||||
DATA 4 0x307a0214 0x04040404
|
||||
DATA 4 0x307a0218 0x0f0f0404
|
||||
|
||||
DATA 4 0x307a0240 0x06000600
|
||||
DATA 4 0x307a0244 0x00000000
|
||||
DATA 4 0x30391000 0x00000000
|
||||
DATA 4 0x30790000 0x17421640
|
||||
DATA 4 0x30790004 0x10210100
|
||||
DATA 4 0x30790008 0x00010000
|
||||
DATA 4 0x30790010 0x00050408
|
||||
DATA 4 0x307900b0 0x1010007e
|
||||
|
||||
DATA 4 0x3079001C 0x01010000
|
||||
DATA 4 0x3079009C 0x00000dee
|
||||
DATA 4 0x3079007c 0x08080808
|
||||
DATA 4 0x30790080 0x08080808
|
||||
DATA 4 0x30790084 0x0a0a0808
|
||||
DATA 4 0x30790088 0x0000000a
|
||||
DATA 4 0x3079006c 0x0a0a0a0a
|
||||
DATA 4 0x30790018 0x0000000f
|
||||
|
||||
DATA 4 0x30790030 0x06060606
|
||||
DATA 4 0x30790020 0x0a0a0a0a
|
||||
DATA 4 0x30790050 0x01000008
|
||||
DATA 4 0x30790050 0x00000008
|
||||
DATA 4 0x307900c0 0x0e487304
|
||||
DATA 4 0x307900c0 0x0e4c7304
|
||||
DATA 4 0x307900c0 0x0e4c7306
|
||||
CHECK_BITS_SET 4 0x307900c4 0x1
|
||||
|
||||
DATA 4 0x307900c0 0x0e4c7304
|
||||
DATA 4 0x307900c0 0x0e487304
|
||||
|
||||
DATA 4 0x30384130 0x00000000
|
||||
DATA 4 0x30340020 0x000001f8
|
||||
DATA 4 0x30384130 0x00000002
|
||||
|
||||
CHECK_BITS_SET 4 0x307a0004 0x1
|
||||
#endif
|
|
@ -0,0 +1,640 @@
|
|||
/*
|
||||
* Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/mx7-pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
#include <asm/mach-imx/boot_mode.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <common.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#include <mmc.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <power/pmic.h>
|
||||
#include <power/pfuze3000_pmic.h>
|
||||
#include "../common/pfuze.h"
|
||||
#ifdef CONFIG_SYS_I2C
|
||||
#include <i2c.h>
|
||||
#include <asm/mach-imx/mxc_i2c.h>
|
||||
#endif
|
||||
#include <asm/arch/crm_regs.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
|
||||
PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
|
||||
|
||||
#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
|
||||
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
|
||||
|
||||
#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
|
||||
#define ENET_PAD_CTRL_MII (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
|
||||
|
||||
#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM)
|
||||
|
||||
#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
|
||||
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
|
||||
|
||||
#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
|
||||
PAD_CTL_DSE_3P3V_49OHM)
|
||||
|
||||
#define QSPI_PAD_CTRL \
|
||||
(PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
|
||||
|
||||
#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
|
||||
|
||||
#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
|
||||
|
||||
#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
|
||||
|
||||
#define WEIM_NOR_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | \
|
||||
PAD_CTL_PUS_PU100KOHM)
|
||||
|
||||
|
||||
#ifdef CONFIG_SYS_I2C
|
||||
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
|
||||
/* I2C1 for PMIC */
|
||||
struct i2c_pads_info i2c_pad_info1 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC,
|
||||
.gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC,
|
||||
.gp = IMX_GPIO_NR(4, 8),
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC,
|
||||
.gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC,
|
||||
.gp = IMX_GPIO_NR(4, 9),
|
||||
},
|
||||
};
|
||||
|
||||
/* I2C2 */
|
||||
struct i2c_pads_info i2c_pad_info2 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX7D_PAD_I2C2_SCL__I2C2_SCL | PC,
|
||||
.gpio_mode = MX7D_PAD_I2C2_SCL__GPIO4_IO10 | PC,
|
||||
.gp = IMX_GPIO_NR(4, 10),
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX7D_PAD_I2C2_SDA__I2C2_SDA | PC,
|
||||
.gpio_mode = MX7D_PAD_I2C2_SDA__GPIO4_IO11 | PC,
|
||||
.gp = IMX_GPIO_NR(4, 11),
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = PHYS_SDRAM_SIZE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static iomux_v3_cfg_t const uart1_pads[] = {
|
||||
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const usdhc1_pads[] = {
|
||||
MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
|
||||
MX7D_PAD_GPIO1_IO08__SD1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
|
||||
MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
};
|
||||
|
||||
#ifdef CONFIG_MTD_NOR_FLASH
|
||||
static iomux_v3_cfg_t const eimnor_pads[] = {
|
||||
MX7D_PAD_LCD_DATA00__EIM_DATA0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA01__EIM_DATA1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA02__EIM_DATA2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA03__EIM_DATA3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA04__EIM_DATA4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA05__EIM_DATA5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA06__EIM_DATA6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA07__EIM_DATA7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA08__EIM_DATA8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA09__EIM_DATA9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA10__EIM_DATA10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA11__EIM_DATA11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA12__EIM_DATA12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA13__EIM_DATA13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA14__EIM_DATA14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA15__EIM_DATA15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
|
||||
MX7D_PAD_EPDC_DATA00__EIM_AD0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA01__EIM_AD1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA02__EIM_AD2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA03__EIM_AD3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA04__EIM_AD4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA05__EIM_AD5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA06__EIM_AD6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA07__EIM_AD7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_BDR1__EIM_AD8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_PWR_COM__EIM_AD9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDCLK__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDLE__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDOE__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDSHR__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDCE0__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDCE1__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_GDOE__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_GDRL__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_GDSP__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_BDR0__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA20__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA21__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_LCD_DATA22__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
|
||||
MX7D_PAD_EPDC_DATA08__EIM_OE | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA09__EIM_RW | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA10__EIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA12__EIM_LBA_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA13__EIM_WAIT | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void eimnor_cs_setup(void)
|
||||
{
|
||||
writel(0x00000120, WEIM_IPS_BASE_ADDR + 0x090);
|
||||
writel(0x00210081, WEIM_IPS_BASE_ADDR + 0x000);
|
||||
writel(0x00000001, WEIM_IPS_BASE_ADDR + 0x004);
|
||||
writel(0x0e020000, WEIM_IPS_BASE_ADDR + 0x008);
|
||||
writel(0x00000000, WEIM_IPS_BASE_ADDR + 0x00c);
|
||||
writel(0x0704a040, WEIM_IPS_BASE_ADDR + 0x010);
|
||||
}
|
||||
|
||||
static void setup_eimnor(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(eimnor_pads,
|
||||
ARRAY_SIZE(eimnor_pads));
|
||||
|
||||
eimnor_cs_setup();
|
||||
}
|
||||
#endif
|
||||
|
||||
static iomux_v3_cfg_t const per_rst_pads[] = {
|
||||
MX7D_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const wdog_pads[] = {
|
||||
MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
static iomux_v3_cfg_t const fec2_pads[] = {
|
||||
MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_fec2(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
|
||||
}
|
||||
#endif
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_QSPI
|
||||
#ifndef CONFIG_DM_SPI
|
||||
static iomux_v3_cfg_t const quadspi_pads[] = {
|
||||
MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA04__QSPI_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
|
||||
MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA12__QSPI_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL),
|
||||
|
||||
};
|
||||
#endif
|
||||
|
||||
int board_qspi_init(void)
|
||||
{
|
||||
#ifndef CONFIG_DM_SPI
|
||||
/* Set the iomux */
|
||||
imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
|
||||
#endif
|
||||
|
||||
/* Set the clock */
|
||||
set_clk_qspi();
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NAND_MXS
|
||||
static iomux_v3_cfg_t const gpmi_pads[] = {
|
||||
MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SAI1_MCLK__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL),
|
||||
MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
|
||||
};
|
||||
|
||||
static void setup_gpmi_nand(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
|
||||
|
||||
/*
|
||||
* NAND_USDHC_BUS_CLK is set in rom
|
||||
*/
|
||||
|
||||
set_clk_nand();
|
||||
|
||||
/*
|
||||
* APBH clock root is set in init_esdhc, USDHC3_CLK.
|
||||
* There is no clk gate for APBHDMA.
|
||||
* No touch here.
|
||||
*/
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
|
||||
#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0)
|
||||
#define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2)
|
||||
|
||||
|
||||
static struct fsl_esdhc_cfg usdhc_cfg[1] = {
|
||||
{USDHC1_BASE_ADDR, 0, 4},
|
||||
};
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
int ret = 0;
|
||||
|
||||
switch (cfg->esdhc_base) {
|
||||
case USDHC1_BASE_ADDR:
|
||||
ret = !gpio_get_value(USDHC1_CD_GPIO);
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
int i, ret;
|
||||
/*
|
||||
* According to the board_mmc_init() the following map is done:
|
||||
* (U-boot device node) (Physical Port)
|
||||
* mmc0 USDHC1
|
||||
*/
|
||||
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
|
||||
switch (i) {
|
||||
case 0:
|
||||
imx_iomux_v3_setup_multiple_pads(
|
||||
usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
|
||||
gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
|
||||
gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr");
|
||||
gpio_direction_input(USDHC1_CD_GPIO);
|
||||
gpio_direction_output(USDHC1_PWR_GPIO, 0);
|
||||
udelay(500);
|
||||
gpio_direction_output(USDHC1_PWR_GPIO, 1);
|
||||
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
|
||||
break;
|
||||
default:
|
||||
printf("Warning: you configured more USDHC controllers"
|
||||
"(%d) than supported by the board\n", i + 1);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
|
||||
if (ret) {
|
||||
printf("Warning: failed to initialize mmc dev %d\n", i);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int ret;
|
||||
|
||||
setup_iomux_fec2();
|
||||
|
||||
ret = fecmxc_initialize_multi(bis, 0,
|
||||
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
|
||||
if (ret)
|
||||
printf("FEC1 MXC: %s:failed\n", __func__);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int setup_fec(void)
|
||||
{
|
||||
struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
|
||||
= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
|
||||
int ret;
|
||||
|
||||
/* Use 125M anatop REF_CLK for ENET2, clear gpr1[14], gpr1[18]*/
|
||||
clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
|
||||
(IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK |
|
||||
IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0);
|
||||
|
||||
ret = set_clk_enet(ENET_125MHZ);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
/* Enable 1.8V(SEL_1P5_1P8_POS_REG) on
|
||||
Phy control debug reg 0 */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
|
||||
|
||||
/* rgmii tx clock delay enable */
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
|
||||
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MXC_SPI
|
||||
iomux_v3_cfg_t const ecspi1_pads[] = {
|
||||
MX7D_PAD_UART3_RX_DATA__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX7D_PAD_UART3_TX_DATA__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
MX7D_PAD_UART3_RTS_B__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
|
||||
|
||||
/* CS0 */
|
||||
MX7D_PAD_UART3_CTS_B__GPIO4_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
void setup_spinor(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
|
||||
ARRAY_SIZE(ecspi1_pads));
|
||||
gpio_direction_output(IMX_GPIO_NR(4, 7), 0);
|
||||
}
|
||||
|
||||
int board_spi_cs_gpio(unsigned bus, unsigned cs)
|
||||
{
|
||||
return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 7)) : -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX7
|
||||
#ifndef CONFIG_DM_USB
|
||||
|
||||
iomux_v3_cfg_t const usb_otg1_pads[] = {
|
||||
MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t const usb_otg2_pads[] = {
|
||||
MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_usb(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, ARRAY_SIZE(usb_otg1_pads));
|
||||
imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, ARRAY_SIZE(usb_otg2_pads));
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_uart();
|
||||
|
||||
#ifdef CONFIG_SYS_I2C
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
||||
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX7
|
||||
#ifndef CONFIG_DM_USB
|
||||
setup_usb();
|
||||
#endif
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
/* Reset peripherals */
|
||||
imx_iomux_v3_setup_multiple_pads(per_rst_pads, ARRAY_SIZE(per_rst_pads));
|
||||
|
||||
gpio_request(IMX_GPIO_NR(1, 3), "per rst");
|
||||
gpio_direction_output(IMX_GPIO_NR(1, 3) , 0);
|
||||
udelay(500);
|
||||
gpio_set_value(IMX_GPIO_NR(1, 3), 1);
|
||||
|
||||
#ifdef CONFIG_MXC_SPI
|
||||
setup_spinor();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MTD_NOR_FLASH
|
||||
setup_eimnor();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NAND_MXS
|
||||
setup_gpmi_nand();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
setup_fec();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_QSPI
|
||||
board_qspi_init();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
static const struct boot_mode board_boot_modes[] = {
|
||||
/* 4 bit bus width */
|
||||
{"sd1", MAKE_CFGVAL(0x10, 0x12, 0x00, 0x00)},
|
||||
{"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)},
|
||||
{NULL, 0},
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_POWER
|
||||
#define I2C_PMIC 0
|
||||
int power_init_board(void)
|
||||
{
|
||||
struct pmic *p;
|
||||
int ret;
|
||||
unsigned int reg, rev_id;
|
||||
|
||||
ret = power_pfuze3000_init(I2C_PMIC);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
p = pmic_get("PFUZE3000");
|
||||
ret = pmic_probe(p);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
|
||||
pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
|
||||
printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
|
||||
|
||||
/* disable Low Power Mode during standby mode */
|
||||
pmic_reg_read(p, PFUZE3000_LDOGCTL, ®);
|
||||
reg |= 0x1;
|
||||
pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
|
||||
|
||||
/* SW1A/1B mode set to APS/APS */
|
||||
reg = 0x8;
|
||||
pmic_reg_write(p, PFUZE3000_SW1AMODE, reg);
|
||||
pmic_reg_write(p, PFUZE3000_SW1BMODE, reg);
|
||||
|
||||
/* SW1A/1B standby voltage set to 0.975V */
|
||||
reg = 0xb;
|
||||
pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg);
|
||||
pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg);
|
||||
|
||||
/* set SW1B normal voltage to 0.975V */
|
||||
pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®);
|
||||
reg &= ~0x1f;
|
||||
reg |= PFUZE3000_SW1AB_SETP(9750);
|
||||
pmic_reg_write(p, PFUZE3000_SW1BVOLT, reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#elif defined(CONFIG_DM_PMIC_PFUZE100)
|
||||
int power_init_board(void)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret, dev_id, rev_id, reg;
|
||||
|
||||
ret = pmic_get("pfuze3000", &dev);
|
||||
if (ret == -ENODEV)
|
||||
return 0;
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
|
||||
dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
|
||||
rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
|
||||
printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
|
||||
|
||||
/* disable Low Power Mode during standby mode */
|
||||
reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
|
||||
reg |= 0x1;
|
||||
pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
|
||||
|
||||
/* SW1A/1B mode set to APS/APS */
|
||||
reg = 0x8;
|
||||
pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg);
|
||||
pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg);
|
||||
|
||||
/* SW1A/1B standby voltage set to 0.975V */
|
||||
reg = 0xb;
|
||||
pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg);
|
||||
pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg);
|
||||
|
||||
/* set SW1B normal voltage to 0.975V */
|
||||
reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
|
||||
reg &= ~0x1f;
|
||||
reg |= PFUZE3000_SW1AB_SETP(9750);
|
||||
pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
add_board_boot_modes(board_boot_modes);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_MMC
|
||||
board_late_mmc_env_init();
|
||||
#endif
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
|
||||
|
||||
set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
u32 get_board_rev(void)
|
||||
{
|
||||
return get_cpu_rev();
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
#ifdef CONFIG_TARGET_MX7D_19X19_LPDDR2_ARM2
|
||||
puts("Board: MX7D 19x19 LPDDR2 ARM2\n");
|
||||
#else
|
||||
puts("Board: MX7D 19x19 LPDDR3 ARM2\n");
|
||||
#endif
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,378 @@
|
|||
/*
|
||||
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
/* DDR script */
|
||||
.macro imx7d_ddrphy_lpddr3_latency_setting
|
||||
ldr r2, =ANATOP_BASE_ADDR
|
||||
ldr r3, [r2, #0x800]
|
||||
and r3, r3, #0xFF
|
||||
cmp r3, #0x11
|
||||
bne TUNE_END
|
||||
|
||||
/*TO 1.1*/
|
||||
ldr r1, =0x1c1c1c1c
|
||||
str r1, [r0, #0x7c]
|
||||
ldr r1, =0x1c1c1c1c
|
||||
str r1, [r0, #0x80]
|
||||
ldr r1, =0x30301c1c
|
||||
str r1, [r0, #0x84]
|
||||
ldr r1, =0x00000030
|
||||
str r1, [r0, #0x88]
|
||||
ldr r1, =0x30303030
|
||||
str r1, [r0, #0x6c]
|
||||
|
||||
TUNE_END:
|
||||
.endm
|
||||
|
||||
.macro imx7d_ddrphy_lpddr2_latency_setting
|
||||
ldr r2, =ANATOP_BASE_ADDR
|
||||
ldr r3, [r2, #0x800]
|
||||
and r3, r3, #0xFF
|
||||
cmp r3, #0x11
|
||||
bne NO_DELAY
|
||||
|
||||
/*TO 1.1*/
|
||||
ldr r1, =0x00000dee
|
||||
str r1, [r0, #0x9c]
|
||||
ldr r1, =0x08080808
|
||||
str r1, [r0, #0x7c]
|
||||
ldr r1, =0x08080808
|
||||
str r1, [r0, #0x80]
|
||||
ldr r1, =0x0a0a0808
|
||||
str r1, [r0, #0x84]
|
||||
ldr r1, =0x0000000a
|
||||
str r1, [r0, #0x88]
|
||||
ldr r1, =0x0a0a0a0a
|
||||
str r1, [r0, #0x6c]
|
||||
b TUNE_END
|
||||
|
||||
NO_DELAY:
|
||||
/*TO 1.0*/
|
||||
ldr r1, =0x00000d6e
|
||||
str r1, [r0, #0x9c]
|
||||
|
||||
TUNE_END:
|
||||
.endm
|
||||
|
||||
.macro imx7d_19x19_lpddr3_arm2_setting
|
||||
/* Configure ocram_epdc */
|
||||
ldr r0, =IOMUXC_GPR_BASE_ADDR
|
||||
ldr r1, =0x4f400005
|
||||
str r1, [r0, #0x4]
|
||||
|
||||
ldr r0, =SRC_BASE_ADDR
|
||||
ldr r1, =0x2
|
||||
ldr r2, =0x1000
|
||||
str r1, [r0, r2]
|
||||
|
||||
ldr r0, =DDRC_IPS_BASE_ADDR
|
||||
ldr r1, =0x03040008
|
||||
str r1, [r0]
|
||||
ldr r1, =0x00200038
|
||||
str r1, [r0, #0x64]
|
||||
ldr r1, =0x1
|
||||
str r1, [r0, #0x490]
|
||||
ldr r1, =0x00350001
|
||||
str r1, [r0, #0xd0]
|
||||
ldr r1, =0x00c3000a
|
||||
str r1, [r0, #0xdc]
|
||||
ldr r1, =0x00010000
|
||||
str r1, [r0, #0xe0]
|
||||
ldr r1, =0x00110006
|
||||
str r1, [r0, #0xe4]
|
||||
ldr r1, =0x33f
|
||||
str r1, [r0, #0xf4]
|
||||
ldr r1, =0x0a0e110b
|
||||
str r1, [r0, #0x100]
|
||||
ldr r1, =0x00020211
|
||||
str r1, [r0, #0x104]
|
||||
ldr r1, =0x03060708
|
||||
str r1, [r0, #0x108]
|
||||
ldr r1, =0x00a0500c
|
||||
str r1, [r0, #0x10c]
|
||||
ldr r1, =0x05020307
|
||||
str r1, [r0, #0x110]
|
||||
ldr r1, =0x02020404
|
||||
str r1, [r0, #0x114]
|
||||
ldr r1, =0x02020003
|
||||
str r1, [r0, #0x118]
|
||||
ldr r1, =0x00000202
|
||||
str r1, [r0, #0x11c]
|
||||
ldr r1, =0x00000202
|
||||
str r1, [r0, #0x120]
|
||||
ldr r1, =0x00600018
|
||||
str r1, [r0, #0x180]
|
||||
ldr r1, =0x00e00100
|
||||
str r1, [r0, #0x184]
|
||||
ldr r1, =0x02098205
|
||||
str r1, [r0, #0x190]
|
||||
ldr r1, =0x00060303
|
||||
str r1, [r0, #0x194]
|
||||
ldr r1, =0x80400003
|
||||
str r1, [r0, #0x1a0]
|
||||
ldr r1, =0x00100020
|
||||
str r1, [r0, #0x1a4]
|
||||
ldr r1, =0x80100004
|
||||
str r1, [r0, #0x1a8]
|
||||
|
||||
ldr r1, =0x00000016
|
||||
str r1, [r0, #0x200]
|
||||
ldr r1, =0x00090909
|
||||
str r1, [r0, #0x204]
|
||||
ldr r1, =0x00000f00
|
||||
str r1, [r0, #0x210]
|
||||
ldr r1, =0x08080808
|
||||
str r1, [r0, #0x214]
|
||||
ldr r1, =0x0f0f0808
|
||||
str r1, [r0, #0x218]
|
||||
|
||||
ldr r1, =0x06000600
|
||||
str r1, [r0, #0x240]
|
||||
mov r1, #0x0
|
||||
str r1, [r0, #0x244]
|
||||
|
||||
ldr r0, =SRC_BASE_ADDR
|
||||
mov r1, #0x0
|
||||
ldr r2, =0x1000
|
||||
str r1, [r0, r2]
|
||||
|
||||
ldr r0, =DDRPHY_IPS_BASE_ADDR
|
||||
ldr r1, =0x17421e40
|
||||
str r1, [r0]
|
||||
ldr r1, =0x10210100
|
||||
str r1, [r0, #0x4]
|
||||
ldr r1, =0x00010000
|
||||
str r1, [r0, #0x8]
|
||||
ldr r1, =0x0007080c
|
||||
str r1, [r0, #0x10]
|
||||
imx7d_ddrphy_lpddr3_latency_setting
|
||||
ldr r1, =0x1010007e
|
||||
str r1, [r0, #0xb0]
|
||||
ldr r1, =0x01010000
|
||||
str r1, [r0, #0x1c]
|
||||
|
||||
ldr r2, =ANATOP_BASE_ADDR
|
||||
ldr r3, [r2, #0x800]
|
||||
and r3, r3, #0xFF
|
||||
cmp r3, #0x11
|
||||
bne 1f
|
||||
|
||||
ldr r1, =0x0db60d6e
|
||||
str r1, [r0, #0x9c]
|
||||
b 2f
|
||||
1:
|
||||
ldr r1, =0x00000b24
|
||||
str r1, [r0, #0x9c]
|
||||
2:
|
||||
ldr r1, =0x06060606
|
||||
str r1, [r0, #0x30]
|
||||
ldr r1, =0x0a0a0a0a
|
||||
str r1, [r0, #0x20]
|
||||
ldr r1, =0x01000008
|
||||
str r1, [r0, #0x50]
|
||||
ldr r1, =0x00000008
|
||||
str r1, [r0, #0x50]
|
||||
|
||||
ldr r1, =0x0000000f
|
||||
str r1, [r0, #0x18]
|
||||
ldr r1, =0x0e487304
|
||||
str r1, [r0, #0xc0]
|
||||
ldr r1, =0x0e4c7304
|
||||
str r1, [r0, #0xc0]
|
||||
ldr r1, =0x0e4c7306
|
||||
str r1, [r0, #0xc0]
|
||||
|
||||
wait_zq:
|
||||
ldr r1, [r0, #0xc4]
|
||||
tst r1, #0x1
|
||||
beq wait_zq
|
||||
|
||||
ldr r1, =0x0e487304
|
||||
str r1, [r0, #0xc0]
|
||||
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
mov r1, #0x0
|
||||
ldr r2, =0x4130
|
||||
str r1, [r0, r2]
|
||||
ldr r0, =IOMUXC_GPR_BASE_ADDR
|
||||
mov r1, #0x178
|
||||
str r1, [r0, #0x20]
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
mov r1, #0x2
|
||||
ldr r2, =0x4130
|
||||
str r1, [r0, r2]
|
||||
|
||||
ldr r0, =DDRC_IPS_BASE_ADDR
|
||||
wait_stat:
|
||||
ldr r1, [r0, #0x4]
|
||||
tst r1, #0x1
|
||||
beq wait_stat
|
||||
.endm
|
||||
|
||||
.macro imx7d_19x19_lpddr2_arm2_setting
|
||||
/* Configure ocram_epdc */
|
||||
ldr r0, =IOMUXC_GPR_BASE_ADDR
|
||||
ldr r1, =0x4f400005
|
||||
str r1, [r0, #0x4]
|
||||
|
||||
ldr r0, =SRC_BASE_ADDR
|
||||
ldr r1, =0x2
|
||||
ldr r2, =0x1000
|
||||
str r1, [r0, r2]
|
||||
|
||||
ldr r0, =DDRC_IPS_BASE_ADDR
|
||||
ldr r1, =0x03020004
|
||||
str r1, [r0]
|
||||
ldr r1, =0x80400003
|
||||
str r1, [r0, #0x1a0]
|
||||
ldr r1, =0x00100020
|
||||
str r1, [r0, #0x1a4]
|
||||
ldr r1, =0x80100004
|
||||
str r1, [r0, #0x1a8]
|
||||
ldr r1, =0x00200023
|
||||
str r1, [r0, #0x64]
|
||||
ldr r1, =0x1
|
||||
str r1, [r0, #0x490]
|
||||
ldr r1, =0x00350001
|
||||
str r1, [r0, #0xd0]
|
||||
ldr r1, =0x00001105
|
||||
str r1, [r0, #0xd8]
|
||||
ldr r1, =0x00c20006
|
||||
str r1, [r0, #0xdc]
|
||||
ldr r1, =0x00020000
|
||||
str r1, [r0, #0xe0]
|
||||
ldr r1, =0x00110006
|
||||
str r1, [r0, #0xe4]
|
||||
ldr r1, =0x33f
|
||||
str r1, [r0, #0xf4]
|
||||
ldr r1, =0x080e110b
|
||||
str r1, [r0, #0x100]
|
||||
ldr r1, =0x00020211
|
||||
str r1, [r0, #0x104]
|
||||
ldr r1, =0x02040706
|
||||
str r1, [r0, #0x108]
|
||||
ldr r1, =0x00504000
|
||||
str r1, [r0, #0x10c]
|
||||
ldr r1, =0x05010307
|
||||
str r1, [r0, #0x110]
|
||||
ldr r1, =0x02020404
|
||||
str r1, [r0, #0x114]
|
||||
ldr r1, =0x02020003
|
||||
str r1, [r0, #0x118]
|
||||
ldr r1, =0x00000202
|
||||
str r1, [r0, #0x11c]
|
||||
ldr r1, =0x00000202
|
||||
str r1, [r0, #0x120]
|
||||
ldr r1, =0x00600018
|
||||
str r1, [r0, #0x180]
|
||||
ldr r1, =0x00e00100
|
||||
str r1, [r0, #0x184]
|
||||
ldr r1, =0x02098203
|
||||
str r1, [r0, #0x190]
|
||||
ldr r1, =0x00060303
|
||||
str r1, [r0, #0x194]
|
||||
|
||||
ldr r1, =0x00000015
|
||||
str r1, [r0, #0x200]
|
||||
ldr r1, =0x00161616
|
||||
str r1, [r0, #0x204]
|
||||
ldr r1, =0x00000f0f
|
||||
str r1, [r0, #0x210]
|
||||
ldr r1, =0x04040404
|
||||
str r1, [r0, #0x214]
|
||||
ldr r1, =0x0f0f0404
|
||||
str r1, [r0, #0x218]
|
||||
|
||||
ldr r1, =0x06000600
|
||||
str r1, [r0, #0x240]
|
||||
mov r1, #0x0
|
||||
str r1, [r0, #0x244]
|
||||
|
||||
ldr r0, =SRC_BASE_ADDR
|
||||
mov r1, #0x0
|
||||
ldr r2, =0x1000
|
||||
str r1, [r0, r2]
|
||||
|
||||
ldr r0, =DDRPHY_IPS_BASE_ADDR
|
||||
ldr r1, =0x17421640
|
||||
str r1, [r0]
|
||||
ldr r1, =0x10210100
|
||||
str r1, [r0, #0x4]
|
||||
ldr r1, =0x00010000
|
||||
str r1, [r0, #0x8]
|
||||
ldr r1, =0x00050408
|
||||
str r1, [r0, #0x10]
|
||||
ldr r1, =0x1010007e
|
||||
str r1, [r0, #0xb0]
|
||||
ldr r1, =0x01010000
|
||||
str r1, [r0, #0x1c]
|
||||
imx7d_ddrphy_lpddr2_latency_setting
|
||||
ldr r1, =0x0000000f
|
||||
str r1, [r0, #0x18]
|
||||
|
||||
ldr r1, =0x06060606
|
||||
str r1, [r0, #0x30]
|
||||
ldr r1, =0x0a0a0a0a
|
||||
str r1, [r0, #0x20]
|
||||
ldr r1, =0x01000008
|
||||
str r1, [r0, #0x50]
|
||||
ldr r1, =0x00000008
|
||||
str r1, [r0, #0x50]
|
||||
|
||||
ldr r1, =0x0e487304
|
||||
str r1, [r0, #0xc0]
|
||||
ldr r1, =0x0e4c7304
|
||||
str r1, [r0, #0xc0]
|
||||
ldr r1, =0x0e4c7306
|
||||
str r1, [r0, #0xc0]
|
||||
|
||||
wait_zq:
|
||||
ldr r1, [r0, #0xc4]
|
||||
tst r1, #0x1
|
||||
beq wait_zq
|
||||
|
||||
ldr r1, =0x0e4c7304
|
||||
str r1, [r0, #0xc0]
|
||||
ldr r1, =0x0e487304
|
||||
str r1, [r0, #0xc0]
|
||||
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
mov r1, #0x0
|
||||
ldr r2, =0x4130
|
||||
str r1, [r0, r2]
|
||||
ldr r0, =IOMUXC_GPR_BASE_ADDR
|
||||
mov r1, #0x1f8
|
||||
str r1, [r0, #0x20]
|
||||
ldr r0, =CCM_BASE_ADDR
|
||||
mov r1, #0x2
|
||||
ldr r2, =0x4130
|
||||
str r1, [r0, r2]
|
||||
|
||||
ldr r0, =DDRC_IPS_BASE_ADDR
|
||||
wait_stat:
|
||||
ldr r1, [r0, #0x4]
|
||||
tst r1, #0x1
|
||||
beq wait_stat
|
||||
.endm
|
||||
|
||||
.macro imx7_clock_gating
|
||||
.endm
|
||||
|
||||
.macro imx7_qos_setting
|
||||
.endm
|
||||
|
||||
.macro imx7_ddr_setting
|
||||
#if defined (TARGET_MX7D_19X19_LPDDR2_ARM2)
|
||||
imx7d_19x19_lpddr2_arm2_setting
|
||||
#else
|
||||
imx7d_19x19_lpddr3_arm2_setting
|
||||
#endif
|
||||
.endm
|
||||
|
||||
/* include the common plugin code here */
|
||||
#include <asm/arch/mx7_plugin.S>
|
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration settings for the Freescale i.MX7D 19x19 DDR3 ARM2 board.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __MX7D_19X19_DDR3_ARM2_CONFIG_H
|
||||
#define __MX7D_19X19_DDR3_ARM2_CONFIG_H
|
||||
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 3
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
|
||||
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
|
||||
|
||||
#define PHYS_SDRAM_SIZE SZ_1G
|
||||
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#ifdef CONFIG_DM_ETH
|
||||
#define CONFIG_ETHPRIME "eth0"
|
||||
#else
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
#endif
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0
|
||||
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_ATHEROS
|
||||
|
||||
/* ENET2 */
|
||||
#define IMX_FEC_BASE ENET2_IPS_BASE_ADDR
|
||||
|
||||
#define CONFIG_FEC_MXC_MDIO_BASE ENET_IPS_BASE_ADDR
|
||||
|
||||
/* For QSPI, not use DM driver, because DTS does not have it supported */
|
||||
#ifdef CONFIG_SPI_BOOT
|
||||
#define CONFIG_MXC_SPI
|
||||
#endif
|
||||
|
||||
#define CONFIG_FSL_QSPI /* Enable the QSPI flash at default */
|
||||
|
||||
#ifndef CONFIG_DM_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#endif
|
||||
#ifdef CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
#endif
|
||||
|
||||
/* PMIC */
|
||||
#ifndef CONFIG_DM_PMIC
|
||||
#define CONFIG_POWER
|
||||
#define CONFIG_POWER_I2C
|
||||
#define CONFIG_POWER_PFUZE3000
|
||||
#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MXC_SPI
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_ATMEL
|
||||
#define CONFIG_SF_DEFAULT_BUS 0
|
||||
#define CONFIG_SF_DEFAULT_SPEED 20000000
|
||||
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
|
||||
#define CONFIG_SF_DEFAULT_CS 0
|
||||
#endif
|
||||
|
||||
#include "mx7d_arm2.h"
|
||||
|
||||
#endif
|
|
@ -0,0 +1,86 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration settings for the Freescale i.MX7D 19x19 LPDDR3 ARM2 board.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __MX7D_19X19_LPDDR3_ARM2_CONFIG_H
|
||||
#define __MX7D_19X19_LPDDR3_ARM2_CONFIG_H
|
||||
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 1
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
|
||||
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
|
||||
|
||||
#ifdef CONFIG_TARGET_MX7D_19X19_LPDDR2_ARM2
|
||||
#define PHYS_SDRAM_SIZE SZ_512M
|
||||
#else
|
||||
#define PHYS_SDRAM_SIZE SZ_2G
|
||||
#endif
|
||||
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#ifdef CONFIG_DM_ETH
|
||||
#define CONFIG_ETHPRIME "eth0"
|
||||
#else
|
||||
#define CONFIG_ETHPRIME "FEC"
|
||||
#endif
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0
|
||||
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_ATHEROS
|
||||
|
||||
/* ENET2 */
|
||||
#define IMX_FEC_BASE ENET2_IPS_BASE_ADDR
|
||||
|
||||
#define CONFIG_FEC_MXC_MDIO_BASE ENET_IPS_BASE_ADDR
|
||||
|
||||
/* QSPI conflict with EIMNOR */
|
||||
/* FEC0 conflict with EIMNOR */
|
||||
/* ECSPI conflict with UART */
|
||||
#ifdef CONFIG_QSPI_BOOT
|
||||
#define CONFIG_FSL_QSPI
|
||||
#elif defined CONFIG_SPI_BOOT
|
||||
#define CONFIG_MXC_SPI
|
||||
#elif defined CONFIG_NOR_BOOT
|
||||
#define CONFIG_MTD_NOR_FLASH
|
||||
#undef CONFIG_FEC_MXC
|
||||
#elif defined CONFIG_NAND_BOOT
|
||||
#define CONFIG_NAND_MXS
|
||||
#else
|
||||
#define CONFIG_MTD_NOR_FLASH
|
||||
#undef CONFIG_FEC_MXC
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_DM_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#endif
|
||||
#ifdef CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
#endif
|
||||
|
||||
/* PMIC */
|
||||
#ifndef CONFIG_DM_PMIC
|
||||
#define CONFIG_POWER
|
||||
#define CONFIG_POWER_I2C
|
||||
#define CONFIG_POWER_PFUZE3000
|
||||
#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MXC_SPI
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_ATMEL
|
||||
#define CONFIG_SF_DEFAULT_BUS 0
|
||||
#define CONFIG_SF_DEFAULT_SPEED 20000000
|
||||
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
|
||||
#define CONFIG_SF_DEFAULT_CS 0
|
||||
#endif
|
||||
|
||||
#include "mx7d_arm2.h"
|
||||
|
||||
#endif
|
Loading…
Reference in New Issue