x86: tsc: Remove legacy timer codes
Now that we have converted all x86 boards to use driver model timer, remove these legacy timer codes in the tsc driver. Note this also removes the TSC_CALIBRATION_BYPASS Kconfig option, as it is not needed with driver model. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>utp
Bin Meng
Simon Glass
parent
80af39842e
commit
1d4c83c248
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@ -279,26 +279,6 @@ config AP_STACK_SIZE
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the memory used by this initialisation process. Typically 4KB is
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enough space.
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config TSC_CALIBRATION_BYPASS
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bool "Bypass Time-Stamp Counter (TSC) calibration"
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default n
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help
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By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
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running frequency via Model-Specific Register (MSR) and Programmable
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Interval Timer (PIT). If the calibration does not work on your board,
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select this option and provide a hardcoded TSC running frequency with
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CONFIG_TSC_FREQ_IN_MHZ below.
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Normally this option should be turned on in a simulation environment
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like qemu.
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config TSC_FREQ_IN_MHZ
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int "Time-Stamp Counter (TSC) running frequency in MHz"
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depends on TSC_CALIBRATION_BYPASS
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default 1000
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help
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The running frequency in MHz of Time-Stamp Counter (TSC).
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config HAVE_VGA_BIOS
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bool "Add a VGA BIOS image"
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help
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@ -6,7 +6,6 @@
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config QEMU
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bool
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select TSC_CALIBRATION_BYPASS
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if QEMU
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@ -7,7 +7,6 @@
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config INTEL_QUARK
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bool
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select HAVE_RMU
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select TSC_CALIBRATION_BYPASS
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if INTEL_QUARK
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@ -119,8 +118,4 @@ config SYS_CAR_SIZE
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Space in bytes in eSRAM used as Cache-As-ARM (CAR).
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Note this size must not exceed eSRAM's total size.
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config TSC_FREQ_IN_MHZ
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int
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default 400
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endif
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@ -54,7 +54,6 @@ struct arch_global_data {
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uint8_t x86_mask;
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uint32_t x86_device;
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uint64_t tsc_base; /* Initial value returned by rdtsc() */
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uint32_t tsc_mhz; /* TSC frequency in MHz */
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void *new_fdt; /* Relocated FDT */
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uint32_t bist; /* Built-in self test value */
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enum pei_boot_mode_t pei_boot_mode;
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@ -280,63 +280,12 @@ success:
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return delta / 1000;
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}
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#ifndef CONFIG_TIMER
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void timer_set_base(u64 base)
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{
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gd->arch.tsc_base = base;
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}
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/*
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* Get the number of CPU time counter ticks since it was read first time after
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* restart. This yields a free running counter guaranteed to take almost 6
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* years to wrap around even at 100GHz clock rate.
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*/
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u64 notrace get_ticks(void)
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{
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u64 now_tick = rdtsc();
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/* We assume that 0 means the base hasn't been set yet */
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if (!gd->arch.tsc_base)
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panic("No tick base available");
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return now_tick - gd->arch.tsc_base;
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}
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#endif /* CONFIG_TIMER */
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/* Get the speed of the TSC timer in MHz */
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unsigned notrace long get_tbclk_mhz(void)
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{
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#ifdef CONFIG_TIMER
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return get_tbclk() / 1000000;
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#else
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unsigned long fast_calibrate;
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if (gd->arch.tsc_mhz)
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return gd->arch.tsc_mhz;
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#ifdef CONFIG_TSC_CALIBRATION_BYPASS
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fast_calibrate = CONFIG_TSC_FREQ_IN_MHZ;
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#else
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fast_calibrate = try_msr_calibrate_tsc();
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if (!fast_calibrate) {
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fast_calibrate = quick_pit_calibrate();
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if (!fast_calibrate)
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panic("TSC frequency is ZERO");
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}
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#endif
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gd->arch.tsc_mhz = fast_calibrate;
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return fast_calibrate;
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#endif
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}
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#ifndef CONFIG_TIMER
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unsigned long get_tbclk(void)
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{
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return get_tbclk_mhz() * 1000 * 1000;
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}
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#endif
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static ulong get_ms_timer(void)
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{
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return (get_ticks() * 1000) / get_tbclk();
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@ -386,7 +335,6 @@ int timer_init(void)
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return 0;
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}
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#ifdef CONFIG_TIMER
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static int tsc_timer_get_count(struct udevice *dev, u64 *count)
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{
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u64 now_tick = rdtsc();
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@ -439,4 +387,3 @@ U_BOOT_DRIVER(tsc_timer) = {
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.ops = &tsc_timer_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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#endif /* CONFIG_TIMER */
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@ -1,7 +1,6 @@
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CONFIG_X86=y
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CONFIG_VENDOR_COREBOOT=y
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CONFIG_TARGET_COREBOOT=y
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CONFIG_TSC_CALIBRATION_BYPASS=y
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_FLASH is not set
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# CONFIG_CMD_SETEXPR is not set
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@ -2,7 +2,6 @@ CONFIG_X86=y
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CONFIG_VENDOR_EFI=y
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CONFIG_DEFAULT_DEVICE_TREE="efi"
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CONFIG_TARGET_EFI=y
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CONFIG_TSC_CALIBRATION_BYPASS=y
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# CONFIG_CMD_BOOTM is not set
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CONFIG_CMD_GPIO=y
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# CONFIG_CMD_NET is not set
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