i2c: sh_i2c: Update to new CONFIG_SYS_I2C framework
This updates to new I2C framwwork on sh_i2c. And this also updates boards(kzm9g and ecovec) that using sh_i2c. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>utp
Nobuhiro Iwamatsu
Heiko Schocher
parent
63c4f17b2f
commit
2035d77d79
18
README
18
README
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@ -2040,6 +2040,24 @@ CBFS (Coreboot Filesystem) support
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- CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3
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- CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses
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- drivers/i2c/sh_i2c.c:
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- activate this driver with CONFIG_SYS_I2C_SH
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- This driver adds from 2 to 5 i2c buses
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- CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0
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- CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0
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- CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1
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- CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1
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- CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2
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- CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2
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- CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3
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- CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3
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- CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4
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- CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
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- CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5
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- CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5
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- CONFIF_SYS_I2C_SH_NUM_CONTROLLERS for nummber of i2c buses
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additional defines:
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CONFIG_SYS_NUM_I2C_BUSES
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@ -289,7 +289,6 @@ void adjust_core_voltage(void)
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{
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u8 data;
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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data = 0x35;
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i2c_set_bus_num(0);
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i2c_write(0x40, 3, 1, &data, 1);
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@ -57,8 +57,7 @@ int board_late_init(void)
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outl(inl(MSTPCR2) & ~0x10000000, MSTPCR2);
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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i2c_set_bus_num(CONFIG_SYS_I2C_MODULE); /* Use I2C 1 */
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i2c_set_bus_num(1); /* Use I2C 1 */
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/* Read MAC address */
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i2c_read(0x50, 0x10, 0, mac, 6);
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@ -18,7 +18,6 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
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obj-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o
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obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
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obj-$(CONFIG_U8500_I2C) += u8500_i2c.o
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obj-$(CONFIG_SH_I2C) += sh_i2c.o
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obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
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obj-$(CONFIG_SYS_I2C) += i2c_core.o
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obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
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@ -26,6 +25,7 @@ obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
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obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
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obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
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obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
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obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
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obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
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obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
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obj-$(CONFIG_ZYNQ_I2C) += zynq_i2c.o
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@ -6,6 +6,7 @@
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -22,8 +23,6 @@ struct sh_i2c {
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};
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#undef ureg
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static struct sh_i2c *base;
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/* ICCR */
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#define SH_I2C_ICCR_ICE (1 << 7)
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#define SH_I2C_ICCR_RACK (1 << 6)
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@ -43,202 +42,165 @@ static struct sh_i2c *base;
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#define SH_I2C_ICIC_ICCHB8 (1 << 6)
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#endif
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static const struct sh_i2c *i2c_dev[CONFIG_SYS_I2C_SH_NUM_CONTROLLERS] = {
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(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE0,
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#ifdef CONFIG_SYS_I2C_SH_BASE1
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(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE1,
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#endif
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#ifdef CONFIG_SYS_I2C_SH_BASE2
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(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE2,
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#endif
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#ifdef CONFIG_SYS_I2C_SH_BASE3
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(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE3,
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#endif
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#ifdef CONFIG_SYS_I2C_SH_BASE4
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(struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE4,
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#endif
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};
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static u16 iccl, icch;
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#define IRQ_WAIT 1000
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static void irq_dte(struct sh_i2c *base)
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static void sh_irq_dte(struct sh_i2c *dev)
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{
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int i;
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for (i = 0 ; i < IRQ_WAIT ; i++) {
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if (SH_IC_DTE & readb(&base->icsr))
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for (i = 0; i < IRQ_WAIT; i++) {
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if (SH_IC_DTE & readb(&dev->icsr))
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break;
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udelay(10);
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}
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}
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static int irq_dte_with_tack(struct sh_i2c *base)
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static int sh_irq_dte_with_tack(struct sh_i2c *dev)
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{
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int i;
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for (i = 0 ; i < IRQ_WAIT ; i++) {
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if (SH_IC_DTE & readb(&base->icsr))
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for (i = 0; i < IRQ_WAIT; i++) {
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if (SH_IC_DTE & readb(&dev->icsr))
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break;
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if (SH_IC_TACK & readb(&base->icsr))
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if (SH_IC_TACK & readb(&dev->icsr))
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return -1;
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udelay(10);
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}
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return 0;
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}
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static void irq_busy(struct sh_i2c *base)
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static void sh_irq_busy(struct sh_i2c *dev)
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{
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int i;
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for (i = 0 ; i < IRQ_WAIT ; i++) {
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if (!(SH_IC_BUSY & readb(&base->icsr)))
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for (i = 0; i < IRQ_WAIT; i++) {
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if (!(SH_IC_BUSY & readb(&dev->icsr)))
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break;
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udelay(10);
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}
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}
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static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop)
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static int sh_i2c_set_addr(struct sh_i2c *dev, u8 chip, u8 addr, int stop)
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{
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u8 icic = SH_IC_TACK;
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clrbits_8(&base->iccr, SH_I2C_ICCR_ICE);
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setbits_8(&base->iccr, SH_I2C_ICCR_ICE);
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debug("%s: chip: %x, addr: %x iccl: %x, icch %x\n",
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__func__, chip, addr, iccl, icch);
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clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
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setbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
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writeb(iccl & 0xff, &base->iccl);
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writeb(icch & 0xff, &base->icch);
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writeb(iccl & 0xff, &dev->iccl);
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writeb(icch & 0xff, &dev->icch);
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#ifdef CONFIG_SH_I2C_8BIT
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if (iccl > 0xff)
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icic |= SH_I2C_ICIC_ICCLB8;
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if (icch > 0xff)
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icic |= SH_I2C_ICIC_ICCHB8;
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#endif
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writeb(icic, &base->icic);
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writeb(icic, &dev->icic);
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writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr);
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irq_dte(base);
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writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
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sh_irq_dte(dev);
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clrbits_8(&base->icsr, SH_IC_TACK);
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writeb(id << 1, &base->icdr);
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if (irq_dte_with_tack(base) != 0)
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clrbits_8(&dev->icsr, SH_IC_TACK);
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writeb(chip << 1, &dev->icdr);
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if (sh_irq_dte_with_tack(dev) != 0)
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return -1;
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writeb(reg, &base->icdr);
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writeb(addr, &dev->icdr);
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if (stop)
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writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &base->iccr);
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writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &dev->iccr);
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if (irq_dte_with_tack(base) != 0)
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if (sh_irq_dte_with_tack(dev) != 0)
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return -1;
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return 0;
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}
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static void i2c_finish(struct sh_i2c *base)
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static void sh_i2c_finish(struct sh_i2c *dev)
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{
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writeb(0, &base->icsr);
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clrbits_8(&base->iccr, SH_I2C_ICCR_ICE);
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writeb(0, &dev->icsr);
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clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
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}
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static int i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val)
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static int
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sh_i2c_raw_write(struct sh_i2c *dev, u8 chip, uint addr, u8 val)
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{
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int ret = -1;
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if (i2c_set_addr(base, id, reg, 0) != 0)
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if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
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goto exit0;
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udelay(10);
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writeb(val, &base->icdr);
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if (irq_dte_with_tack(base) != 0)
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writeb(val, &dev->icdr);
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if (sh_irq_dte_with_tack(dev) != 0)
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goto exit0;
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writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &base->iccr);
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if (irq_dte_with_tack(base) != 0)
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writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &dev->iccr);
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if (sh_irq_dte_with_tack(dev) != 0)
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goto exit0;
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irq_busy(base);
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sh_irq_busy(dev);
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ret = 0;
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exit0:
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i2c_finish(base);
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sh_i2c_finish(dev);
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return ret;
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}
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static int i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
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static int sh_i2c_raw_read(struct sh_i2c *dev, u8 chip, u8 addr)
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{
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int ret = -1;
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#if defined(CONFIG_SH73A0)
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if (i2c_set_addr(base, id, reg, 0) != 0)
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if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
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goto exit0;
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#else
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if (i2c_set_addr(base, id, reg, 1) != 0)
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if (sh_i2c_set_addr(dev, chip, addr, 1) != 0)
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goto exit0;
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udelay(100);
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#endif
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writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr);
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irq_dte(base);
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writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
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sh_irq_dte(dev);
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writeb(id << 1 | 0x01, &base->icdr);
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if (irq_dte_with_tack(base) != 0)
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writeb(chip << 1 | 0x01, &dev->icdr);
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if (sh_irq_dte_with_tack(dev) != 0)
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goto exit0;
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writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &base->iccr);
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if (irq_dte_with_tack(base) != 0)
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writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &dev->iccr);
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if (sh_irq_dte_with_tack(dev) != 0)
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goto exit0;
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ret = readb(&base->icdr) & 0xff;
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ret = readb(&dev->icdr) & 0xff;
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writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &dev->iccr);
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readb(&dev->icdr); /* Dummy read */
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sh_irq_busy(dev);
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writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &base->iccr);
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readb(&base->icdr); /* Dummy read */
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irq_busy(base);
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exit0:
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i2c_finish(base);
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sh_i2c_finish(dev);
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return ret;
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}
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#ifdef CONFIG_I2C_MULTI_BUS
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static unsigned int current_bus;
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/**
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* i2c_set_bus_num - change active I2C bus
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* @bus: bus index, zero based
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* @returns: 0 on success, non-0 on failure
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*/
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int i2c_set_bus_num(unsigned int bus)
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{
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if ((bus < 0) || (bus >= CONFIG_SYS_MAX_I2C_BUS)) {
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printf("Bad bus: %d\n", bus);
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return -1;
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}
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switch (bus) {
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case 0:
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base = (void *)CONFIG_SH_I2C_BASE0;
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break;
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case 1:
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base = (void *)CONFIG_SH_I2C_BASE1;
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break;
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#ifdef CONFIG_SH_I2C_BASE2
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case 2:
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base = (void *)CONFIG_SH_I2C_BASE2;
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break;
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#endif
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#ifdef CONFIG_SH_I2C_BASE3
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case 3:
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base = (void *)CONFIG_SH_I2C_BASE3;
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break;
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#endif
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#ifdef CONFIG_SH_I2C_BASE4
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case 4:
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base = (void *)CONFIG_SH_I2C_BASE4;
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break;
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#endif
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default:
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return -1;
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}
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current_bus = bus;
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return 0;
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}
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/**
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* i2c_get_bus_num - returns index of active I2C bus
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*/
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unsigned int i2c_get_bus_num(void)
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{
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return current_bus;
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}
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#endif
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#define SH_I2C_ICCL_CALC(clk, date, t_low, t_high) \
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((clk / rate) * (t_low / t_low + t_high))
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#define SH_I2C_ICCH_CALC(clk, date, t_low, t_high) \
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((clk / rate) * (t_high / t_low + t_high))
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void i2c_init(int speed, int slaveaddr)
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static void
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sh_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
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{
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int num, denom, tmp;
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@ -246,11 +208,6 @@ void i2c_init(int speed, int slaveaddr)
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if (!(gd->flags & GD_FLG_RELOC))
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return;
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#ifdef CONFIG_I2C_MULTI_BUS
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current_bus = 0;
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#endif
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base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0;
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/*
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* Calculate the value for iccl. From the data sheet:
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* iccl = (p-clock / transfer-rate) * (L / (L + H))
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@ -272,67 +229,78 @@ void i2c_init(int speed, int slaveaddr)
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icch = (u16)((num/denom) + 1);
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else
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icch = (u16)(num/denom);
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debug("clock: %d, speed %d, iccl: %x, icch: %x\n",
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CONFIG_SH_I2C_CLOCK, speed, iccl, icch);
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}
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/*
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* i2c_read: - Read multiple bytes from an i2c device
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*
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* The higher level routines take into account that this function is only
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* called with len < page length of the device (see configuration file)
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*
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* @chip: address of the chip which is to be read
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* @addr: i2c data address within the chip
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* @alen: length of the i2c data address (1..2 bytes)
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* @buffer: where to write the data
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* @len: how much byte do we want to read
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* @return: 0 in case of success
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*/
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int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len)
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static int sh_i2c_read(struct i2c_adapter *adap, uint8_t chip,
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uint addr, int alen, u8 *data, int len)
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{
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int ret;
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int i = 0;
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for (i = 0 ; i < len ; i++) {
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ret = i2c_raw_read(base, chip, addr + i);
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int ret, i;
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struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
ret = sh_i2c_raw_read(dev, chip, addr + i);
|
||||
if (ret < 0)
|
||||
return -1;
|
||||
buffer[i] = ret & 0xff;
|
||||
|
||||
data[i] = ret & 0xff;
|
||||
debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sh_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
|
||||
int alen, u8 *data, int len)
|
||||
{
|
||||
struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
|
||||
int i;
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
|
||||
if (sh_i2c_raw_write(dev, chip, addr + i, data[i]) != 0)
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* i2c_write: - Write multiple bytes to an i2c device
|
||||
*
|
||||
* The higher level routines take into account that this function is only
|
||||
* called with len < page length of the device (see configuration file)
|
||||
*
|
||||
* @chip: address of the chip which is to be written
|
||||
* @addr: i2c data address within the chip
|
||||
* @alen: length of the i2c data address (1..2 bytes)
|
||||
* @buffer: where to find the data to be written
|
||||
* @len: how much byte do we want to read
|
||||
* @return: 0 in case of success
|
||||
*/
|
||||
int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len)
|
||||
static int
|
||||
sh_i2c_probe(struct i2c_adapter *adap, u8 dev)
|
||||
{
|
||||
int i = 0;
|
||||
for (i = 0; i < len ; i++)
|
||||
if (i2c_raw_write(base, chip, addr + i, buffer[i]) != 0)
|
||||
return -1;
|
||||
return sh_i2c_read(adap, dev, 0, 0, NULL, 0);
|
||||
}
|
||||
|
||||
static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap,
|
||||
unsigned int speed)
|
||||
{
|
||||
struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
|
||||
|
||||
sh_i2c_finish(dev);
|
||||
sh_i2c_init(adap, speed, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* i2c_probe: - Test if a chip answers for a given i2c address
|
||||
*
|
||||
* @chip: address of the chip which is searched for
|
||||
* @return: 0 if a chip was found, -1 otherwhise
|
||||
* Register RCAR i2c adapters
|
||||
*/
|
||||
int i2c_probe(u8 chip)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = i2c_set_addr(base, chip, 0, 1);
|
||||
i2c_finish(base);
|
||||
return ret;
|
||||
}
|
||||
U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
|
||||
sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0)
|
||||
#ifdef CONFIG_SYS_I2C_SH_BASE1
|
||||
U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
|
||||
sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1)
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_I2C_SH_BASE2
|
||||
U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
|
||||
sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2)
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_I2C_SH_BASE3
|
||||
U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
|
||||
sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3)
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_I2C_SH_BASE4
|
||||
U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
|
||||
sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4)
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -58,18 +58,17 @@
|
|||
|
||||
/* I2C */
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_SH_I2C 1
|
||||
#define CONFIG_HARD_I2C 1
|
||||
#define CONFIG_I2C_MULTI_BUS 1
|
||||
#define CONFIG_SYS_MAX_I2C_BUS 2
|
||||
#define CONFIG_SYS_I2C_MODULE 1
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_SH
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 2
|
||||
#define CONFIG_SYS_I2C_SH_BASE0 0xA4470000
|
||||
#define CONFIG_SYS_I2C_SH_SPEED0 100000
|
||||
#define CONFIG_SYS_I2C_SH_BASE1 0xA4750000
|
||||
#define CONFIG_SYS_I2C_SH_SPEED1 100000
|
||||
#define CONFIG_SH_I2C_DATA_HIGH 4
|
||||
#define CONFIG_SH_I2C_DATA_LOW 5
|
||||
#define CONFIG_SH_I2C_CLOCK 41666666
|
||||
#define CONFIG_SH_I2C_BASE0 0xA4470000
|
||||
#define CONFIG_SH_I2C_BASE1 0xA4750000
|
||||
|
||||
/* Ether */
|
||||
#define CONFIG_SH_ETHER 1
|
||||
|
|
|
|||
|
|
@ -139,21 +139,22 @@
|
|||
|
||||
/* I2C */
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_SH_I2C 1
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_SH
|
||||
#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5
|
||||
#define CONFIG_SYS_I2C_SH_BASE0 0xE6820000
|
||||
#define CONFIG_SYS_I2C_SH_SPEED0 100000
|
||||
#define CONFIG_SYS_I2C_SH_BASE1 0xE6822000
|
||||
#define CONFIG_SYS_I2C_SH_SPEED1 100000
|
||||
#define CONFIG_SYS_I2C_SH_BASE2 0xE6824000
|
||||
#define CONFIG_SYS_I2C_SH_SPEED2 100000
|
||||
#define CONFIG_SYS_I2C_SH_BASE3 0xE6826000
|
||||
#define CONFIG_SYS_I2C_SH_SPEED3 100000
|
||||
#define CONFIG_SYS_I2C_SH_BASE4 0xE6828000
|
||||
#define CONFIG_SYS_I2C_SH_SPEED4 100000
|
||||
#define CONFIG_SH_I2C_8BIT
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_I2C_MULTI_BUS
|
||||
#define CONFIG_SYS_MAX_I2C_BUS (5)
|
||||
#define CONFIG_SYS_I2C_MODULE
|
||||
#define CONFIG_SYS_I2C_SPEED (100000) /* 100 kHz */
|
||||
#define CONFIG_SYS_I2C_SLAVE (0x7F)
|
||||
#define CONFIG_SH_I2C_DATA_HIGH (4)
|
||||
#define CONFIG_SH_I2C_DATA_LOW (5)
|
||||
#define CONFIG_SH_I2C_CLOCK (104000000) /* 104 MHz */
|
||||
#define CONFIG_SH_I2C_BASE0 (0xE6820000)
|
||||
#define CONFIG_SH_I2C_BASE1 (0xE6822000)
|
||||
#define CONFIG_SH_I2C_BASE2 (0xE6824000)
|
||||
#define CONFIG_SH_I2C_BASE3 (0xE6826000)
|
||||
#define CONFIG_SH_I2C_BASE4 (0xE6828000)
|
||||
#define CONFIG_SH_I2C_DATA_HIGH 4
|
||||
#define CONFIG_SH_I2C_DATA_LOW 5
|
||||
#define CONFIG_SH_I2C_CLOCK 104000000 /* 104 MHz */
|
||||
|
||||
#endif /* __KZM9G_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue