86xx: Update Global Utilities structure
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
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@ -1289,22 +1289,35 @@ typedef struct ccsr_gur {
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uint powmgtcsr; /* 0xe0080 - Power management status and control register */
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char res8[12];
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uint mcpsumr; /* 0xe0090 - Machine check summary register */
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char res9[12];
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uint rstrscr; /* 0xe0094 - Reset request status and control register */
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char res9[8];
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uint pvr; /* 0xe00a0 - Processor version register */
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uint svr; /* 0xe00a4 - System version register */
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char res10a[1880];
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char res10a[8];
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uint rstcr; /* 0xe00b0 - Reset control register */
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#define MPC86xx_RSTCR_HRST_REQ 0x00000002
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char res10b[1868];
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uint clkdvdr; /* 0xe0800 - Clock Divide register */
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char res10b[1532];
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char res10c[796];
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uint ddr1clkdr; /* 0xe0b20 - DDRC1 Clock Disable register */
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char res10d[4];
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uint ddr2clkdr; /* 0xe0b28 - DDRC2 Clock Disable register */
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char res10e[724];
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uint clkocr; /* 0xe0e00 - Clock out select register */
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char res11[12];
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uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
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char res12[12];
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uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */
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int res13[57];
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uint lynxdcr1; /* 0xe0f08 - Lynx debug control register 1*/
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int res14[6];
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uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */
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char res15[216];
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char res13a[224];
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uint srds1cr0; /* 0xe0f04 - SerDes1 control register 0 */
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char res13b[4];
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uint srds1cr1; /* 0xe0f08 - SerDes1 control register 1 */
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char res14[24];
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uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */
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char res15a[24];
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uint srds2cr0; /* 0xe0f40 - SerDes2 control register 0 */
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uint srds2cr1; /* 0xe0f44 - SerDes2 control register 1 */
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char res16[184];
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} ccsr_gur_t;
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/*
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