dcd: fix reinitialization of DDR
Martin T. H. Sandsmark
parent
71c1effdad
commit
23f85ebd9b
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@ -95,7 +95,7 @@ DATA 4 MX6_IOM_GRP_DDRPKE 0x00000000 /* Disable pull/keeper */
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/* CLOCK:*/
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/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 */
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/* Don't bother setting it, 0x00000030 is the default value */
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/* DATA 4 MX6_IOM_DRAM_SDCLK0_P 0x00000030 */
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DATA 4 MX6_IOM_DRAM_SDCLK0_P 0x00000030
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/* Control:*/
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@ -148,6 +148,11 @@ DATA 4 MX6_IOM_DRAM_DQM1 0x00000030
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DATA 4 MX6_IOM_DRAM_DQM2 0x00000030
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DATA 4 MX6_IOM_DRAM_DQM3 0x00000030
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/* Step 5.5 */
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/* Disable periodic refresh to be able to run calibration */
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DATA 4 MX6_MMDC_P0_MDREF 0x00000000
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/* ============================================================================= */
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/* DDR Controller Registers */
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/* ============================================================================= */
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@ -163,10 +168,6 @@ DATA 4 MX6_IOM_DRAM_DQM3 0x00000030
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/* Data bus width 32 */
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/* ============================================================================= */
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/* DDR_PHY_P0_MPZQHWCTRL: enable both one-time & periodic HW ZQ calibration.*/
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/* change ZQ_HW_PER=256ms: Original - 0xa1390003*/
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DATA 4 MX6_MMDC_P0_MPZQHWCTRL 0xa1390023
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/* write leveling: based on Freescale board layout and T topology*/
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/* For target board: may need to run write leveling calibration*/
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/* to fine tune these settings*/
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@ -176,9 +177,7 @@ DATA 4 MX6_MMDC_P0_MPWLDECTRL0 0x002D0028
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DATA 4 MX6_MMDC_P0_MPWLDECTRL1 0x00280028
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/* ######################################################*/
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/* calibration values based on calibration compare of 0x00ffff00:*/
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/* Note: these calibration values are based on Freescale's board*/
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/* May need to run calibration on target board to fine tune these*/
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/* Calibration values from DDR stress tester tool */
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/* ######################################################*/
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/* MPDGCTRL0 PHY0*/
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@ -200,6 +199,8 @@ DATA 4 MX6_MMDC_P0_MPRDDLCTL 0x3E3E4446
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/* Write calibration */
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DATA 4 MX6_MMDC_P0_MPWRDLCTL 0x38343830
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/* Read data DQ byte 0-3 delay */
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/* DDR_PHY_P0_MPREDQBY0DL3*/
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/* DDR_PHY_P0_MPREDQBY1DL3*/
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/* DDR_PHY_P0_MPREDQBY2DL3*/
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@ -209,41 +210,36 @@ DATA 4 MX6_MMDC_P0_MPRDDQBY1DL 0x33333333
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DATA 4 MX6_MMDC_P0_MPRDDQBY2DL 0x33333333
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DATA 4 MX6_MMDC_P0_MPRDDQBY3DL 0x33333333
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/* MMDC termination */
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/* DDR_PHY_P0_MPODTCTRL*/
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/*DATA 4 MX6_MMDC_P0_MPODTCTRL 0x00011117*/
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DATA 4 MX6_MMDC_P0_MPODTCTRL 0x00022227
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/* Complete calibration by forced measurement:*/
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/* DDR_PHY_P0_MPMUR0: frc_msr*/
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DATA 4 MX6_MMDC_P0_MPMUR0 0x00000800
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/* MMDC0_MDPDC*/
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/* MMDC0_MDOTC*/
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/* MMDC0_MDCFG0*/
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/* MMDC0_MDCFG1*/
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/* MMDC0_MDCFG2*/
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/* MMDC0_MDMISC*/
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DATA 4 MX6_MMDC_P0_MDPDC 0x00020024
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DATA 4 MX6_MMDC_P0_MDOTC 0x00333040
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DATA 4 MX6_MMDC_P0_MDCFG0 0x3F435313
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DATA 4 MX6_MMDC_P0_MDCFG1 0xB68E8B63
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DATA 4 MX6_MMDC_P0_MDCFG2 0x01FF00DB
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DATA 4 MX6_MMDC_P0_MDMISC 0x00091740
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/* DATA 4 MX6_MMDC_P0_MDPDC 0x00020024 */
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/* =============================================================== */
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/* MMDC initialization sequence from 32.4.2 in the i.MX6SL manual */
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/* =============================================================== */
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/* MMDC0_MDCTL*/
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/* Step 1 */
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/* Set the Configuration request bit during MMDC set up*/
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DATA 4 MX6_MMDC_P0_MDSCR MX6_MMDC_MDSCR_CON_REQ
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/* Delay register; recommend to maintain the default values*/
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DATA 4 MX6_MMDC_P0_MDRWD 0x000026d2
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/* Out of reset delay register */
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/* CKE HIGH to a valid command: 0 cycles */
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/* Time from SDE enable to CKE rise: 1 cycle */
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/* In case that DDR reset# is low, will wait */
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/* until it's high and thenwait this period until */
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/* rising CKE. (JEDEC value is 500 us) */
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/* Time from SDE enable to DDR reset# high: 14 cycles */
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DATA 4 MX6_MMDC_P0_MDOR 0x00431023
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/* Step 2 */
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/* Timing configuration */
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DATA 4 MX6_MMDC_P0_MDCFG0 0x3F435313
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DATA 4 MX6_MMDC_P0_MDCFG1 0xB68E8B63
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DATA 4 MX6_MMDC_P0_MDCFG2 0x01FF00DB
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DATA 4 MX6_MMDC_P0_MDOTC 0x00333040
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/* CS0_END. Defines the absolute last address */
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/* associated with CS0 with increments of 256Mb. */
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/* CS0_END=AXI_ADDRESS[31:25] bits. */
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@ -254,26 +250,75 @@ DATA 4 MX6_MMDC_P0_MDOR 0x00431023
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DATA 4 MX6_MMDC_P0_MDASP 0x0000004F
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/*DATA 4 MX6_MMDC_P0_MDASP 0x0000004F*/
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/* Step 3 */
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/* Configure DDR type */
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DATA 4 MX6_MMDC_P0_MDMISC 0x00091742
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/* Step 4 */
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/* Out of reset delay register */
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/* CKE HIGH to a valid command: 0 cycles */
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/* Time from SDE enable to CKE rise: 1 cycle */
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/* In case that DDR reset# is low, will wait */
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/* until it's high and thenwait this period until */
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/* rising CKE. (JEDEC value is 500 us) */
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/* Time from SDE enable to DDR reset# high: 14 cycles */
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DATA 4 MX6_MMDC_P0_MDOR 0x00431023
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/* Step 5 */
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/* DDR physical parameters (density/burst length */
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/*DATA 4 MX6_MMDC_P0_MDCTL 0xC3190000*/
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/*DATA 4 MX6_MMDC_P0_MDCTL 0x83190000*/
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DATA 4 MX6_MMDC_P0_MDCTL 0x03190000
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/* Step 6 */
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/* DDR_PHY_P0_MPZQHWCTRL: enable one-time HW ZQ calibration.*/
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DATA 4 MX6_MMDC_P0_MPZQHWCTRL 0xa1390001
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/* Step 7 */
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/* Enable MMDC with correct chip select */
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DATA 4 MX6_MMDC_P0_MDCTL 0x83190000
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/* Mode register writes*/
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/* MMDC0_MDSCR: MR3 write: CS0*/
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/* MMDC0_MDSCR: MR1 write: CS0*/
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/* MMDC0_MDSCR: MR0 write: CS0*/
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/* Step 8 */
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/* Write mode registers to init ddr3 devices */
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/* MMDC0_MDSCR: MR2 write: Bank 0, CS0
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Load Mode Register Command
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DDR3, set correct CMD_CS, CMD_BA, CMD_ADDR_LSB, CMD_ADDR_MSB)*/
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DATA 4 MX6_MMDC_P0_MDSCR 0x02008032
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/*DATA 4 MX6_MMDC_P0_MDSCR 0x04008032*/
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/* MMDC0_MDSCR: MR3 write: CS0*/
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DATA 4 MX6_MMDC_P0_MDSCR 0x00008033
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/* MMDC0_MDSCR: MR1 write: CS0*/
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DATA 4 MX6_MMDC_P0_MDSCR 0x00048031
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/* MMDC0_MDSCR: MR0 write: CS0*/
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DATA 4 MX6_MMDC_P0_MDSCR 0x05208030
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/* MMDC0_MDSCR: ZQ calibration command sent to device on CS0 */
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DATA 4 MX6_MMDC_P0_MDSCR 0x04008040
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/* Step 10 */
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/* Power down control and self-refresh */
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/* MMDC0_MDPDC now SDCTL power down enabled*/
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DATA 4 MX6_MMDC_P0_MDPDC 0x00025524
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/* MMDC0_MAPSR ADOPT power down enabled*/
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DATA 4 MX6_MMDC_P0_MAPSR 0x00011006
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/* Step 11 */
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/* DDR_PHY_P0_MPZQHWCTRL: enable both one-time & periodic HW ZQ calibration.*/
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/* change ZQ_HW_PER=256ms: Original - 0xa1390003*/
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DATA 4 MX6_MMDC_P0_MPZQHWCTRL 0xa1390023
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/* Step 12 */
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/* Configure and activate periodic refresh */
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/* MMDC0_MDREF*/
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DATA 4 MX6_MMDC_P0_MDREF 0x00005800
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/* Step 13 */
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/* De-assert configuration request (CON_REQ) */
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DATA 4 MX6_MMDC_P0_MDSCR 0x00000000
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/* Delay register; recommend to maintain the default values*/
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/*DATA 4 MX6_MMDC_P0_MDRWD 0x000026d2*/
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/* Mode register writes*/
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/* MMDC0_MDSCR: MR2 write: CS1*/
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/* MMDC0_MDSCR: MR3 write: CS1*/
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/* MMDC0_MDSCR: MR1 write: CS1*/
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@ -287,19 +332,4 @@ DATA 4 MX6_MMDC_P0_MDSCR 0x04008040
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/* DATA 4 MX6_MMDC_P0_MDSCR 0x04008048 */
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/* MMDC0_MDREF*/
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/* DDR_PHY_P0_MPODTCTRL*/
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DATA 4 MX6_MMDC_P0_MDREF 0x00005800
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/*DATA 4 MX6_MMDC_P0_MPODTCTRL 0x00011117*/
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DATA 4 MX6_MMDC_P0_MPODTCTRL 0x00022227
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/* MMDC0_MDPDC now SDCTL power down enabled*/
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/* MMDC0_MAPSR ADOPT power down enabled*/
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/* MMDC0_MDSCR: clear this register (especially the configuration bit as initialization is complete*/
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DATA 4 MX6_MMDC_P0_MDPDC 0x00025564
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DATA 4 MX6_MMDC_P0_MAPSR 0x00011006
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DATA 4 MX6_MMDC_P0_MDSCR 0x00000000
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