musb-new: Add sunxi musb controller support
This is based on Jussi Kivilinna's work for the linux-sunxi-3.4 kernel to use the kernels musb driver instead of Allwinners own custom driver. Signed-off-by: Hans de Goede <hdegoede@redhat.com>utp
Hans de Goede
Marek Vasut
parent
0f8bc53240
commit
28a15ef7fd
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@ -8,6 +8,7 @@ obj-$(CONFIG_MUSB_HOST) += musb_host.o musb_core.o musb_uboot.o
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obj-$(CONFIG_USB_MUSB_DSPS) += musb_dsps.o
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obj-$(CONFIG_USB_MUSB_AM35X) += am35x.o
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obj-$(CONFIG_USB_MUSB_OMAP2PLUS) += omap2430.o
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obj-$(CONFIG_USB_MUSB_SUNXI) += sunxi.o
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ccflags-y := $(call cc-option,-Wno-unused-variable) \
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$(call cc-option,-Wno-unused-but-set-variable) \
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@ -0,0 +1,279 @@
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/*
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* Allwinner SUNXI "glue layer"
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*
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* Copyright © 2015 Hans de Goede <hdegoede@redhat.com>
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* Copyright © 2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
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*
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* Based on the sw_usb "Allwinner OTG Dual Role Controller" code.
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* Copyright 2007-2012 (C) Allwinner Technology Co., Ltd.
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* javen <javen@allwinnertech.com>
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*
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* Based on the DA8xx "glue layer" code.
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* Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
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* Copyright (C) 2005-2006 by Texas Instruments
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*
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* This file is part of the Inventra Controller Driver for Linux.
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*
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* The Inventra Controller Driver for Linux is free software; you
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* can redistribute it and/or modify it under the terms of the GNU
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* General Public License version 2 as published by the Free Software
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* Foundation.
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*
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/usbc.h>
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#include "linux-compat.h"
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#include "musb_core.h"
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/******************************************************************************
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******************************************************************************
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* From the Allwinner driver
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******************************************************************************
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******************************************************************************/
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/******************************************************************************
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* From include/sunxi_usb_bsp.h
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******************************************************************************/
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/* reg offsets */
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#define USBC_REG_o_ISCR 0x0400
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#define USBC_REG_o_PHYCTL 0x0404
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#define USBC_REG_o_PHYBIST 0x0408
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#define USBC_REG_o_PHYTUNE 0x040c
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#define USBC_REG_o_VEND0 0x0043
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/* Interface Status and Control */
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#define USBC_BP_ISCR_VBUS_VALID_FROM_DATA 30
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#define USBC_BP_ISCR_VBUS_VALID_FROM_VBUS 29
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#define USBC_BP_ISCR_EXT_ID_STATUS 28
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#define USBC_BP_ISCR_EXT_DM_STATUS 27
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#define USBC_BP_ISCR_EXT_DP_STATUS 26
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#define USBC_BP_ISCR_MERGED_VBUS_STATUS 25
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#define USBC_BP_ISCR_MERGED_ID_STATUS 24
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#define USBC_BP_ISCR_ID_PULLUP_EN 17
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#define USBC_BP_ISCR_DPDM_PULLUP_EN 16
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#define USBC_BP_ISCR_FORCE_ID 14
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#define USBC_BP_ISCR_FORCE_VBUS_VALID 12
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#define USBC_BP_ISCR_VBUS_VALID_SRC 10
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#define USBC_BP_ISCR_HOSC_EN 7
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#define USBC_BP_ISCR_VBUS_CHANGE_DETECT 6
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#define USBC_BP_ISCR_ID_CHANGE_DETECT 5
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#define USBC_BP_ISCR_DPDM_CHANGE_DETECT 4
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#define USBC_BP_ISCR_IRQ_ENABLE 3
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#define USBC_BP_ISCR_VBUS_CHANGE_DETECT_EN 2
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#define USBC_BP_ISCR_ID_CHANGE_DETECT_EN 1
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#define USBC_BP_ISCR_DPDM_CHANGE_DETECT_EN 0
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/******************************************************************************
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* From usbc/usbc.c
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******************************************************************************/
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static u32 USBC_WakeUp_ClearChangeDetect(u32 reg_val)
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{
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u32 temp = reg_val;
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temp &= ~(1 << USBC_BP_ISCR_VBUS_CHANGE_DETECT);
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temp &= ~(1 << USBC_BP_ISCR_ID_CHANGE_DETECT);
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temp &= ~(1 << USBC_BP_ISCR_DPDM_CHANGE_DETECT);
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return temp;
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}
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static void USBC_EnableIdPullUp(__iomem void *base)
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{
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u32 reg_val;
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reg_val = musb_readl(base, USBC_REG_o_ISCR);
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reg_val |= (1 << USBC_BP_ISCR_ID_PULLUP_EN);
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reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
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musb_writel(base, USBC_REG_o_ISCR, reg_val);
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}
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static void USBC_DisableIdPullUp(__iomem void *base)
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{
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u32 reg_val;
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reg_val = musb_readl(base, USBC_REG_o_ISCR);
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reg_val &= ~(1 << USBC_BP_ISCR_ID_PULLUP_EN);
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reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
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musb_writel(base, USBC_REG_o_ISCR, reg_val);
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}
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static void USBC_EnableDpDmPullUp(__iomem void *base)
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{
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u32 reg_val;
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reg_val = musb_readl(base, USBC_REG_o_ISCR);
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reg_val |= (1 << USBC_BP_ISCR_DPDM_PULLUP_EN);
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reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
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musb_writel(base, USBC_REG_o_ISCR, reg_val);
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}
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static void USBC_DisableDpDmPullUp(__iomem void *base)
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{
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u32 reg_val;
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reg_val = musb_readl(base, USBC_REG_o_ISCR);
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reg_val &= ~(1 << USBC_BP_ISCR_DPDM_PULLUP_EN);
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reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
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musb_writel(base, USBC_REG_o_ISCR, reg_val);
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}
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static void USBC_ForceIdToLow(__iomem void *base)
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{
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u32 reg_val;
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reg_val = musb_readl(base, USBC_REG_o_ISCR);
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reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID);
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reg_val |= (0x02 << USBC_BP_ISCR_FORCE_ID);
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reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
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musb_writel(base, USBC_REG_o_ISCR, reg_val);
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}
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static void USBC_ForceIdToHigh(__iomem void *base)
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{
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u32 reg_val;
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reg_val = musb_readl(base, USBC_REG_o_ISCR);
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reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_ID);
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reg_val |= (0x03 << USBC_BP_ISCR_FORCE_ID);
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reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
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musb_writel(base, USBC_REG_o_ISCR, reg_val);
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}
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static void USBC_ForceVbusValidDisable(__iomem void *base)
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{
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u32 reg_val;
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reg_val = musb_readl(base, USBC_REG_o_ISCR);
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reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
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reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
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musb_writel(base, USBC_REG_o_ISCR, reg_val);
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}
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static void USBC_ForceVbusValidToHigh(__iomem void *base)
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{
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u32 reg_val;
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reg_val = musb_readl(base, USBC_REG_o_ISCR);
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reg_val &= ~(0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
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reg_val |= (0x03 << USBC_BP_ISCR_FORCE_VBUS_VALID);
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reg_val = USBC_WakeUp_ClearChangeDetect(reg_val);
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musb_writel(base, USBC_REG_o_ISCR, reg_val);
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}
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static void USBC_ConfigFIFO_Base(void)
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{
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u32 reg_value;
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/* config usb fifo, 8kb mode */
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reg_value = readl(SUNXI_SRAMC_BASE + 0x04);
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reg_value &= ~(0x03 << 0);
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reg_value |= (1 << 0);
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writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
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}
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/******************************************************************************
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* MUSB Glue code
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******************************************************************************/
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static irqreturn_t sunxi_musb_interrupt(int irq, void *__hci)
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{
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struct musb *musb = __hci;
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irqreturn_t retval = IRQ_NONE;
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/* read and flush interrupts */
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musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
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if (musb->int_usb)
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musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
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musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
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if (musb->int_tx)
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musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
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musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
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if (musb->int_rx)
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musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
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if (musb->int_usb || musb->int_tx || musb->int_rx)
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retval |= musb_interrupt(musb);
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return retval;
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}
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static void sunxi_musb_enable(struct musb *musb)
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{
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pr_debug("%s():\n", __func__);
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/* select PIO mode */
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musb_writeb(musb->mregs, USBC_REG_o_VEND0, 0);
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if (is_host_enabled(musb)) {
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/* port power on */
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sunxi_usbc_vbus_enable(0);
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}
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}
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static void sunxi_musb_disable(struct musb *musb)
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{
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pr_debug("%s():\n", __func__);
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/* Put the controller back in a pristane state for "usb reset" */
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if (musb->is_active) {
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sunxi_usbc_disable(0);
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sunxi_usbc_enable(0);
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musb->is_active = 0;
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}
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}
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static int sunxi_musb_init(struct musb *musb)
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{
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int err;
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pr_debug("%s():\n", __func__);
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err = sunxi_usbc_request_resources(0);
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if (err)
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return err;
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musb->isr = sunxi_musb_interrupt;
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sunxi_usbc_enable(0);
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USBC_ConfigFIFO_Base();
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USBC_EnableDpDmPullUp(musb->mregs);
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USBC_EnableIdPullUp(musb->mregs);
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if (is_host_enabled(musb)) {
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/* Host mode */
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USBC_ForceIdToLow(musb->mregs);
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USBC_ForceVbusValidToHigh(musb->mregs);
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} else {
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/* Peripheral mode */
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USBC_ForceIdToHigh(musb->mregs);
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USBC_ForceVbusValidDisable(musb->mregs);
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}
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return 0;
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}
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static int sunxi_musb_exit(struct musb *musb)
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{
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pr_debug("%s():\n", __func__);
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USBC_DisableDpDmPullUp(musb->mregs);
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USBC_DisableIdPullUp(musb->mregs);
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sunxi_usbc_vbus_disable(0);
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sunxi_usbc_disable(0);
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return sunxi_usbc_free_resources(0);
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}
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const struct musb_platform_ops sunxi_musb_ops = {
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.init = sunxi_musb_init,
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.exit = sunxi_musb_exit,
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.enable = sunxi_musb_enable,
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.disable = sunxi_musb_disable,
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};
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@ -154,8 +154,8 @@ enum usb_init_type {
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defined(CONFIG_USB_OMAP3) || defined(CONFIG_USB_DA8XX) || \
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defined(CONFIG_USB_BLACKFIN) || defined(CONFIG_USB_AM35X) || \
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defined(CONFIG_USB_MUSB_DSPS) || defined(CONFIG_USB_MUSB_AM35X) || \
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defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined(CONFIG_USB_XHCI) || \
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defined(CONFIG_USB_DWC2)
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defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined(CONFIG_USB_MUSB_SUNXI) || \
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defined(CONFIG_USB_XHCI) || defined(CONFIG_USB_DWC2)
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int usb_lowlevel_init(int index, enum usb_init_type init, void **controller);
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int usb_lowlevel_stop(int index);
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