arm: Add support for LEGO MINDSTORMS EV3
This is based on the davinci da850evm. It can boot from either the on-board 16MB flash or from a microSD card. It also reads board information from an I2C EEPROM. The EV3 itself initally boots from write-protected EEPROM, so no u-boot SPL is needed. Signed-off-by: David Lechner <david@lechnology.com> Reviewed-by: Tom Rini <trini@konsulko.com>utp
David Lechner
Tom Rini
parent
6f6e9439e4
commit
2ac07f75d1
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@ -22,6 +22,9 @@ config TARGET_OMAPL138_LCDK
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config TARGET_CALIMAIN
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bool "Calimain board"
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config TARGET_LEGOEV3
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bool "LEGO MINDSTORMS EV3"
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endchoice
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config SYS_SOC
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@ -31,5 +34,6 @@ source "board/Barix/ipam390/Kconfig"
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source "board/davinci/da8xxevm/Kconfig"
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source "board/davinci/ea20/Kconfig"
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source "board/omicron/calimain/Kconfig"
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source "board/lego/ev3/Kconfig"
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endif
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@ -12,6 +12,16 @@
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#include <asm/arch/pinmux_defs.h>
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/* SPI pin muxer settings */
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const struct pinmux_config spi0_pins_base[] = {
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{ pinmux(3), 1, 0 }, /* SPI0_CLK */
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{ pinmux(3), 1, 2 }, /* SPI0_SOMI */
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{ pinmux(3), 1, 3 }, /* SPI0_SIMO */
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};
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const struct pinmux_config spi0_pins_scs0[] = {
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{ pinmux(4), 1, 1 }, /* SPI0_SCS[0] */
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};
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const struct pinmux_config spi1_pins_base[] = {
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{ pinmux(5), 1, 2 }, /* SPI1_CLK */
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{ pinmux(5), 1, 4 }, /* SPI1_SOMI */
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@ -503,6 +503,7 @@ struct davinci_syscfg_regs {
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#define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21)
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#define DAVINCI_SYSCFG_SUSPSRC_SPI1 (1 << 22)
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#define DAVINCI_SYSCFG_SUSPSRC_UART0 (1 << 18)
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#define DAVINCI_SYSCFG_SUSPSRC_UART1 (1 << 19)
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#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20)
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#define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27)
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@ -0,0 +1,12 @@
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if TARGET_LEGOEV3
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config SYS_BOARD
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default "ev3"
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config SYS_VENDOR
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default "lego"
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config SYS_CONFIG_NAME
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default "legoev3"
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endif
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@ -0,0 +1,6 @@
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LEGOEV3 BOARD
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M: David Lechner <david@lechnology.com>
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S: Maintained
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F: board/lego/ev3/
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F: include/configs/legoev3.h
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F: configs/legoev3_defconfig
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@ -0,0 +1,10 @@
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#
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# (C) Copyright 2000, 2001, 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += legoev3.o
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@ -0,0 +1,32 @@
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Summary
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=======
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LEGO MINDSTORMS EV3 is a toy robot produced by the LEGO Group. It is based
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on the davinci da850 evm. The EV3 has a 16MB spi flash and a SDHC microSD card
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reader.
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Booting
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=======
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The EV3 contains a bootloader in EEPROM that loads u-boot.bin from address 0x0
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of the spi flash memory. Using the default configuration, u-boot will check to
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see if there is a boot.scr file on the first FAT partition of the mmc. If there
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is, it will run the script and boot the kernel from the uImage file also in
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the FAT partition. Otherwise, it will load a kernel and rootfs from the flash.
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The kernel must be stored at address 0x50000 on the flash and have a maximum
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size of 3MiB. The rootfs must be a squasfs image and stored at 0x350000 in the
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flash and have a maximum size of 9.3MiB. The flash starting at 0xCB0000 is
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reserved for user data.
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Writing image to flash
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======================
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The EEPROM contains a program for uploading an image file to the flash memory.
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The program is started by holding down the right button on the EV3 when powering
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it on. You can also `run fwupdateboot` in the u-boot shell to reboot into this
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mode. The image can then be uploaded using the official LEGO MINDSTORMS EV3
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software or a 3rd party program capable of uploading a firmware file.
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If you are booting from the microSD card, it is enough to just write uboot.bin
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to the flash. If you are not using a microSD card, you will need to create an
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image file using the layout described above.
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@ -0,0 +1,176 @@
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/*
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* Copyright (C) 2016 David Lechner <david@lechnology.com>
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*
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* Based on da850evm.c
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*
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Based on da830evm.c. Original Copyrights follow:
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*
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* Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <net.h>
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#include <netdev.h>
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#include <spi.h>
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#include <spi_flash.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/pinmux_defs.h>
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#include <asm/io.h>
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#include <asm/arch/davinci_misc.h>
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#include <asm/errno.h>
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#include <hwconfig.h>
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#ifdef CONFIG_DAVINCI_MMC
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#include <mmc.h>
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#include <asm/arch/sdmmc_defs.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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u8 board_rev;
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#define EEPROM_I2C_ADDR 0x50
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#define EEPROM_REV_OFFSET 0x3F00
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#define EEPROM_MAC_OFFSET 0x3F06
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#ifdef CONFIG_DAVINCI_MMC
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static struct davinci_mmc mmc_sd0 = {
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.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
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.host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
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.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
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.version = MMC_CTLR_VERSION_2,
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};
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int board_mmc_init(bd_t *bis)
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{
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mmc_sd0.input_clk = clk_get(DAVINCI_MMCSD_CLKID);
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/* Add slot-0 to mmc subsystem */
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return davinci_mmc_init(bis, &mmc_sd0);
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}
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#endif
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const struct pinmux_resource pinmuxes[] = {
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PINMUX_ITEM(spi0_pins_base),
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PINMUX_ITEM(spi0_pins_scs0),
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PINMUX_ITEM(uart1_pins_txrx),
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PINMUX_ITEM(i2c0_pins),
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PINMUX_ITEM(mmc0_pins),
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};
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const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
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const struct lpsc_resource lpsc[] = {
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{ DAVINCI_LPSC_SPI0 }, /* Serial Flash */
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{ DAVINCI_LPSC_UART1 }, /* console */
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{ DAVINCI_LPSC_MMC_SD },
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};
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const int lpsc_size = ARRAY_SIZE(lpsc);
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u32 get_board_rev(void)
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{
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u8 buf[2];
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if (!board_rev) {
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if (i2c_read(EEPROM_I2C_ADDR, EEPROM_REV_OFFSET, 2, buf, 2)) {
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printf("\nBoard revision read failed!\n");
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} else {
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/*
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* Board rev 3 has MAC address at EEPROM_REV_OFFSET.
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* Other revisions have checksum at EEPROM_REV_OFFSET+1
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* to detect this.
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*/
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if ((buf[0] ^ buf[1]) == 0xFF)
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board_rev = buf[0];
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else
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board_rev = 3;
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}
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}
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return board_rev;
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}
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/*
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* The Bluetooth MAC address serves as the board serial number.
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*/
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void get_board_serial(struct tag_serialnr *serialnr)
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{
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u32 offset;
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u8 buf[6];
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if (!board_rev)
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board_rev = get_board_rev();
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/* Board rev 3 has MAC address where rev should be */
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offset = (board_rev == 3) ? EEPROM_REV_OFFSET : EEPROM_MAC_OFFSET;
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if (i2c_read(EEPROM_I2C_ADDR, offset, 2, buf, 6)) {
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printf("\nBoard serial read failed!\n");
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} else {
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u8 *nr;
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nr = (u8 *)&serialnr->low;
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nr[0] = buf[5];
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nr[1] = buf[4];
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nr[2] = buf[3];
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nr[3] = buf[2];
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nr = (u8 *)&serialnr->high;
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nr[0] = buf[1];
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nr[1] = buf[0];
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nr[2] = 0;
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nr[3] = 0;
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}
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}
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int board_early_init_f(void)
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{
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/*
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* Power on required peripherals
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* ARM does not have access by default to PSC0 and PSC1
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* assuming here that the DSP bootloader has set the IOPU
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* such that PSC access is available to ARM
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*/
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if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
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return 1;
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return 0;
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}
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int board_init(void)
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{
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#ifndef CONFIG_USE_IRQ
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irq_init();
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#endif
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/* arch number of the board */
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/* LEGO didn't register for a unique number and uses da850evm */
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gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
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/* address of boot parameters */
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gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
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/* setup the SUSPSRC for ARM to control emulation suspend */
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writel(readl(&davinci_syscfg_regs->suspsrc) &
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~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
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DAVINCI_SYSCFG_SUSPSRC_SPI0 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
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DAVINCI_SYSCFG_SUSPSRC_UART1),
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&davinci_syscfg_regs->suspsrc);
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/* configure pinmux settings */
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if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
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return 1;
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/* enable the console UART */
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writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
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DAVINCI_UART_PWREMU_MGMT_UTRST),
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&davinci_uart1_ctrl_regs->pwremu_mgmt);
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return 0;
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}
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@ -0,0 +1,12 @@
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CONFIG_ARM=y
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CONFIG_ARCH_DAVINCI=y
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CONFIG_TARGET_LEGOEV3=y
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CONFIG_AUTOBOOT_KEYED=y
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CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds - press 'l' to stop...\n"
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CONFIG_AUTOBOOT_STOP_STR="l"
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_FLASH is not set
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SYS_NS16550=y
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@ -0,0 +1,255 @@
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/*
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* Copyright (C) 2016 David Lechner <david@lechnology.com>
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*
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* Based on da850evm.h
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*
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Based on davinci_dvevm.h. Original Copyrights follow:
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*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* SoC Configuration
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*/
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#define CONFIG_MACH_DAVINCI_DA850_EVM
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#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
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#define CONFIG_SOC_DA850 /* TI DA850 SoC */
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#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
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#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
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#define CONFIG_SYS_OSCIN_FREQ 24000000
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#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
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#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
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#define CONFIG_SYS_DA850_PLL_INIT
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#define CONFIG_SYS_DA850_DDR_INIT
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#define CONFIG_SYS_TEXT_BASE 0xc1080000
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/*
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* Memory Info
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*/
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#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
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#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
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#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
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#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
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/* memtest start addr */
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#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
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/* memtest will be run on 16MB */
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#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
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DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
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DAVINCI_SYSCFG_SUSPSRC_SPI0 | \
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DAVINCI_SYSCFG_SUSPSRC_UART1 | \
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DAVINCI_SYSCFG_SUSPSRC_EMAC | \
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DAVINCI_SYSCFG_SUSPSRC_I2C)
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/*
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* PLL configuration
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*/
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#define CONFIG_SYS_DV_CLKMODE 0
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#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
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#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
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#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
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#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
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#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
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#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
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#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
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#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
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#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
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#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
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#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
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#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
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#define CONFIG_SYS_DA850_PLL0_PLLM 24
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#define CONFIG_SYS_DA850_PLL1_PLLM 21
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/*
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* DDR2 memory configuration
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*/
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#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
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DV_DDR_PHY_EXT_STRBEN | \
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(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
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#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
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(1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
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(1 << DV_DDR_SDCR_DDREN_SHIFT) | \
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(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
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(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
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(0x3 << DV_DDR_SDCR_CL_SHIFT) | \
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(0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
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(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
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/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
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#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
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#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
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(14 << DV_DDR_SDTMR1_RFC_SHIFT) | \
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(2 << DV_DDR_SDTMR1_RP_SHIFT) | \
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(2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
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(1 << DV_DDR_SDTMR1_WR_SHIFT) | \
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(5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
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(8 << DV_DDR_SDTMR1_RC_SHIFT) | \
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(1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
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(0 << DV_DDR_SDTMR1_WTR_SHIFT))
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#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
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(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
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(0 << DV_DDR_SDTMR2_XP_SHIFT) | \
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(0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
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(17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
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(199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
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(0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
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(0 << DV_DDR_SDTMR2_CKE_SHIFT))
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#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
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#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
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/*
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* Serial Driver info
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*/
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
|
||||
#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART1_BASE /* Base address of UART1 */
|
||||
#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
|
||||
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
|
||||
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
|
||||
|
||||
#define CONFIG_SPI
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_DAVINCI_SPI
|
||||
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI0_BASE
|
||||
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID)
|
||||
#define CONFIG_SF_DEFAULT_SPEED 50000000
|
||||
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
|
||||
|
||||
/*
|
||||
* I2C Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_DAVINCI
|
||||
#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
|
||||
|
||||
/*
|
||||
* U-Boot general configuration
|
||||
*/
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_BOOTFILE "uImage" /* Boot file name */
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
|
||||
#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
|
||||
#define CONFIG_VERSION_VARIABLE
|
||||
#define CONFIG_AUTO_COMPLETE
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_CRC32_VERIFY
|
||||
#define CONFIG_MX_CYCLIC
|
||||
#define CONFIG_OF_LIBFDT
|
||||
|
||||
/*
|
||||
* Linux Information
|
||||
*/
|
||||
#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
|
||||
#define CONFIG_HWCONFIG /* enable hwconfig */
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_REVISION_TAG
|
||||
#define CONFIG_SERIAL_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_SETUP_INITRD_TAG
|
||||
#define CONFIG_BOOTDELAY 0
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"if mmc rescan; then " \
|
||||
"if run loadbootscr; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcargs; " \
|
||||
"run mmcboot; " \
|
||||
"else " \
|
||||
"run flashargs; " \
|
||||
"run flashboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"run flashargs; " \
|
||||
"run flashboot; " \
|
||||
"fi"
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"hostname=EV3\0" \
|
||||
"memsize=64M\0" \
|
||||
"filesyssize=10M\0" \
|
||||
"verify=n\0" \
|
||||
"console=ttyS1,115200n8\0" \
|
||||
"bootscraddr=0xC0600000\0" \
|
||||
"loadaddr=0xC0007FC0\0" \
|
||||
"filesysaddr=0xC1180000\0" \
|
||||
"fwupdateboot=mw 0xFFFF1FFC 0x5555AAAA; reset\0" \
|
||||
"mmcargs=setenv bootargs mem=${memsize} console=${console} root=/dev/mmcblk0p2 rw rootwait lpj=747520\0" \
|
||||
"mmcboot=bootm ${loadaddr}\0" \
|
||||
"flashargs=setenv bootargs mem=${memsize} initrd=${filesysaddr},${filesyssize} root=/dev/ram0 rw rootfstype=squashfs console=${console} lpj=747520\0" \
|
||||
"flashboot=sf probe 0; sf read ${loadaddr} 0x50000 0x300000; sf read ${filesysaddr} 0x350000 0x960000; bootm ${loadaddr}\0" \
|
||||
"loadimage=fatload mmc 0 ${loadaddr} uImage\0" \
|
||||
"loadbootscr=fatload mmc 0 ${bootscraddr} boot.scr\0" \
|
||||
"bootscript=source ${bootscraddr}\0" \
|
||||
|
||||
/*
|
||||
* U-Boot commands
|
||||
*/
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_DIAG
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_SAVES
|
||||
|
||||
#ifdef CONFIG_CMD_BDI
|
||||
#define CONFIG_CLOCKS
|
||||
#endif
|
||||
|
||||
#define CONFIG_CMD_SPI
|
||||
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
#define CONFIG_ENV_SIZE (16 << 10)
|
||||
|
||||
/* SD/MMC configuration */
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_DAVINCI_MMC_SD1
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_DAVINCI_MMC
|
||||
|
||||
/*
|
||||
* Enable MMC commands only when
|
||||
* MMC support is present
|
||||
*/
|
||||
#ifdef CONFIG_MMC
|
||||
#define CONFIG_DOS_PARTITION
|
||||
#define CONFIG_CMD_EXT3
|
||||
#define CONFIG_CMD_EXT4
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_MMC
|
||||
#endif
|
||||
|
||||
/* additions for new relocation code, must added to all boards */
|
||||
#define CONFIG_SYS_SDRAM_BASE 0xc0000000
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR 0x80010000
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue