Program EPLD to force full duplex mode for PHY.
EPLD forces modes of PHY operation. By default full duplex is turned off. This fix turns it on. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
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636538c520
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2db6478406
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@ -39,8 +39,6 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
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************************************************************************/
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************************************************************************/
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int board_early_init_f(void)
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int board_early_init_f(void)
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{
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{
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volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
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mtebc( pb0ap, 0x03800000 ); /* set chip selects */
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mtebc( pb0ap, 0x03800000 ); /* set chip selects */
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mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
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mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
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mtebc( pb1ap, 0x03800000 );
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mtebc( pb1ap, 0x03800000 );
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@ -66,8 +64,6 @@ int board_early_init_f(void)
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mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */
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mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */
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mtdcr( uic0sr, 0xffffffff );
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mtdcr( uic0sr, 0xffffffff );
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x->ethuart &= ~EPLD2_RESET_ETH_N; /* put Ethernet+PHY in reset */
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return 0;
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return 0;
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}
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}
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@ -79,7 +75,18 @@ int board_early_init_f(void)
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int misc_init_r(void)
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int misc_init_r(void)
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{
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{
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volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
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volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
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x->ethuart |= EPLD2_RESET_ETH_N; /* take Ethernet+PHY out of reset */
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/* set modes of operation */
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x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 |
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EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE;
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/* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */
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x->ethuart &= ~EPLD2_ETH_AUTO_NEGO;
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/* put Ethernet+PHY in reset */
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x->ethuart &= ~EPLD2_RESET_ETH_N;
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udelay(10000);
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/* take Ethernet+PHY out of reset */
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x->ethuart |= EPLD2_RESET_ETH_N;
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return 0;
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return 0;
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}
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}
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@ -138,7 +138,8 @@
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#define BI_PHYMODE_MII 7
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#define BI_PHYMODE_MII 7
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#endif
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#endif
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#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || \
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defined(CONFIG_440GRX) || defined(CONFIG_440SP)
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#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
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#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
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#endif
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#endif
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@ -408,7 +409,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
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int ethgroup = -1;
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int ethgroup = -1;
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#endif
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#endif
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#endif
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#endif
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_440SPE) || defined(CONFIG_440SP)
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unsigned long mfr;
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unsigned long mfr;
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#endif
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#endif
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@ -500,7 +502,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
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__asm__ volatile ("eieio");
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__asm__ volatile ("eieio");
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/* reset emac so we have access to the phy */
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/* reset emac so we have access to the phy */
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#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_440SP)
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/* provide clocks for EMAC internal loopback */
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/* provide clocks for EMAC internal loopback */
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mfsdr (sdr_mfr, mfr);
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mfsdr (sdr_mfr, mfr);
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mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
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mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
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@ -518,7 +521,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
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if (failsafe <= 0)
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if (failsafe <= 0)
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printf("\nProblem resetting EMAC!\n");
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printf("\nProblem resetting EMAC!\n");
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#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_440SP)
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/* remove clocks for EMAC internal loopback */
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/* remove clocks for EMAC internal loopback */
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mfsdr (sdr_mfr, mfr);
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mfsdr (sdr_mfr, mfr);
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mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
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mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
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