tegra: Move display controller header into common
Allow this to be used by other Tegra SoCs. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>utp
Simon Glass
Tom Warren
parent
96e82a253a
commit
2eb70de6b1
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@ -234,7 +234,7 @@ struct dc_disp_reg {
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uint cursor_pos_ns; /* _DISP_CURSOR_POSITION_NS_0 */
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uint seq_ctrl; /* _DISP_INIT_SEQ_CONTROL_0 */
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/* Address 0x442 ~ 0x446 */
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/* Address 0x443 ~ 0x446 */
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uint spi_init_seq_data_a; /* _DISP_SPI_INIT_SEQ_DATA_A_0 */
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uint spi_init_seq_data_b; /* _DISP_SPI_INIT_SEQ_DATA_B_0 */
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uint spi_init_seq_data_c; /* _DISP_SPI_INIT_SEQ_DATA_C_0 */
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@ -254,6 +254,11 @@ struct dc_disp_reg {
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/* Address 0x4c0 ~ 0x4c1 */
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uint dac_crt_ctrl; /* _DISP_DAC_CRT_CTRL_0 */
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uint disp_misc_ctrl; /* _DISP_DISP_MISC_CONTROL_0 */
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u32 rsvd_4c2[34]; /* 4c2 - 4e3 */
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/* Address 0x4e4 */
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u32 blend_background_color; /* _DISP_BLEND_BACKGROUND_COLOR_0 */
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};
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enum dc_winc_filter_p {
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@ -289,9 +294,9 @@ struct dc_winc_reg {
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uint v_filter_p[WINC_FILTER_COUNT];
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};
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/* WIN A/B/C Register 0x700 ~ 0x714*/
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/* WIN A/B/C Register 0x700 ~ 0x719*/
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struct dc_win_reg {
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/* Address 0x700 ~ 0x714 */
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/* Address 0x700 ~ 0x719 */
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uint win_opt; /* _WIN_WIN_OPTIONS_0 */
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uint byte_swap; /* _WIN_BYTE_SWAP_0 */
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uint buffer_ctrl; /* _WIN_BUFFER_CONTROL_0 */
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@ -313,11 +318,16 @@ struct dc_win_reg {
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uint blend_2win_y; /* _WIN_BLEND_2WIN_Y_0 */
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uint blend_3win_xy; /* _WIN_BLEND_3WIN_XY_0 */
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uint hp_fetch_ctrl; /* _WIN_HP_FETCH_CONTROL_0 */
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uint global_alpha; /* _WIN_GLOBAL_ALPHA */
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uint blend_layer_ctrl; /* _WINBUF_BLEND_LAYER_CONTROL_0 */
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uint blend_match_select; /* _WINBUF_BLEND_MATCH_SELECT_0 */
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uint blend_nomatch_select; /* _WINBUF_BLEND_NOMATCH_SELECT_0 */
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uint blend_alpha_1bit; /* _WINBUF_BLEND_ALPHA_1BIT_0 */
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};
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/* WINBUF A/B/C Register 0x800 ~ 0x80a */
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/* WINBUF A/B/C Register 0x800 ~ 0x80d */
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struct dc_winbuf_reg {
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/* Address 0x800 ~ 0x80a */
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/* Address 0x800 ~ 0x80d */
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uint start_addr; /* _WINBUF_START_ADDR_0 */
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uint start_addr_ns; /* _WINBUF_START_ADDR_NS_0 */
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uint start_addr_u; /* _WINBUF_START_ADDR_U_0 */
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@ -329,6 +339,9 @@ struct dc_winbuf_reg {
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uint addr_v_offset; /* _WINBUF_ADDR_V_OFFSET_0 */
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uint addr_v_offset_ns; /* _WINBUF_ADDR_V_OFFSET_NS_0 */
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uint uflow_status; /* _WINBUF_UFLOW_STATUS_0 */
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uint buffer_surface_kind; /* DC_WIN_BUFFER_SURFACE_KIND */
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uint rsvd_80c;
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uint start_addr_hi; /* DC_WINBUF_START_ADDR_HI_0 */
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};
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/* Display Controller (DC_) regs */
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@ -339,16 +352,16 @@ struct dc_ctlr {
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struct dc_com_reg com; /* COM register 0x300 ~ 0x329 */
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uint reserved1[0xd6];
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struct dc_disp_reg disp; /* DISP register 0x400 ~ 0x4c1 */
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uint reserved2[0x3e];
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struct dc_disp_reg disp; /* DISP register 0x400 ~ 0x4e4 */
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uint reserved2[0x1b];
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struct dc_winc_reg winc; /* Window A/B/C 0x500 ~ 0x628 */
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uint reserved3[0xd7];
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struct dc_win_reg win; /* WIN A/B/C 0x700 ~ 0x714*/
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uint reserved4[0xeb];
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struct dc_win_reg win; /* WIN A/B/C 0x700 ~ 0x719*/
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uint reserved4[0xe6];
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struct dc_winbuf_reg winbuf; /* WINBUF A/B/C 0x800 ~ 0x80a */
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struct dc_winbuf_reg winbuf; /* WINBUF A/B/C 0x800 ~ 0x80d */
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};
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#define BIT(pos) (1U << pos)
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@ -399,20 +412,45 @@ enum win_color_depth_id {
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#define SPI_ENABLE BIT(24)
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#define HSPI_ENABLE BIT(25)
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/* DC_CMD_STATE_ACCESS 0x040 */
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#define READ_MUX_ASSEMBLY (0 << 0)
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#define READ_MUX_ACTIVE (1 << 0)
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#define WRITE_MUX_ASSEMBLY (0 << 2)
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#define WRITE_MUX_ACTIVE (1 << 2)
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/* DC_CMD_STATE_CONTROL 0x041 */
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#define GENERAL_ACT_REQ BIT(0)
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#define WIN_A_ACT_REQ BIT(1)
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#define WIN_B_ACT_REQ BIT(2)
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#define WIN_C_ACT_REQ BIT(3)
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#define WIN_D_ACT_REQ BIT(4)
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#define WIN_H_ACT_REQ BIT(5)
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#define CURSOR_ACT_REQ BIT(7)
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#define GENERAL_UPDATE BIT(8)
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#define WIN_A_UPDATE BIT(9)
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#define WIN_B_UPDATE BIT(10)
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#define WIN_C_UPDATE BIT(11)
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#define WIN_D_UPDATE BIT(12)
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#define WIN_H_UPDATE BIT(13)
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#define CURSOR_UPDATE BIT(15)
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#define NC_HOST_TRIG BIT(24)
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/* DC_CMD_DISPLAY_WINDOW_HEADER 0x042 */
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#define WINDOW_A_SELECT BIT(4)
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#define WINDOW_B_SELECT BIT(5)
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#define WINDOW_C_SELECT BIT(6)
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#define WINDOW_D_SELECT BIT(7)
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#define WINDOW_H_SELECT BIT(8)
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/* DC_DISP_DISP_WIN_OPTIONS 0x402 */
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#define CURSOR_ENABLE BIT(16)
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#define SOR_ENABLE BIT(25)
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#define TVO_ENABLE BIT(28)
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#define DSI_ENABLE BIT(29)
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#define HDMI_ENABLE BIT(30)
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/* DC_DISP_DISP_TIMING_OPTIONS 0x405 */
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#define VSYNC_H_POSITION(x) ((x) & 0xfff)
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/* DC_DISP_DISP_CLOCK_CONTROL 0x42e */
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#define SHIFT_CLK_DIVIDER_SHIFT 0
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@ -526,4 +564,9 @@ enum {
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#define V_DDA_INC_SHIFT 16
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#define V_DDA_INC_MASK (0xFFFF << V_DDA_INC_SHIFT)
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struct display_timing;
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int display_init(void *lcdbase, int fb_bits_per_pixel,
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struct display_timing *timing);
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#endif /* __ASM_ARCH_TEGRA_DC_H */
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@ -8,7 +8,7 @@
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#ifndef __ASM_ARCH_TEGRA_DISPLAY_H
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#define __ASM_ARCH_TEGRA_DISPLAY_H
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#include <asm/arch/dc.h>
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#include <asm/arch-tegra/dc.h>
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#include <fdtdec.h>
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#include <asm/gpio.h>
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@ -10,7 +10,7 @@
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#include <asm/arch/clock.h>
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#include <asm/arch/tegra.h>
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#include <asm/arch/display.h>
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#include <asm/arch/dc.h>
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#include <asm/arch-tegra/dc.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <asm/arch-tegra/timer.h>
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