x86: Add basic support for broadwell
This adds the broadwell architecture, with the CPU driver and some useful header files. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>utp
Simon Glass
Bin Meng
parent
c13dcb3dc7
commit
2f3f477b77
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@ -34,6 +34,7 @@ source "board/intel/Kconfig"
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# platform-specific options below
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source "arch/x86/cpu/baytrail/Kconfig"
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source "arch/x86/cpu/broadwell/Kconfig"
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source "arch/x86/cpu/coreboot/Kconfig"
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source "arch/x86/cpu/ivybridge/Kconfig"
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source "arch/x86/cpu/qemu/Kconfig"
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@ -20,6 +20,7 @@ extra-y += call32.o
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obj-y += intel_common/
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obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
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obj-$(CONFIG_INTEL_BROADWELL) += broadwell/
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obj-$(CONFIG_SYS_COREBOOT) += coreboot/
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obj-$(CONFIG_EFI_APP) += efi/
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obj-$(CONFIG_QEMU) += qemu/
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@ -0,0 +1,30 @@
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#
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# Copyright (C) 2016 Google Inc.
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#
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# SPDX-License-Identifier: GPL-2.0
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config INTEL_BROADWELL
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bool
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select CACHE_MRC_BIN
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if INTEL_BROADWELL
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config DCACHE_RAM_BASE
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default 0xff7c0000
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config DCACHE_RAM_SIZE
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default 0x40000
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config DCACHE_RAM_MRC_VAR_SIZE
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default 0x30000
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select SMM_TSEG
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select X86_RAMTEST
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config SMM_TSEG_SIZE
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hex
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default 0x800000
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endif
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@ -0,0 +1,7 @@
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#
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# Copyright (c) 2016 Google, Inc
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += cpu.o
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@ -0,0 +1,761 @@
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/*
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* Copyright (c) 2016 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0
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*
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* Based on code from coreboot src/soc/intel/broadwell/cpu.c
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*/
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#include <common.h>
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#include <dm.h>
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#include <cpu.h>
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#include <asm/cpu.h>
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#include <asm/cpu_x86.h>
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#include <asm/cpu_common.h>
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#include <asm/intel_regs.h>
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#include <asm/msr.h>
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#include <asm/post.h>
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#include <asm/turbo.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/pch.h>
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#include <asm/arch/rcb.h>
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struct cpu_broadwell_priv {
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bool ht_disabled;
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};
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/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
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static const u8 power_limit_time_sec_to_msr[] = {
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[0] = 0x00,
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[1] = 0x0a,
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[2] = 0x0b,
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[3] = 0x4b,
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[4] = 0x0c,
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[5] = 0x2c,
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[6] = 0x4c,
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[7] = 0x6c,
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[8] = 0x0d,
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[10] = 0x2d,
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[12] = 0x4d,
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[14] = 0x6d,
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[16] = 0x0e,
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[20] = 0x2e,
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[24] = 0x4e,
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[28] = 0x6e,
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[32] = 0x0f,
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[40] = 0x2f,
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[48] = 0x4f,
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[56] = 0x6f,
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[64] = 0x10,
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[80] = 0x30,
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[96] = 0x50,
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[112] = 0x70,
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[128] = 0x11,
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};
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/* Convert POWER_LIMIT_1_TIME MSR value to seconds */
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static const u8 power_limit_time_msr_to_sec[] = {
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[0x00] = 0,
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[0x0a] = 1,
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[0x0b] = 2,
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[0x4b] = 3,
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[0x0c] = 4,
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[0x2c] = 5,
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[0x4c] = 6,
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[0x6c] = 7,
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[0x0d] = 8,
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[0x2d] = 10,
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[0x4d] = 12,
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[0x6d] = 14,
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[0x0e] = 16,
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[0x2e] = 20,
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[0x4e] = 24,
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[0x6e] = 28,
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[0x0f] = 32,
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[0x2f] = 40,
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[0x4f] = 48,
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[0x6f] = 56,
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[0x10] = 64,
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[0x30] = 80,
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[0x50] = 96,
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[0x70] = 112,
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[0x11] = 128,
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};
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int arch_cpu_init_dm(void)
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{
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struct udevice *dev;
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int ret;
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/* Start up the LPC so we have serial */
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ret = uclass_first_device(UCLASS_LPC, &dev);
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if (ret)
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return ret;
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if (!dev)
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return -ENODEV;
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ret = cpu_set_flex_ratio_to_tdp_nominal();
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if (ret)
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return ret;
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return 0;
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}
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void set_max_freq(void)
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{
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msr_t msr, perf_ctl, platform_info;
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/* Check for configurable TDP option */
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platform_info = msr_read(MSR_PLATFORM_INFO);
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if ((platform_info.hi >> 1) & 3) {
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/* Set to nominal TDP ratio */
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msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
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perf_ctl.lo = (msr.lo & 0xff) << 8;
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} else {
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/* Platform Info bits 15:8 give max ratio */
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msr = msr_read(MSR_PLATFORM_INFO);
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perf_ctl.lo = msr.lo & 0xff00;
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}
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perf_ctl.hi = 0;
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msr_write(IA32_PERF_CTL, perf_ctl);
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debug("CPU: frequency set to %d MHz\n",
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((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK);
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}
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int arch_cpu_init(void)
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{
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post_code(POST_CPU_INIT);
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return x86_cpu_init_f();
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}
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int print_cpuinfo(void)
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{
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char processor_name[CPU_MAX_NAME_LEN];
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const char *name;
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int ret;
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set_max_freq();
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ret = cpu_common_init();
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if (ret)
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return ret;
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gd->arch.pei_boot_mode = PEI_BOOT_NONE;
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/* Print processor name */
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name = cpu_get_name(processor_name);
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printf("CPU: %s\n", name);
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return 0;
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}
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/*
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* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
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* the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly
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* when a core is woken up
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*/
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static int pcode_ready(void)
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{
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int wait_count;
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const int delay_step = 10;
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wait_count = 0;
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do {
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if (!(readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) &
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MAILBOX_RUN_BUSY))
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return 0;
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wait_count += delay_step;
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udelay(delay_step);
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} while (wait_count < 1000);
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return -ETIMEDOUT;
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}
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static u32 pcode_mailbox_read(u32 command)
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{
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int ret;
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ret = pcode_ready();
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if (ret) {
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debug("PCODE: mailbox timeout on wait ready\n");
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return ret;
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}
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/* Send command and start transaction */
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writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
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ret = pcode_ready();
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if (ret) {
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debug("PCODE: mailbox timeout on completion\n");
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return ret;
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}
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/* Read mailbox */
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return readl(MCHBAR_REG(BIOS_MAILBOX_DATA));
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}
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static int pcode_mailbox_write(u32 command, u32 data)
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{
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int ret;
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ret = pcode_ready();
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if (ret) {
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debug("PCODE: mailbox timeout on wait ready\n");
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return ret;
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}
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writel(data, MCHBAR_REG(BIOS_MAILBOX_DATA));
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/* Send command and start transaction */
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writel(command | MAILBOX_RUN_BUSY, MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
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ret = pcode_ready();
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if (ret) {
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debug("PCODE: mailbox timeout on completion\n");
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return ret;
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}
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return 0;
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}
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/* @dev is the CPU device */
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static void initialize_vr_config(struct udevice *dev)
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{
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int ramp, min_vid;
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msr_t msr;
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debug("Initializing VR config\n");
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/* Configure VR_CURRENT_CONFIG */
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msr = msr_read(MSR_VR_CURRENT_CONFIG);
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/*
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* Preserve bits 63 and 62. Bit 62 is PSI4 enable, but it is only valid
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* on ULT systems
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*/
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msr.hi &= 0xc0000000;
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msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A */
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msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A */
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msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A */
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msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */
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/* Leave the max instantaneous current limit (12:0) to default */
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msr_write(MSR_VR_CURRENT_CONFIG, msr);
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/* Configure VR_MISC_CONFIG MSR */
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msr = msr_read(MSR_VR_MISC_CONFIG);
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/* Set the IOUT_SLOPE scalar applied to dIout in U10.1.9 format */
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msr.hi &= ~(0x3ff << (40 - 32));
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msr.hi |= (0x200 << (40 - 32)); /* 1.0 */
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/* Set IOUT_OFFSET to 0 */
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msr.hi &= ~0xff;
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/* Set entry ramp rate to slow */
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msr.hi &= ~(1 << (51 - 32));
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/* Enable decay mode on C-state entry */
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msr.hi |= (1 << (52 - 32));
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/* Set the slow ramp rate */
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msr.hi &= ~(0x3 << (53 - 32));
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/* Configure the C-state exit ramp rate */
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ramp = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "intel,slow-ramp",
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-1);
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if (ramp != -1) {
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/* Configured slow ramp rate */
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msr.hi |= ((ramp & 0x3) << (53 - 32));
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/* Set exit ramp rate to slow */
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msr.hi &= ~(1 << (50 - 32));
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} else {
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/* Fast ramp rate / 4 */
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msr.hi |= (0x01 << (53 - 32));
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/* Set exit ramp rate to fast */
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msr.hi |= (1 << (50 - 32));
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}
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/* Set MIN_VID (31:24) to allow CPU to have full control */
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msr.lo &= ~0xff000000;
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min_vid = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "intel,min-vid",
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0);
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msr.lo |= (min_vid & 0xff) << 24;
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msr_write(MSR_VR_MISC_CONFIG, msr);
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/* Configure VR_MISC_CONFIG2 MSR */
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msr = msr_read(MSR_VR_MISC_CONFIG2);
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msr.lo &= ~0xffff;
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/*
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* Allow CPU to control minimum voltage completely (15:8) and
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* set the fast ramp voltage in 10mV steps
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*/
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if (cpu_get_family_model() == BROADWELL_FAMILY_ULT)
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msr.lo |= 0x006a; /* 1.56V */
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else
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msr.lo |= 0x006f; /* 1.60V */
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msr_write(MSR_VR_MISC_CONFIG2, msr);
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/* Set C9/C10 VCC Min */
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pcode_mailbox_write(MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE, 0x1f1f);
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}
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static int calibrate_24mhz_bclk(void)
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{
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int err_code;
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int ret;
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ret = pcode_ready();
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if (ret)
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return ret;
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/* A non-zero value initiates the PCODE calibration */
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writel(~0, MCHBAR_REG(BIOS_MAILBOX_DATA));
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writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL,
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MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
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ret = pcode_ready();
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if (ret)
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return ret;
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err_code = readl(MCHBAR_REG(BIOS_MAILBOX_INTERFACE)) & 0xff;
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debug("PCODE: 24MHz BLCK calibration response: %d\n", err_code);
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/* Read the calibrated value */
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writel(MAILBOX_RUN_BUSY | MAILBOX_BIOS_CMD_READ_CALIBRATION,
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MCHBAR_REG(BIOS_MAILBOX_INTERFACE));
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ret = pcode_ready();
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if (ret)
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return ret;
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debug("PCODE: 24MHz BLCK calibration value: 0x%08x\n",
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readl(MCHBAR_REG(BIOS_MAILBOX_DATA)));
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return 0;
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}
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static void configure_pch_power_sharing(void)
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{
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u32 pch_power, pch_power_ext, pmsync, pmsync2;
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int i;
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/* Read PCH Power levels from PCODE */
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pch_power = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER);
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pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT);
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debug("PCH Power: PCODE Levels 0x%08x 0x%08x\n", pch_power,
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pch_power_ext);
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pmsync = readl(RCB_REG(PMSYNC_CONFIG));
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pmsync2 = readl(RCB_REG(PMSYNC_CONFIG2));
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/*
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* Program PMSYNC_TPR_CONFIG PCH power limit values
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* pmsync[0:4] = mailbox[0:5]
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* pmsync[8:12] = mailbox[6:11]
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* pmsync[16:20] = mailbox[12:17]
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*/
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for (i = 0; i < 3; i++) {
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u32 level = pch_power & 0x3f;
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pch_power >>= 6;
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pmsync &= ~(0x1f << (i * 8));
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pmsync |= (level & 0x1f) << (i * 8);
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}
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writel(pmsync, RCB_REG(PMSYNC_CONFIG));
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/*
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* Program PMSYNC_TPR_CONFIG2 Extended PCH power limit values
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* pmsync2[0:4] = mailbox[23:18]
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* pmsync2[8:12] = mailbox_ext[6:11]
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* pmsync2[16:20] = mailbox_ext[12:17]
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* pmsync2[24:28] = mailbox_ext[18:22]
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*/
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pmsync2 &= ~0x1f;
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pmsync2 |= pch_power & 0x1f;
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for (i = 1; i < 4; i++) {
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u32 level = pch_power_ext & 0x3f;
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pch_power_ext >>= 6;
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pmsync2 &= ~(0x1f << (i * 8));
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pmsync2 |= (level & 0x1f) << (i * 8);
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}
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writel(pmsync2, RCB_REG(PMSYNC_CONFIG2));
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}
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static int bsp_init_before_ap_bringup(struct udevice *dev)
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{
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int ret;
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initialize_vr_config(dev);
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ret = calibrate_24mhz_bclk();
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if (ret)
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return ret;
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configure_pch_power_sharing();
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return 0;
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}
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int cpu_config_tdp_levels(void)
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{
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msr_t platform_info;
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/* Bits 34:33 indicate how many levels supported */
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platform_info = msr_read(MSR_PLATFORM_INFO);
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return (platform_info.hi >> 1) & 3;
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}
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static void set_max_ratio(void)
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{
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msr_t msr, perf_ctl;
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perf_ctl.hi = 0;
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/* Check for configurable TDP option */
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if (turbo_get_state() == TURBO_ENABLED) {
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msr = msr_read(MSR_NHM_TURBO_RATIO_LIMIT);
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perf_ctl.lo = (msr.lo & 0xff) << 8;
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} else if (cpu_config_tdp_levels()) {
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/* Set to nominal TDP ratio */
|
||||
msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
|
||||
perf_ctl.lo = (msr.lo & 0xff) << 8;
|
||||
} else {
|
||||
/* Platform Info bits 15:8 give max ratio */
|
||||
msr = msr_read(MSR_PLATFORM_INFO);
|
||||
perf_ctl.lo = msr.lo & 0xff00;
|
||||
}
|
||||
msr_write(IA32_PERF_CTL, perf_ctl);
|
||||
|
||||
debug("cpu: frequency set to %d\n",
|
||||
((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK);
|
||||
}
|
||||
|
||||
int broadwell_init(struct udevice *dev)
|
||||
{
|
||||
struct cpu_broadwell_priv *priv = dev_get_priv(dev);
|
||||
int num_threads;
|
||||
int num_cores;
|
||||
msr_t msr;
|
||||
int ret;
|
||||
|
||||
msr = msr_read(CORE_THREAD_COUNT_MSR);
|
||||
num_threads = (msr.lo >> 0) & 0xffff;
|
||||
num_cores = (msr.lo >> 16) & 0xffff;
|
||||
debug("CPU has %u cores, %u threads enabled\n", num_cores,
|
||||
num_threads);
|
||||
|
||||
priv->ht_disabled = num_threads == num_cores;
|
||||
|
||||
ret = bsp_init_before_ap_bringup(dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
set_max_ratio();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void configure_mca(void)
|
||||
{
|
||||
msr_t msr;
|
||||
const unsigned int mcg_cap_msr = 0x179;
|
||||
int i;
|
||||
int num_banks;
|
||||
|
||||
msr = msr_read(mcg_cap_msr);
|
||||
num_banks = msr.lo & 0xff;
|
||||
msr.lo = 0;
|
||||
msr.hi = 0;
|
||||
/*
|
||||
* TODO(adurbin): This should only be done on a cold boot. Also, some
|
||||
* of these banks are core vs package scope. For now every CPU clears
|
||||
* every bank
|
||||
*/
|
||||
for (i = 0; i < num_banks; i++)
|
||||
msr_write(MSR_IA32_MC0_STATUS + (i * 4), msr);
|
||||
}
|
||||
|
||||
static void enable_lapic_tpr(void)
|
||||
{
|
||||
msr_t msr;
|
||||
|
||||
msr = msr_read(MSR_PIC_MSG_CONTROL);
|
||||
msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
|
||||
msr_write(MSR_PIC_MSG_CONTROL, msr);
|
||||
}
|
||||
|
||||
|
||||
static void configure_c_states(void)
|
||||
{
|
||||
msr_t msr;
|
||||
|
||||
msr = msr_read(MSR_PMG_CST_CONFIG_CONTROL);
|
||||
msr.lo |= (1 << 31); /* Timed MWAIT Enable */
|
||||
msr.lo |= (1 << 30); /* Package c-state Undemotion Enable */
|
||||
msr.lo |= (1 << 29); /* Package c-state Demotion Enable */
|
||||
msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */
|
||||
msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */
|
||||
msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */
|
||||
msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */
|
||||
msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */
|
||||
/* The deepest package c-state defaults to factory-configured value */
|
||||
msr_write(MSR_PMG_CST_CONFIG_CONTROL, msr);
|
||||
|
||||
msr = msr_read(MSR_MISC_PWR_MGMT);
|
||||
msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */
|
||||
msr_write(MSR_MISC_PWR_MGMT, msr);
|
||||
|
||||
msr = msr_read(MSR_POWER_CTL);
|
||||
msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */
|
||||
msr.lo |= (1 << 1); /* C1E Enable */
|
||||
msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */
|
||||
msr_write(MSR_POWER_CTL, msr);
|
||||
|
||||
/* C-state Interrupt Response Latency Control 0 - package C3 latency */
|
||||
msr.hi = 0;
|
||||
msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT;
|
||||
msr_write(MSR_C_STATE_LATENCY_CONTROL_0, msr);
|
||||
|
||||
/* C-state Interrupt Response Latency Control 1 */
|
||||
msr.hi = 0;
|
||||
msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;
|
||||
msr_write(MSR_C_STATE_LATENCY_CONTROL_1, msr);
|
||||
|
||||
/* C-state Interrupt Response Latency Control 2 - package C6/C7 short */
|
||||
msr.hi = 0;
|
||||
msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;
|
||||
msr_write(MSR_C_STATE_LATENCY_CONTROL_2, msr);
|
||||
|
||||
/* C-state Interrupt Response Latency Control 3 - package C8 */
|
||||
msr.hi = 0;
|
||||
msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT;
|
||||
msr_write(MSR_C_STATE_LATENCY_CONTROL_3, msr);
|
||||
|
||||
/* C-state Interrupt Response Latency Control 4 - package C9 */
|
||||
msr.hi = 0;
|
||||
msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT;
|
||||
msr_write(MSR_C_STATE_LATENCY_CONTROL_4, msr);
|
||||
|
||||
/* C-state Interrupt Response Latency Control 5 - package C10 */
|
||||
msr.hi = 0;
|
||||
msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT;
|
||||
msr_write(MSR_C_STATE_LATENCY_CONTROL_5, msr);
|
||||
}
|
||||
|
||||
static void configure_misc(void)
|
||||
{
|
||||
msr_t msr;
|
||||
|
||||
msr = msr_read(MSR_IA32_MISC_ENABLE);
|
||||
msr.lo |= (1 << 0); /* Fast String enable */
|
||||
msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
|
||||
msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
|
||||
msr_write(MSR_IA32_MISC_ENABLE, msr);
|
||||
|
||||
/* Disable thermal interrupts */
|
||||
msr.lo = 0;
|
||||
msr.hi = 0;
|
||||
msr_write(MSR_IA32_THERM_INTERRUPT, msr);
|
||||
|
||||
/* Enable package critical interrupt only */
|
||||
msr.lo = 1 << 4;
|
||||
msr.hi = 0;
|
||||
msr_write(MSR_IA32_PACKAGE_THERM_INTERRUPT, msr);
|
||||
}
|
||||
|
||||
static void configure_thermal_target(struct udevice *dev)
|
||||
{
|
||||
int tcc_offset;
|
||||
msr_t msr;
|
||||
|
||||
tcc_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
|
||||
"intel,tcc-offset", 0);
|
||||
|
||||
/* Set TCC activaiton offset if supported */
|
||||
msr = msr_read(MSR_PLATFORM_INFO);
|
||||
if ((msr.lo & (1 << 30)) && tcc_offset) {
|
||||
msr = msr_read(MSR_TEMPERATURE_TARGET);
|
||||
msr.lo &= ~(0xf << 24); /* Bits 27:24 */
|
||||
msr.lo |= (tcc_offset & 0xf) << 24;
|
||||
msr_write(MSR_TEMPERATURE_TARGET, msr);
|
||||
}
|
||||
}
|
||||
|
||||
static void configure_dca_cap(void)
|
||||
{
|
||||
struct cpuid_result cpuid_regs;
|
||||
msr_t msr;
|
||||
|
||||
/* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
|
||||
cpuid_regs = cpuid(1);
|
||||
if (cpuid_regs.ecx & (1 << 18)) {
|
||||
msr = msr_read(MSR_IA32_PLATFORM_DCA_CAP);
|
||||
msr.lo |= 1;
|
||||
msr_write(MSR_IA32_PLATFORM_DCA_CAP, msr);
|
||||
}
|
||||
}
|
||||
|
||||
static void set_energy_perf_bias(u8 policy)
|
||||
{
|
||||
msr_t msr;
|
||||
int ecx;
|
||||
|
||||
/* Determine if energy efficient policy is supported */
|
||||
ecx = cpuid_ecx(0x6);
|
||||
if (!(ecx & (1 << 3)))
|
||||
return;
|
||||
|
||||
/* Energy Policy is bits 3:0 */
|
||||
msr = msr_read(MSR_IA32_ENERGY_PERFORMANCE_BIAS);
|
||||
msr.lo &= ~0xf;
|
||||
msr.lo |= policy & 0xf;
|
||||
msr_write(MSR_IA32_ENERGY_PERFORMANCE_BIAS, msr);
|
||||
|
||||
debug("cpu: energy policy set to %u\n", policy);
|
||||
}
|
||||
|
||||
/* All CPUs including BSP will run the following function */
|
||||
static void cpu_core_init(struct udevice *dev)
|
||||
{
|
||||
/* Clear out pending MCEs */
|
||||
configure_mca();
|
||||
|
||||
/* Enable the local cpu apics */
|
||||
enable_lapic_tpr();
|
||||
|
||||
/* Configure C States */
|
||||
configure_c_states();
|
||||
|
||||
/* Configure Enhanced SpeedStep and Thermal Sensors */
|
||||
configure_misc();
|
||||
|
||||
/* Thermal throttle activation offset */
|
||||
configure_thermal_target(dev);
|
||||
|
||||
/* Enable Direct Cache Access */
|
||||
configure_dca_cap();
|
||||
|
||||
/* Set energy policy */
|
||||
set_energy_perf_bias(ENERGY_POLICY_NORMAL);
|
||||
|
||||
/* Enable Turbo */
|
||||
turbo_enable();
|
||||
}
|
||||
|
||||
/*
|
||||
* Configure processor power limits if possible
|
||||
* This must be done AFTER set of BIOS_RESET_CPL
|
||||
*/
|
||||
void cpu_set_power_limits(int power_limit_1_time)
|
||||
{
|
||||
msr_t msr;
|
||||
msr_t limit;
|
||||
unsigned power_unit;
|
||||
unsigned tdp, min_power, max_power, max_time;
|
||||
u8 power_limit_1_val;
|
||||
|
||||
msr = msr_read(MSR_PLATFORM_INFO);
|
||||
if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
|
||||
power_limit_1_time = 28;
|
||||
|
||||
if (!(msr.lo & PLATFORM_INFO_SET_TDP))
|
||||
return;
|
||||
|
||||
/* Get units */
|
||||
msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
|
||||
power_unit = 2 << ((msr.lo & 0xf) - 1);
|
||||
|
||||
/* Get power defaults for this SKU */
|
||||
msr = msr_read(MSR_PKG_POWER_SKU);
|
||||
tdp = msr.lo & 0x7fff;
|
||||
min_power = (msr.lo >> 16) & 0x7fff;
|
||||
max_power = msr.hi & 0x7fff;
|
||||
max_time = (msr.hi >> 16) & 0x7f;
|
||||
|
||||
debug("CPU TDP: %u Watts\n", tdp / power_unit);
|
||||
|
||||
if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
|
||||
power_limit_1_time = power_limit_time_msr_to_sec[max_time];
|
||||
|
||||
if (min_power > 0 && tdp < min_power)
|
||||
tdp = min_power;
|
||||
|
||||
if (max_power > 0 && tdp > max_power)
|
||||
tdp = max_power;
|
||||
|
||||
power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
|
||||
|
||||
/* Set long term power limit to TDP */
|
||||
limit.lo = 0;
|
||||
limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
|
||||
limit.lo |= PKG_POWER_LIMIT_EN;
|
||||
limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
|
||||
PKG_POWER_LIMIT_TIME_SHIFT;
|
||||
|
||||
/* Set short term power limit to 1.25 * TDP */
|
||||
limit.hi = 0;
|
||||
limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
|
||||
limit.hi |= PKG_POWER_LIMIT_EN;
|
||||
/* Power limit 2 time is only programmable on server SKU */
|
||||
|
||||
msr_write(MSR_PKG_POWER_LIMIT, limit);
|
||||
|
||||
/* Set power limit values in MCHBAR as well */
|
||||
writel(limit.lo, MCHBAR_REG(MCH_PKG_POWER_LIMIT_LO));
|
||||
writel(limit.hi, MCHBAR_REG(MCH_PKG_POWER_LIMIT_HI));
|
||||
|
||||
/* Set DDR RAPL power limit by copying from MMIO to MSR */
|
||||
msr.lo = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_LO));
|
||||
msr.hi = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_HI));
|
||||
msr_write(MSR_DDR_RAPL_LIMIT, msr);
|
||||
|
||||
/* Use nominal TDP values for CPUs with configurable TDP */
|
||||
if (cpu_config_tdp_levels()) {
|
||||
msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
|
||||
limit.hi = 0;
|
||||
limit.lo = msr.lo & 0xff;
|
||||
msr_write(MSR_TURBO_ACTIVATION_RATIO, limit);
|
||||
}
|
||||
}
|
||||
|
||||
static int broadwell_get_info(struct udevice *dev, struct cpu_info *info)
|
||||
{
|
||||
msr_t msr;
|
||||
|
||||
msr = msr_read(IA32_PERF_CTL);
|
||||
info->cpu_freq = ((msr.lo >> 8) & 0xff) * BROADWELL_BCLK * 1000000;
|
||||
info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
|
||||
1 << CPU_FEAT_UCODE | 1 << CPU_FEAT_DEVICE_ID;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int broadwell_get_count(struct udevice *dev)
|
||||
{
|
||||
return 4;
|
||||
}
|
||||
|
||||
static int cpu_x86_broadwell_probe(struct udevice *dev)
|
||||
{
|
||||
if (dev->seq == 0) {
|
||||
cpu_core_init(dev);
|
||||
return broadwell_init(dev);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct cpu_ops cpu_x86_broadwell_ops = {
|
||||
.get_desc = cpu_x86_get_desc,
|
||||
.get_info = broadwell_get_info,
|
||||
.get_count = broadwell_get_count,
|
||||
};
|
||||
|
||||
static const struct udevice_id cpu_x86_broadwell_ids[] = {
|
||||
{ .compatible = "intel,core-i3-gen5" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(cpu_x86_broadwell_drv) = {
|
||||
.name = "cpu_x86_broadwell",
|
||||
.id = UCLASS_CPU,
|
||||
.of_match = cpu_x86_broadwell_ids,
|
||||
.bind = cpu_x86_bind,
|
||||
.probe = cpu_x86_broadwell_probe,
|
||||
.ops = &cpu_x86_broadwell_ops,
|
||||
.priv_auto_alloc_size = sizeof(struct cpu_broadwell_priv),
|
||||
};
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Google, Inc
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef __asm_arch_cpu_h
|
||||
#define __asm_arch_cpu_h
|
||||
|
||||
/* CPU types */
|
||||
#define HASWELL_FAMILY_ULT 0x40650
|
||||
#define BROADWELL_FAMILY_ULT 0x306d0
|
||||
|
||||
/* Supported CPUIDs */
|
||||
#define CPUID_HASWELL_A0 0x306c1
|
||||
#define CPUID_HASWELL_B0 0x306c2
|
||||
#define CPUID_HASWELL_C0 0x306c3
|
||||
#define CPUID_HASWELL_ULT_B0 0x40650
|
||||
#define CPUID_HASWELL_ULT 0x40651
|
||||
#define CPUID_HASWELL_HALO 0x40661
|
||||
#define CPUID_BROADWELL_C0 0x306d2
|
||||
#define CPUID_BROADWELL_D0 0x306d3
|
||||
#define CPUID_BROADWELL_E0 0x306d4
|
||||
|
||||
/* Broadwell bus clock is fixed at 100MHz */
|
||||
#define BROADWELL_BCLK 100
|
||||
|
||||
#define BROADWELL_FAMILY_ULT 0x306d0
|
||||
|
||||
#define CORE_THREAD_COUNT_MSR 0x35
|
||||
|
||||
#define MSR_VR_CURRENT_CONFIG 0x601
|
||||
#define MSR_VR_MISC_CONFIG 0x603
|
||||
#define MSR_PKG_POWER_SKU 0x614
|
||||
#define MSR_DDR_RAPL_LIMIT 0x618
|
||||
#define MSR_VR_MISC_CONFIG2 0x636
|
||||
|
||||
/* Latency times in units of 1024ns. */
|
||||
#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42
|
||||
#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73
|
||||
#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91
|
||||
#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4
|
||||
#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145
|
||||
#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef
|
||||
|
||||
void cpu_set_power_limits(int power_limit_1_time);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* From Coreboot soc/intel/broadwell/include/soc/iomap.h
|
||||
*
|
||||
* Copyright (C) 2016 Google Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __asm_arch_iomap_h
|
||||
#define __asm_arch_iomap_h
|
||||
|
||||
#define MCFG_BASE_ADDRESS 0xf0000000
|
||||
#define MCFG_BASE_SIZE 0x4000000
|
||||
|
||||
#define HPET_BASE_ADDRESS 0xfed00000
|
||||
|
||||
#define MCH_BASE_ADDRESS 0xfed10000
|
||||
#define MCH_BASE_SIZE 0x8000
|
||||
|
||||
#define DMI_BASE_ADDRESS 0xfed18000
|
||||
#define DMI_BASE_SIZE 0x1000
|
||||
|
||||
#define EP_BASE_ADDRESS 0xfed19000
|
||||
#define EP_BASE_SIZE 0x1000
|
||||
|
||||
#define EDRAM_BASE_ADDRESS 0xfed80000
|
||||
#define EDRAM_BASE_SIZE 0x4000
|
||||
|
||||
#define GDXC_BASE_ADDRESS 0xfed84000
|
||||
#define GDXC_BASE_SIZE 0x1000
|
||||
|
||||
#define RCBA_BASE_ADDRESS 0xfed1c000
|
||||
#define RCBA_BASE_SIZE 0x4000
|
||||
|
||||
#define HPET_BASE_ADDRESS 0xfed00000
|
||||
|
||||
#define ACPI_BASE_ADDRESS 0x1000
|
||||
#define ACPI_BASE_SIZE 0x100
|
||||
|
||||
#define GPIO_BASE_ADDRESS 0x1400
|
||||
#define GPIO_BASE_SIZE 0x400
|
||||
|
||||
#define SMBUS_BASE_ADDRESS 0x0400
|
||||
#define SMBUS_BASE_SIZE 0x10
|
||||
|
||||
/* Temporary addresses used before relocation */
|
||||
#define EARLY_GTT_BAR 0xe0000000
|
||||
#define EARLY_XHCI_BAR 0xd7000000
|
||||
#define EARLY_EHCI_BAR 0xd8000000
|
||||
#define EARLY_UART_BAR 0x3f8
|
||||
#define EARLY_TEMP_MMIO 0xfed08000
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,200 @@
|
|||
/*
|
||||
* From coreboot soc/intel/broadwell/include/soc/me.h
|
||||
*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef _asm_arch_me_h
|
||||
#define _asm_arch_me_h
|
||||
|
||||
#include <asm/me_common.h>
|
||||
|
||||
#define ME_INIT_STATUS_SUCCESS_OTHER 3 /* SEE ME9 BWG */
|
||||
|
||||
#define ME_HSIO_MESSAGE (7 << 28)
|
||||
#define ME_HSIO_CMD_GETHSIOVER 1
|
||||
#define ME_HSIO_CMD_CLOSE 0
|
||||
|
||||
/*
|
||||
* Apparently the GMES register is renamed to HFS2 (or HFSTS2 according
|
||||
* to ME9 BWG). Sadly the PCH EDS and the ME BWG do not match on nomenclature.
|
||||
*/
|
||||
#define PCI_ME_HFS2 0x48
|
||||
/* Infrastructure Progress Values */
|
||||
#define ME_HFS2_PHASE_ROM 0
|
||||
#define ME_HFS2_PHASE_BUP 1
|
||||
#define ME_HFS2_PHASE_UKERNEL 2
|
||||
#define ME_HFS2_PHASE_POLICY 3
|
||||
#define ME_HFS2_PHASE_MODULE_LOAD 4
|
||||
#define ME_HFS2_PHASE_UNKNOWN 5
|
||||
#define ME_HFS2_PHASE_HOST_COMM 6
|
||||
/* Current State - Based on Infra Progress values. */
|
||||
/* ROM State */
|
||||
#define ME_HFS2_STATE_ROM_BEGIN 0
|
||||
#define ME_HFS2_STATE_ROM_DISABLE 6
|
||||
/* BUP State */
|
||||
#define ME_HFS2_STATE_BUP_INIT 0
|
||||
#define ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1
|
||||
#define ME_HFS2_STATE_BUP_FLOW_DET 4
|
||||
#define ME_HFS2_STATE_BUP_VSCC_ERR 8
|
||||
#define ME_HFS2_STATE_BUP_CHECK_STRAP 0xa
|
||||
#define ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb
|
||||
#define ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd
|
||||
#define ME_HFS2_STATE_BUP_M3 0x11
|
||||
#define ME_HFS2_STATE_BUP_M0 0x12
|
||||
#define ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13
|
||||
#define ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15
|
||||
#define ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING 0x17
|
||||
#define ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18
|
||||
#define ME_HFS2_STATE_BUP_T32_MISSING 0x1c
|
||||
#define ME_HFS2_STATE_BUP_WAIT_DID 0x1f
|
||||
#define ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20
|
||||
#define ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21
|
||||
#define ME_HFS2_STATE_BUP_ENABLE_UMA 0x22
|
||||
#define ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23
|
||||
#define ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24
|
||||
#define ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25
|
||||
#define ME_HFS2_STATE_BUP_M0_CLK 0x26
|
||||
#define ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27
|
||||
#define ME_HFS2_STATE_BUP_TEMP_DIS 0x28
|
||||
#define ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32
|
||||
/* Policy Module State */
|
||||
#define ME_HFS2_STATE_POLICY_ENTRY 0
|
||||
#define ME_HFS2_STATE_POLICY_RCVD_S3 3
|
||||
#define ME_HFS2_STATE_POLICY_RCVD_S4 4
|
||||
#define ME_HFS2_STATE_POLICY_RCVD_S5 5
|
||||
#define ME_HFS2_STATE_POLICY_RCVD_UPD 6
|
||||
#define ME_HFS2_STATE_POLICY_RCVD_PCR 7
|
||||
#define ME_HFS2_STATE_POLICY_RCVD_NPCR 8
|
||||
#define ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9
|
||||
#define ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa
|
||||
#define ME_HFS2_STATE_POLICY_RCVD_DID 0xb
|
||||
#define ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc
|
||||
#define ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd
|
||||
#define ME_HFS2_STATE_POLICY_FPB_ERR 0xe
|
||||
#define ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf
|
||||
#define ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10
|
||||
/* Current PM Event Values */
|
||||
#define ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0
|
||||
#define ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1
|
||||
#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2
|
||||
#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3
|
||||
#define ME_HFS2_PMEVENT_CLEAN_ME_RESET 4
|
||||
#define ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5
|
||||
#define ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6
|
||||
#define ME_HFS2_PMEVENT_S0MO_SXM3 7
|
||||
#define ME_HFS2_PMEVENT_SXM3_S0M0 8
|
||||
#define ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9
|
||||
#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa
|
||||
#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb
|
||||
#define ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc
|
||||
|
||||
struct me_hfs2 {
|
||||
u32 bist_in_progress:1;
|
||||
u32 reserved1:2;
|
||||
u32 invoke_mebx:1;
|
||||
u32 cpu_replaced_sts:1;
|
||||
u32 mbp_rdy:1;
|
||||
u32 mfs_failure:1;
|
||||
u32 warm_reset_request:1;
|
||||
u32 cpu_replaced_valid:1;
|
||||
u32 reserved2:4;
|
||||
u32 mbp_cleared:1;
|
||||
u32 reserved3:2;
|
||||
u32 current_state:8;
|
||||
u32 current_pmevent:4;
|
||||
u32 progress_code:4;
|
||||
} __packed;
|
||||
|
||||
#define PCI_ME_HFS5 0x68
|
||||
|
||||
#define PCI_ME_H_GS2 0x70
|
||||
#define PCI_ME_MBP_GIVE_UP 0x01
|
||||
|
||||
/* ICC Messages */
|
||||
#define ICC_SET_CLOCK_ENABLES 0x3
|
||||
#define ICC_API_VERSION_LYNXPOINT 0x00030000
|
||||
|
||||
struct icc_header {
|
||||
u32 api_version;
|
||||
u32 icc_command;
|
||||
u32 icc_status;
|
||||
u32 length;
|
||||
u32 reserved;
|
||||
} __packed;
|
||||
|
||||
struct icc_clock_enables_msg {
|
||||
u32 clock_enables;
|
||||
u32 clock_mask;
|
||||
u32 no_response:1;
|
||||
u32 reserved:31;
|
||||
} __packed;
|
||||
|
||||
/*
|
||||
* ME to BIOS Payload Datastructures and definitions. The ordering of the
|
||||
* structures follows the ordering in the ME9 BWG.
|
||||
*/
|
||||
|
||||
#define MBP_APPID_KERNEL 1
|
||||
#define MBP_APPID_INTEL_AT 3
|
||||
#define MBP_APPID_HWA 4
|
||||
#define MBP_APPID_ICC 5
|
||||
#define MBP_APPID_NFC 6
|
||||
/* Kernel items: */
|
||||
#define MBP_KERNEL_FW_VER_ITEM 1
|
||||
#define MBP_KERNEL_FW_CAP_ITEM 2
|
||||
#define MBP_KERNEL_ROM_BIST_ITEM 3
|
||||
#define MBP_KERNEL_PLAT_KEY_ITEM 4
|
||||
#define MBP_KERNEL_FW_TYPE_ITEM 5
|
||||
#define MBP_KERNEL_MFS_FAILURE_ITEM 6
|
||||
#define MBP_KERNEL_PLAT_TIME_ITEM 7
|
||||
/* Intel AT items: */
|
||||
#define MBP_INTEL_AT_STATE_ITEM 1
|
||||
/* ICC Items: */
|
||||
#define MBP_ICC_PROFILE_ITEM 1
|
||||
/* HWA Items: */
|
||||
#define MBP_HWA_REQUEST_ITEM 1
|
||||
/* NFC Items: */
|
||||
#define MBP_NFC_SUPPORT_DATA_ITEM 1
|
||||
|
||||
#define MBP_MAKE_IDENT(appid, item) ((appid << 8) | item)
|
||||
#define MBP_IDENT(appid, item) \
|
||||
MBP_MAKE_IDENT(MBP_APPID_##appid, MBP_##appid##_##item##_ITEM)
|
||||
|
||||
struct mbp_fw_version_name {
|
||||
u32 major_version:16;
|
||||
u32 minor_version:16;
|
||||
u32 hotfix_version:16;
|
||||
u32 build_version:16;
|
||||
} __packed;
|
||||
|
||||
struct icc_address_mask {
|
||||
u16 icc_start_address;
|
||||
u16 mask;
|
||||
} __packed;
|
||||
|
||||
struct mbp_icc_profile {
|
||||
u8 num_icc_profiles;
|
||||
u8 icc_profile_soft_strap;
|
||||
u8 icc_profile_index;
|
||||
u8 reserved;
|
||||
u32 icc_reg_bundles;
|
||||
struct icc_address_mask icc_address_mask[0];
|
||||
} __packed;
|
||||
|
||||
struct me_bios_payload {
|
||||
struct mbp_fw_version_name *fw_version_name;
|
||||
struct mbp_mefwcaps *fw_capabilities;
|
||||
struct mbp_rom_bist_data *rom_bist_data;
|
||||
struct mbp_platform_key *platform_key;
|
||||
struct mbp_plat_type *fw_plat_type;
|
||||
struct mbp_icc_profile *icc_profile;
|
||||
struct mbp_at_state *at_state;
|
||||
u32 *mfsintegrity;
|
||||
struct mbp_plat_time *plat_time;
|
||||
struct mbp_nfc_data *nfc_data;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* Copyright (c) 2016 Google, Inc
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef __asm_arch_rcba_h
|
||||
#define __asm_arch_rcba_h
|
||||
|
||||
#define PMSYNC_CONFIG 0x33c4 /* 32bit */
|
||||
#define PMSYNC_CONFIG2 0x33cc /* 32bit */
|
||||
|
||||
#define DEEP_S3_POL 0x3328 /* 32bit */
|
||||
#define DEEP_S3_EN_AC (1 << 0)
|
||||
#define DEEP_S3_EN_DC (1 << 1)
|
||||
#define DEEP_S5_POL 0x3330 /* 32bit */
|
||||
#define DEEP_S5_EN_AC (1 << 14)
|
||||
#define DEEP_S5_EN_DC (1 << 15)
|
||||
#define DEEP_SX_CONFIG 0x3334 /* 32bit */
|
||||
#define DEEP_SX_WAKE_PIN_EN (1 << 2)
|
||||
#define DEEP_SX_ACPRESENT_PD (1 << 1)
|
||||
#define DEEP_SX_GP27_PIN_EN (1 << 0)
|
||||
#define PMSYNC_CONFIG 0x33c4 /* 32bit */
|
||||
#define PMSYNC_CONFIG2 0x33cc /* 32bit */
|
||||
|
||||
#define RC 0x3400 /* 32bit */
|
||||
#define HPTC 0x3404 /* 32bit */
|
||||
#define GCS 0x3410 /* 32bit */
|
||||
#define BUC 0x3414 /* 32bit */
|
||||
#define PCH_DISABLE_GBE (1 << 5)
|
||||
#define FD 0x3418 /* 32bit */
|
||||
#define FDSW 0x3420 /* 8bit */
|
||||
#define DISPBDF 0x3424 /* 16bit */
|
||||
#define FD2 0x3428 /* 32bit */
|
||||
#define CG 0x341c /* 32bit */
|
||||
|
||||
/* Function Disable 1 RCBA 0x3418 */
|
||||
#define PCH_DISABLE_ALWAYS (1 << 0)
|
||||
#define PCH_DISABLE_ADSPD (1 << 1)
|
||||
#define PCH_DISABLE_SATA1 (1 << 2)
|
||||
#define PCH_DISABLE_SMBUS (1 << 3)
|
||||
#define PCH_DISABLE_HD_AUDIO (1 << 4)
|
||||
#define PCH_DISABLE_EHCI2 (1 << 13)
|
||||
#define PCH_DISABLE_LPC (1 << 14)
|
||||
#define PCH_DISABLE_EHCI1 (1 << 15)
|
||||
#define PCH_DISABLE_PCIE(x) (1 << (16 + x))
|
||||
#define PCH_DISABLE_THERMAL (1 << 24)
|
||||
#define PCH_DISABLE_SATA2 (1 << 25)
|
||||
#define PCH_DISABLE_XHCI (1 << 27)
|
||||
|
||||
/* Function Disable 2 RCBA 0x3428 */
|
||||
#define PCH_DISABLE_KT (1 << 4)
|
||||
#define PCH_DISABLE_IDER (1 << 3)
|
||||
#define PCH_DISABLE_MEI2 (1 << 2)
|
||||
#define PCH_DISABLE_MEI1 (1 << 1)
|
||||
#define PCH_ENABLE_DBDF (1 << 0)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Copyright (C) 2014 Google Inc.
|
||||
*
|
||||
* This file is from coreboot soc/intel/broadwell/include/soc/spi.h
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef _BROADWELL_SPI_H_
|
||||
#define _BROADWELL_SPI_H_
|
||||
|
||||
/*
|
||||
* SPI Opcode Menu setup for SPIBAR lockdown
|
||||
* should support most common flash chips.
|
||||
*/
|
||||
|
||||
#define SPIBAR_OFFSET 0x3800
|
||||
#define SPI_REG(x) (RCB_REG(SPIBAR_OFFSET + (x)))
|
||||
|
||||
/* Reigsters within the SPIBAR */
|
||||
#define SPIBAR_SSFC 0x91
|
||||
#define SPIBAR_FDOC 0xb0
|
||||
#define SPIBAR_FDOD 0xb4
|
||||
|
||||
#define SPIBAR_PREOP 0x94
|
||||
#define SPIBAR_OPTYPE 0x96
|
||||
#define SPIBAR_OPMENU_LOWER 0x98
|
||||
#define SPIBAR_OPMENU_UPPER 0x9c
|
||||
|
||||
#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
|
||||
#define SPI_OPTYPE_0 0x01 /* Write, no address */
|
||||
|
||||
#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
|
||||
#define SPI_OPTYPE_1 0x03 /* Write, address required */
|
||||
|
||||
#define SPI_OPMENU_2 0x03 /* READ: Read Data */
|
||||
#define SPI_OPTYPE_2 0x02 /* Read, address required */
|
||||
|
||||
#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
|
||||
#define SPI_OPTYPE_3 0x00 /* Read, no address */
|
||||
|
||||
#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
|
||||
#define SPI_OPTYPE_4 0x03 /* Write, address required */
|
||||
|
||||
#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
|
||||
#define SPI_OPTYPE_5 0x00 /* Read, no address */
|
||||
|
||||
#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
|
||||
#define SPI_OPTYPE_6 0x03 /* Write, address required */
|
||||
|
||||
#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
|
||||
#define SPI_OPTYPE_7 0x02 /* Read, address required */
|
||||
|
||||
#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
|
||||
(SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
|
||||
#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
|
||||
(SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
|
||||
|
||||
#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
|
||||
(SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
|
||||
(SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
|
||||
(SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
|
||||
|
||||
#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
|
||||
|
||||
#define SPIBAR_HSFS 0x04 /* SPI hardware sequence status */
|
||||
#define SPIBAR_HSFS_FLOCKDN (1 << 15)/* Flash Configuration Lock-Down */
|
||||
#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */
|
||||
#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */
|
||||
#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */
|
||||
#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */
|
||||
#define SPIBAR_HSFC 0x06 /* SPI hardware sequence control */
|
||||
#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8)
|
||||
#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */
|
||||
#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */
|
||||
#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */
|
||||
#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */
|
||||
#define SPIBAR_FADDR 0x08 /* SPI flash address */
|
||||
#define SPIBAR_FDATA(n) (0x10 + (4 * n)) /* SPI flash data */
|
||||
#define SPIBAR_SSFS 0x90
|
||||
#define SPIBAR_SSFS_ERROR (1 << 3)
|
||||
#define SPIBAR_SSFS_DONE (1 << 2)
|
||||
#define SPIBAR_SSFC 0x91
|
||||
#define SPIBAR_SSFC_DATA (1 << 14)
|
||||
#define SPIBAR_SSFC_GO (1 << 1)
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue